target/linux/generic/backport-5.10/747-v5.16-03-net-dsa-qca8k-add-support-for-sgmii-falling-edge.patch

   1 From 6c43809bf1bee76c434e365a26546a92a5fbec14 Mon Sep 17 00:00:00 2001
   2 From: Ansuel Smith <ansuelsmth@gmail.com>
   3 Date: Thu, 14 Oct 2021 00:39:08 +0200
   4 Subject: net: dsa: qca8k: add support for sgmii falling edge
   5
   6 Add support for this in the qca8k driver. Also add support for SGMII
   7 rx/tx clock falling edge. This is only present for pad0, pad5 and
   8 pad6 have these bit reserved from Documentation. Add a comment that this
   9 is hardcoded to PAD0 as qca8327/28/34/37 have an unique sgmii line and
  10 setting falling in port0 applies to both configuration with sgmii used
  11 for port0 or port6.
  12
  13 Co-developed-by: Matthew Hagan <mnhagan88@gmail.com>
  14 Signed-off-by: Matthew Hagan <mnhagan88@gmail.com>
  15 Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
  16 Signed-off-by: David S. Miller <davem@davemloft.net>
  17 ---
  18  drivers/net/dsa/qca8k.c | 63 +++++++++++++++++++++++++++++++++++++++++++++++++
  19  drivers/net/dsa/qca8k.h |  4 ++++
  20  2 files changed, 67 insertions(+)
  21
  22 --- a/drivers/net/dsa/qca8k.c
  23 +++ b/drivers/net/dsa/qca8k.c
  24 @@ -978,6 +978,42 @@ qca8k_setup_mac_pwr_sel(struct qca8k_pri
  25  }
  26
  27  static int
  28 +qca8k_parse_port_config(struct qca8k_priv *priv)
  29 +{
  30 +       struct device_node *port_dn;
  31 +       phy_interface_t mode;
  32 +       struct dsa_port *dp;
  33 +       int port, ret;
  34 +
  35 +       /* We have 2 CPU port. Check them */
  36 +       for (port = 0; port < QCA8K_NUM_PORTS; port++) {
  37 +               /* Skip every other port */
  38 +               if (port != 0 && port != 6)
  39 +                       continue;
  40 +
  41 +               dp = dsa_to_port(priv->ds, port);
  42 +               port_dn = dp->dn;
  43 +
  44 +               if (!of_device_is_available(port_dn))
  45 +                       continue;
  46 +
  47 +               ret = of_get_phy_mode(port_dn, &mode);
  48 +               if (ret)
  49 +                       continue;
  50 +
  51 +               if (mode == PHY_INTERFACE_MODE_SGMII) {
  52 +                       if (of_property_read_bool(port_dn, "qca,sgmii-txclk-falling-edge"))
  53 +                               priv->sgmii_tx_clk_falling_edge = true;
  54 +
  55 +                       if (of_property_read_bool(port_dn, "qca,sgmii-rxclk-falling-edge"))
  56 +                               priv->sgmii_rx_clk_falling_edge = true;
  57 +               }
  58 +       }
  59 +
  60 +       return 0;
  61 +}
  62 +
  63 +static int
  64  qca8k_setup(struct dsa_switch *ds)
  65  {
  66         struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
  67 @@ -990,6 +1026,11 @@ qca8k_setup(struct dsa_switch *ds)
  68                 return -EINVAL;
  69         }
  70
  71 +       /* Parse CPU port config to be later used in phy_link mac_config */
  72 +       ret = qca8k_parse_port_config(priv);
  73 +       if (ret)
  74 +               return ret;
  75 +
  76         mutex_init(&priv->reg_mutex);
  77
  78         /* Start by setting up the register mapping */
  79 @@ -1274,6 +1315,28 @@ qca8k_phylink_mac_config(struct dsa_swit
  80                 }
  81
  82                 qca8k_write(priv, QCA8K_REG_SGMII_CTRL, val);
  83 +
  84 +               /* For qca8327/qca8328/qca8334/qca8338 sgmii is unique and
  85 +                * falling edge is set writing in the PORT0 PAD reg
  86 +                */
  87 +               if (priv->switch_id == QCA8K_ID_QCA8327 ||
  88 +                   priv->switch_id == QCA8K_ID_QCA8337)
  89 +                       reg = QCA8K_REG_PORT0_PAD_CTRL;
  90 +
  91 +               val = 0;
  92 +
  93 +               /* SGMII Clock phase configuration */
  94 +               if (priv->sgmii_rx_clk_falling_edge)
  95 +                       val |= QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE;
  96 +
  97 +               if (priv->sgmii_tx_clk_falling_edge)
  98 +                       val |= QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE;
  99 +
 100 +               if (val)
 101 +                       ret = qca8k_rmw(priv, reg,
 102 +                                       QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE |
 103 +                                       QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE,
 104 +                                       val);
 105                 break;
 106         default:
 107                 dev_err(ds->dev, "xMII mode %s not supported for port %d\n",
 108 --- a/drivers/net/dsa/qca8k.h
 109 +++ b/drivers/net/dsa/qca8k.h
 110 @@ -35,6 +35,8 @@
 111  #define   QCA8K_MASK_CTRL_DEVICE_ID_MASK               GENMASK(15, 8)
 112  #define   QCA8K_MASK_CTRL_DEVICE_ID(x)                 ((x) >> 8)
 113  #define QCA8K_REG_PORT0_PAD_CTRL                       0x004
 114 +#define   QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE     BIT(19)
 115 +#define   QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE     BIT(18)
 116  #define QCA8K_REG_PORT5_PAD_CTRL                       0x008
 117  #define QCA8K_REG_PORT6_PAD_CTRL                       0x00c
 118  #define   QCA8K_PORT_PAD_RGMII_EN                      BIT(26)
 119 @@ -260,6 +262,8 @@ struct qca8k_priv {
 120         u8 switch_revision;
 121         u8 rgmii_tx_delay;
 122         u8 rgmii_rx_delay;
 123 +       bool sgmii_rx_clk_falling_edge;
 124 +       bool sgmii_tx_clk_falling_edge;
 125         bool legacy_phy_port_mapping;
 126         struct regmap *regmap;
 127         struct mii_bus *bus;