kernel: fix mtk_eth_soc throughput regressions on gigabit PHY ports
[openwrt/openwrt.git] / target / linux / generic / backport-5.15 / 345-v5.17-arm64-dts-marvell-armada-37xx-Add-xtal-clock-to-comp.patch
1 From 73a78b6130d9e13daca22b86ad52f063b9403e03 Mon Sep 17 00:00:00 2001
2 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>
3 Date: Wed, 8 Dec 2021 03:40:35 +0100
4 Subject: [PATCH 1/1] arm64: dts: marvell: armada-37xx: Add xtal clock to
5 comphy node
6 MIME-Version: 1.0
7 Content-Type: text/plain; charset=UTF-8
8 Content-Transfer-Encoding: 8bit
9
10 Kernel driver phy-mvebu-a3700-comphy.c needs to know the rate of the
11 reference xtal clock. So add missing xtal clock source into comphy device
12 tree node. If the property is not present, the driver defaults to 25 MHz
13 xtal rate (which, as far as we know, is used by all the existing boards).
14
15 Signed-off-by: Pali Rohár <pali@kernel.org>
16 Signed-off-by: Marek Behún <kabel@kernel.org>
17 Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
18 ---
19 arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 2 ++
20 1 file changed, 2 insertions(+)
21
22 --- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
23 +++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
24 @@ -265,6 +265,8 @@
25 "lane2_sata_usb3";
26 #address-cells = <1>;
27 #size-cells = <0>;
28 + clocks = <&xtalclk>;
29 + clock-names = "xtal";
30
31 comphy0: phy@0 {
32 reg = <0>;