target/linux/generic/backport-5.15/704-09-v5.19-net-mtk_eth_soc-add-mask-and-update-PCS-speed-defini.patch

   1 From bc5e93e0cd22e360eda23859b939280205567580 Mon Sep 17 00:00:00 2001
   2 From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
   3 Date: Wed, 18 May 2022 15:54:42 +0100
   4 Subject: [PATCH 03/12] net: mtk_eth_soc: add mask and update PCS speed
   5  definitions
   6
   7 The PCS speed setting is a two bit field, but it is defined as two
   8 separate bits. Add a bitfield mask for the speed definitions, an
   9  use the FIELD_PREP() macro to define each PCS speed.
  10
  11 Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
  12 Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  13 ---
  14  drivers/net/ethernet/mediatek/mtk_eth_soc.h | 8 +++++---
  15  1 file changed, 5 insertions(+), 3 deletions(-)
  16
  17 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
  18 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
  19 @@ -17,6 +17,7 @@
  20  #include <linux/phylink.h>
  21  #include <linux/rhashtable.h>
  22  #include <linux/dim.h>
  23 +#include <linux/bitfield.h>
  24  #include "mtk_ppe.h"
  25
  26  #define MTK_QDMA_PAGE_SIZE     2048
  27 @@ -473,9 +474,10 @@
  28  #define SGMSYS_SGMII_MODE              0x20
  29  #define SGMII_IF_MODE_BIT0             BIT(0)
  30  #define SGMII_SPEED_DUPLEX_AN          BIT(1)
  31 -#define SGMII_SPEED_10                 0x0
  32 -#define SGMII_SPEED_100                        BIT(2)
  33 -#define SGMII_SPEED_1000               BIT(3)
  34 +#define SGMII_SPEED_MASK               GENMASK(3, 2)
  35 +#define SGMII_SPEED_10                 FIELD_PREP(SGMII_SPEED_MASK, 0)
  36 +#define SGMII_SPEED_100                        FIELD_PREP(SGMII_SPEED_MASK, 1)
  37 +#define SGMII_SPEED_1000               FIELD_PREP(SGMII_SPEED_MASK, 2)
  38  #define SGMII_DUPLEX_FULL              BIT(4)
  39  #define SGMII_IF_MODE_BIT5             BIT(5)
  40  #define SGMII_REMOTE_FAULT_DIS         BIT(8)