target/linux/generic/backport-6.1/733-v6.3-18-net-ethernet-mtk_eth_soc-add-support-for-MT7981.patch

   1 From f5d43ddd334b7c32fcaed9ba46afbd85cb467f1f Mon Sep 17 00:00:00 2001
   2 From: Daniel Golle <daniel@makrotopia.org>
   3 Date: Sun, 19 Mar 2023 12:56:28 +0000
   4 Subject: [PATCH] net: ethernet: mtk_eth_soc: add support for MT7981 SoC
   5
   6 The MediaTek MT7981 SoC comes with two 1G/2.5G SGMII ports, just like
   7 MT7986.
   8
   9 In addition MT7981 is equipped with a built-in 1000Base-T PHY which can
  10 be used with GMAC1.
  11
  12 As many MT7981 boards make use of inverting SGMII signal polarity, add
  13 new device-tree attribute 'mediatek,pn_swap' to support them.
  14
  15 Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  16 Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  17
  18 --- a/drivers/net/ethernet/mediatek/mtk_eth_path.c
  19 +++ b/drivers/net/ethernet/mediatek/mtk_eth_path.c
  20 @@ -96,12 +96,20 @@ static int set_mux_gmac2_gmac0_to_gephy(
  21
  22  static int set_mux_u3_gmac2_to_qphy(struct mtk_eth *eth, int path)
  23  {
  24 -       unsigned int val = 0;
  25 +       unsigned int val = 0, mask = 0, reg = 0;
  26         bool updated = true;
  27
  28         switch (path) {
  29         case MTK_ETH_PATH_GMAC2_SGMII:
  30 -               val = CO_QPHY_SEL;
  31 +               if (MTK_HAS_CAPS(eth->soc->caps, MTK_U3_COPHY_V2)) {
  32 +                       reg = USB_PHY_SWITCH_REG;
  33 +                       val = SGMII_QPHY_SEL;
  34 +                       mask = QPHY_SEL_MASK;
  35 +               } else {
  36 +                       reg = INFRA_MISC2;
  37 +                       val = CO_QPHY_SEL;
  38 +                       mask = val;
  39 +               }
  40                 break;
  41         default:
  42                 updated = false;
  43 @@ -109,7 +117,7 @@ static int set_mux_u3_gmac2_to_qphy(stru
  44         }
  45
  46         if (updated)
  47 -               regmap_update_bits(eth->infra, INFRA_MISC2, CO_QPHY_SEL, val);
  48 +               regmap_update_bits(eth->infra, reg, mask, val);
  49
  50         dev_dbg(eth->dev, "path %s in %s updated = %d\n",
  51                 mtk_eth_path_name(path), __func__, updated);
  52 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
  53 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
  54 @@ -4801,6 +4801,26 @@ static const struct mtk_soc_data mt7629_
  55         },
  56  };
  57
  58 +static const struct mtk_soc_data mt7981_data = {
  59 +       .reg_map = &mt7986_reg_map,
  60 +       .ana_rgc3 = 0x128,
  61 +       .caps = MT7981_CAPS,
  62 +       .hw_features = MTK_HW_FEATURES,
  63 +       .required_clks = MT7981_CLKS_BITMAP,
  64 +       .required_pctl = false,
  65 +       .offload_version = 2,
  66 +       .hash_offset = 4,
  67 +       .foe_entry_size = sizeof(struct mtk_foe_entry),
  68 +       .txrx = {
  69 +               .txd_size = sizeof(struct mtk_tx_dma_v2),
  70 +               .rxd_size = sizeof(struct mtk_rx_dma_v2),
  71 +               .rx_irq_done_mask = MTK_RX_DONE_INT_V2,
  72 +               .rx_dma_l4_valid = RX_DMA_L4_VALID_V2,
  73 +               .dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
  74 +               .dma_len_offset = 8,
  75 +       },
  76 +};
  77 +
  78  static const struct mtk_soc_data mt7986_data = {
  79         .reg_map = &mt7986_reg_map,
  80         .ana_rgc3 = 0x128,
  81 @@ -4842,6 +4862,7 @@ const struct of_device_id of_mtk_match[]
  82         { .compatible = "mediatek,mt7622-eth", .data = &mt7622_data},
  83         { .compatible = "mediatek,mt7623-eth", .data = &mt7623_data},
  84         { .compatible = "mediatek,mt7629-eth", .data = &mt7629_data},
  85 +       { .compatible = "mediatek,mt7981-eth", .data = &mt7981_data},
  86         { .compatible = "mediatek,mt7986-eth", .data = &mt7986_data},
  87         { .compatible = "ralink,rt5350-eth", .data = &rt5350_data},
  88         {},
  89 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
  90 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
  91 @@ -556,11 +556,22 @@
  92  #define SGMSYS_QPHY_PWR_STATE_CTRL 0xe8
  93  #define        SGMII_PHYA_PWD          BIT(4)
  94
  95 +/* Register to QPHY wrapper control */
  96 +#define SGMSYS_QPHY_WRAP_CTRL  0xec
  97 +#define SGMII_PN_SWAP_MASK     GENMASK(1, 0)
  98 +#define SGMII_PN_SWAP_TX_RX    (BIT(0) | BIT(1))
  99 +#define MTK_SGMII_FLAG_PN_SWAP BIT(0)
 100 +
 101  /* Infrasys subsystem config registers */
 102  #define INFRA_MISC2            0x70c
 103  #define CO_QPHY_SEL            BIT(0)
 104  #define GEPHY_MAC_SEL          BIT(1)
 105
 106 +/* Top misc registers */
 107 +#define USB_PHY_SWITCH_REG     0x218
 108 +#define QPHY_SEL_MASK          GENMASK(1, 0)
 109 +#define SGMII_QPHY_SEL         0x2
 110 +
 111  /* MT7628/88 specific stuff */
 112  #define MT7628_PDMA_OFFSET     0x0800
 113  #define MT7628_SDM_OFFSET      0x0c00
 114 @@ -741,6 +752,17 @@ enum mtk_clks_map {
 115                                  BIT(MTK_CLK_SGMII2_CDR_FB) | \
 116                                  BIT(MTK_CLK_SGMII_CK) | \
 117                                  BIT(MTK_CLK_ETH2PLL) | BIT(MTK_CLK_SGMIITOP))
 118 +#define MT7981_CLKS_BITMAP     (BIT(MTK_CLK_FE) | BIT(MTK_CLK_GP2) | BIT(MTK_CLK_GP1) | \
 119 +                                BIT(MTK_CLK_WOCPU0) | \
 120 +                                BIT(MTK_CLK_SGMII_TX_250M) | \
 121 +                                BIT(MTK_CLK_SGMII_RX_250M) | \
 122 +                                BIT(MTK_CLK_SGMII_CDR_REF) | \
 123 +                                BIT(MTK_CLK_SGMII_CDR_FB) | \
 124 +                                BIT(MTK_CLK_SGMII2_TX_250M) | \
 125 +                                BIT(MTK_CLK_SGMII2_RX_250M) | \
 126 +                                BIT(MTK_CLK_SGMII2_CDR_REF) | \
 127 +                                BIT(MTK_CLK_SGMII2_CDR_FB) | \
 128 +                                BIT(MTK_CLK_SGMII_CK))
 129  #define MT7986_CLKS_BITMAP     (BIT(MTK_CLK_FE) | BIT(MTK_CLK_GP2) | BIT(MTK_CLK_GP1) | \
 130                                  BIT(MTK_CLK_WOCPU1) | BIT(MTK_CLK_WOCPU0) | \
 131                                  BIT(MTK_CLK_SGMII_TX_250M) | \
 132 @@ -854,6 +876,7 @@ enum mkt_eth_capabilities {
 133         MTK_NETSYS_V2_BIT,
 134         MTK_SOC_MT7628_BIT,
 135         MTK_RSTCTRL_PPE1_BIT,
 136 +       MTK_U3_COPHY_V2_BIT,
 137
 138         /* MUX BITS*/
 139         MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT,
 140 @@ -888,6 +911,7 @@ enum mkt_eth_capabilities {
 141  #define MTK_NETSYS_V2          BIT(MTK_NETSYS_V2_BIT)
 142  #define MTK_SOC_MT7628         BIT(MTK_SOC_MT7628_BIT)
 143  #define MTK_RSTCTRL_PPE1       BIT(MTK_RSTCTRL_PPE1_BIT)
 144 +#define MTK_U3_COPHY_V2                BIT(MTK_U3_COPHY_V2_BIT)
 145
 146  #define MTK_ETH_MUX_GDM1_TO_GMAC1_ESW          \
 147         BIT(MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT)
 148 @@ -966,6 +990,11 @@ enum mkt_eth_capabilities {
 149                       MTK_MUX_U3_GMAC2_TO_QPHY | \
 150                       MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA)
 151
 152 +#define MT7981_CAPS  (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | MTK_GMAC2_GEPHY | \
 153 +                     MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \
 154 +                     MTK_MUX_U3_GMAC2_TO_QPHY | MTK_U3_COPHY_V2 | \
 155 +                     MTK_NETSYS_V2 | MTK_RSTCTRL_PPE1)
 156 +
 157  #define MT7986_CAPS  (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | \
 158                       MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \
 159                       MTK_NETSYS_V2 | MTK_RSTCTRL_PPE1)
 160 @@ -1079,12 +1108,14 @@ struct mtk_soc_data {
 161   * @ana_rgc3:          The offset refers to register ANA_RGC3 related to regmap
 162   * @interface:         Currently configured interface mode
 163   * @pcs:               Phylink PCS structure
 164 + * @flags:             Flags indicating hardware properties
 165   */
 166  struct mtk_pcs {
 167         struct regmap   *regmap;
 168         u32             ana_rgc3;
 169         phy_interface_t interface;
 170         struct phylink_pcs pcs;
 171 +       u32             flags;
 172  };
 173
 174  /* struct mtk_sgmii -  This is the structure holding sgmii regmap and its
 175 --- a/drivers/net/ethernet/mediatek/mtk_sgmii.c
 176 +++ b/drivers/net/ethernet/mediatek/mtk_sgmii.c
 177 @@ -87,6 +87,11 @@ static int mtk_pcs_config(struct phylink
 178                 regmap_update_bits(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL,
 179                                    SGMII_PHYA_PWD, SGMII_PHYA_PWD);
 180
 181 +               if (mpcs->flags & MTK_SGMII_FLAG_PN_SWAP)
 182 +                       regmap_update_bits(mpcs->regmap, SGMSYS_QPHY_WRAP_CTRL,
 183 +                                          SGMII_PN_SWAP_MASK,
 184 +                                          SGMII_PN_SWAP_TX_RX);
 185 +
 186                 /* Reset SGMII PCS state */
 187                 regmap_update_bits(mpcs->regmap, SGMII_RESERVED_0,
 188                                    SGMII_SW_RESET, SGMII_SW_RESET);
 189 @@ -186,6 +191,11 @@ int mtk_sgmii_init(struct mtk_sgmii *ss,
 190
 191                 ss->pcs[i].ana_rgc3 = ana_rgc3;
 192                 ss->pcs[i].regmap = syscon_node_to_regmap(np);
 193 +
 194 +               ss->pcs[i].flags = 0;
 195 +               if (of_property_read_bool(np, "mediatek,pnswap"))
 196 +                       ss->pcs[i].flags |= MTK_SGMII_FLAG_PN_SWAP;
 197 +
 198                 of_node_put(np);
 199                 if (IS_ERR(ss->pcs[i].regmap))
 200                         return PTR_ERR(ss->pcs[i].regmap);