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odhcpd: send current hop-limit by default in RAs
[openwrt/openwrt.git] / target / linux / generic / patches-3.10 / 025-bcma_backport.patch
1 --- a/drivers/bcma/Kconfig
2 +++ b/drivers/bcma/Kconfig
3 @@ -26,6 +26,7 @@ config BCMA_HOST_PCI_POSSIBLE
4 config BCMA_HOST_PCI
5 bool "Support for BCMA on PCI-host bus"
6 depends on BCMA_HOST_PCI_POSSIBLE
7 + default y
8
9 config BCMA_DRIVER_PCI_HOSTMODE
10 bool "Driver for PCI core working in hostmode"
11 @@ -34,8 +35,14 @@ config BCMA_DRIVER_PCI_HOSTMODE
12 PCI core hostmode operation (external PCI bus).
13
14 config BCMA_HOST_SOC
15 - bool
16 - depends on BCMA_DRIVER_MIPS
17 + bool "Support for BCMA in a SoC"
18 + depends on BCMA
19 + help
20 + Host interface for a Broadcom AIX bus directly mapped into
21 + the memory. This only works with the Broadcom SoCs from the
22 + BCM47XX line.
23 +
24 + If unsure, say N
25
26 config BCMA_DRIVER_MIPS
27 bool "BCMA Broadcom MIPS core driver"
28 @@ -68,6 +75,7 @@ config BCMA_DRIVER_GMAC_CMN
29 config BCMA_DRIVER_GPIO
30 bool "BCMA GPIO driver"
31 depends on BCMA && GPIOLIB
32 + select IRQ_DOMAIN if BCMA_HOST_SOC
33 help
34 Driver to provide access to the GPIO pins of the bcma bus.
35
36 --- a/drivers/bcma/Makefile
37 +++ b/drivers/bcma/Makefile
38 @@ -1,8 +1,10 @@
39 bcma-y += main.o scan.o core.o sprom.o
40 bcma-y += driver_chipcommon.o driver_chipcommon_pmu.o
41 +bcma-y += driver_chipcommon_b.o
42 bcma-$(CONFIG_BCMA_SFLASH) += driver_chipcommon_sflash.o
43 bcma-$(CONFIG_BCMA_NFLASH) += driver_chipcommon_nflash.o
44 bcma-y += driver_pci.o
45 +bcma-y += driver_pcie2.o
46 bcma-$(CONFIG_BCMA_DRIVER_PCI_HOSTMODE) += driver_pci_host.o
47 bcma-$(CONFIG_BCMA_DRIVER_MIPS) += driver_mips.o
48 bcma-$(CONFIG_BCMA_DRIVER_GMAC_CMN) += driver_gmac_cmn.o
49 --- a/drivers/bcma/bcma_private.h
50 +++ b/drivers/bcma/bcma_private.h
51 @@ -22,6 +22,9 @@
52 struct bcma_bus;
53
54 /* main.c */
55 +bool bcma_wait_value(struct bcma_device *core, u16 reg, u32 mask, u32 value,
56 + int timeout);
57 +void bcma_prepare_core(struct bcma_bus *bus, struct bcma_device *core);
58 int bcma_bus_register(struct bcma_bus *bus);
59 void bcma_bus_unregister(struct bcma_bus *bus);
60 int __init bcma_bus_early_register(struct bcma_bus *bus,
61 @@ -31,8 +34,6 @@ int __init bcma_bus_early_register(struc
62 int bcma_bus_suspend(struct bcma_bus *bus);
63 int bcma_bus_resume(struct bcma_bus *bus);
64 #endif
65 -struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
66 - u8 unit);
67
68 /* scan.c */
69 int bcma_bus_scan(struct bcma_bus *bus);
70 @@ -50,6 +51,10 @@ void bcma_chipco_serial_init(struct bcma
71 extern struct platform_device bcma_pflash_dev;
72 #endif /* CONFIG_BCMA_DRIVER_MIPS */
73
74 +/* driver_chipcommon_b.c */
75 +int bcma_core_chipcommon_b_init(struct bcma_drv_cc_b *ccb);
76 +void bcma_core_chipcommon_b_free(struct bcma_drv_cc_b *ccb);
77 +
78 /* driver_chipcommon_pmu.c */
79 u32 bcma_pmu_get_alp_clock(struct bcma_drv_cc *cc);
80 u32 bcma_pmu_get_cpu_clock(struct bcma_drv_cc *cc);
81 @@ -84,6 +89,20 @@ extern int __init bcma_host_pci_init(voi
82 extern void __exit bcma_host_pci_exit(void);
83 #endif /* CONFIG_BCMA_HOST_PCI */
84
85 +/* host_soc.c */
86 +#if defined(CONFIG_BCMA_HOST_SOC) && defined(CONFIG_OF)
87 +extern int __init bcma_host_soc_register_driver(void);
88 +extern void __exit bcma_host_soc_unregister_driver(void);
89 +#else
90 +static inline int __init bcma_host_soc_register_driver(void)
91 +{
92 + return 0;
93 +}
94 +static inline void __exit bcma_host_soc_unregister_driver(void)
95 +{
96 +}
97 +#endif /* CONFIG_BCMA_HOST_SOC && CONFIG_OF */
98 +
99 /* driver_pci.c */
100 u32 bcma_pcie_read(struct bcma_drv_pci *pc, u32 address);
101
102 --- a/drivers/bcma/core.c
103 +++ b/drivers/bcma/core.c
104 @@ -9,6 +9,25 @@
105 #include <linux/export.h>
106 #include <linux/bcma/bcma.h>
107
108 +static bool bcma_core_wait_value(struct bcma_device *core, u16 reg, u32 mask,
109 + u32 value, int timeout)
110 +{
111 + unsigned long deadline = jiffies + timeout;
112 + u32 val;
113 +
114 + do {
115 + val = bcma_aread32(core, reg);
116 + if ((val & mask) == value)
117 + return true;
118 + cpu_relax();
119 + udelay(10);
120 + } while (!time_after_eq(jiffies, deadline));
121 +
122 + bcma_warn(core->bus, "Timeout waiting for register 0x%04X!\n", reg);
123 +
124 + return false;
125 +}
126 +
127 bool bcma_core_is_enabled(struct bcma_device *core)
128 {
129 if ((bcma_aread32(core, BCMA_IOCTL) & (BCMA_IOCTL_CLK | BCMA_IOCTL_FGC))
130 @@ -25,13 +44,15 @@ void bcma_core_disable(struct bcma_devic
131 if (bcma_aread32(core, BCMA_RESET_CTL) & BCMA_RESET_CTL_RESET)
132 return;
133
134 - bcma_awrite32(core, BCMA_IOCTL, flags);
135 - bcma_aread32(core, BCMA_IOCTL);
136 - udelay(10);
137 + bcma_core_wait_value(core, BCMA_RESET_ST, ~0, 0, 300);
138
139 bcma_awrite32(core, BCMA_RESET_CTL, BCMA_RESET_CTL_RESET);
140 bcma_aread32(core, BCMA_RESET_CTL);
141 udelay(1);
142 +
143 + bcma_awrite32(core, BCMA_IOCTL, flags);
144 + bcma_aread32(core, BCMA_IOCTL);
145 + udelay(10);
146 }
147 EXPORT_SYMBOL_GPL(bcma_core_disable);
148
149 @@ -43,6 +64,7 @@ int bcma_core_enable(struct bcma_device
150 bcma_aread32(core, BCMA_IOCTL);
151
152 bcma_awrite32(core, BCMA_RESET_CTL, 0);
153 + bcma_aread32(core, BCMA_RESET_CTL);
154 udelay(1);
155
156 bcma_awrite32(core, BCMA_IOCTL, (BCMA_IOCTL_CLK | flags));
157 --- a/drivers/bcma/driver_chipcommon.c
158 +++ b/drivers/bcma/driver_chipcommon.c
159 @@ -140,8 +140,15 @@ void bcma_core_chipcommon_init(struct bc
160 bcma_core_chipcommon_early_init(cc);
161
162 if (cc->core->id.rev >= 20) {
163 - bcma_cc_write32(cc, BCMA_CC_GPIOPULLUP, 0);
164 - bcma_cc_write32(cc, BCMA_CC_GPIOPULLDOWN, 0);
165 + u32 pullup = 0, pulldown = 0;
166 +
167 + if (cc->core->bus->chipinfo.id == BCMA_CHIP_ID_BCM43142) {
168 + pullup = 0x402e0;
169 + pulldown = 0x20500;
170 + }
171 +
172 + bcma_cc_write32(cc, BCMA_CC_GPIOPULLUP, pullup);
173 + bcma_cc_write32(cc, BCMA_CC_GPIOPULLDOWN, pulldown);
174 }
175
176 if (cc->capabilities & BCMA_CC_CAP_PMU)
177 @@ -332,7 +339,7 @@ void bcma_chipco_serial_init(struct bcma
178 return;
179 }
180
181 - irq = bcma_core_irq(cc->core);
182 + irq = bcma_core_irq(cc->core, 0);
183
184 /* Determine the registers of the UARTs */
185 cc->nr_serial_ports = (cc->capabilities & BCMA_CC_CAP_NRUART);
186 --- a/drivers/bcma/driver_chipcommon_pmu.c
187 +++ b/drivers/bcma/driver_chipcommon_pmu.c
188 @@ -56,6 +56,109 @@ void bcma_chipco_regctl_maskset(struct b
189 }
190 EXPORT_SYMBOL_GPL(bcma_chipco_regctl_maskset);
191
192 +static u32 bcma_pmu_xtalfreq(struct bcma_drv_cc *cc)
193 +{
194 + u32 ilp_ctl, alp_hz;
195 +
196 + if (!(bcma_cc_read32(cc, BCMA_CC_PMU_STAT) &
197 + BCMA_CC_PMU_STAT_EXT_LPO_AVAIL))
198 + return 0;
199 +
200 + bcma_cc_write32(cc, BCMA_CC_PMU_XTAL_FREQ,
201 + BIT(BCMA_CC_PMU_XTAL_FREQ_MEASURE_SHIFT));
202 + usleep_range(1000, 2000);
203 +
204 + ilp_ctl = bcma_cc_read32(cc, BCMA_CC_PMU_XTAL_FREQ);
205 + ilp_ctl &= BCMA_CC_PMU_XTAL_FREQ_ILPCTL_MASK;
206 +
207 + bcma_cc_write32(cc, BCMA_CC_PMU_XTAL_FREQ, 0);
208 +
209 + alp_hz = ilp_ctl * 32768 / 4;
210 + return (alp_hz + 50000) / 100000 * 100;
211 +}
212 +
213 +static void bcma_pmu2_pll_init0(struct bcma_drv_cc *cc, u32 xtalfreq)
214 +{
215 + struct bcma_bus *bus = cc->core->bus;
216 + u32 freq_tgt_target = 0, freq_tgt_current;
217 + u32 pll0, mask;
218 +
219 + switch (bus->chipinfo.id) {
220 + case BCMA_CHIP_ID_BCM43142:
221 + /* pmu2_xtaltab0_adfll_485 */
222 + switch (xtalfreq) {
223 + case 12000:
224 + freq_tgt_target = 0x50D52;
225 + break;
226 + case 20000:
227 + freq_tgt_target = 0x307FE;
228 + break;
229 + case 26000:
230 + freq_tgt_target = 0x254EA;
231 + break;
232 + case 37400:
233 + freq_tgt_target = 0x19EF8;
234 + break;
235 + case 52000:
236 + freq_tgt_target = 0x12A75;
237 + break;
238 + }
239 + break;
240 + }
241 +
242 + if (!freq_tgt_target) {
243 + bcma_err(bus, "Unknown TGT frequency for xtalfreq %d\n",
244 + xtalfreq);
245 + return;
246 + }
247 +
248 + pll0 = bcma_chipco_pll_read(cc, BCMA_CC_PMU15_PLL_PLLCTL0);
249 + freq_tgt_current = (pll0 & BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK) >>
250 + BCMA_CC_PMU15_PLL_PC0_FREQTGT_SHIFT;
251 +
252 + if (freq_tgt_current == freq_tgt_target) {
253 + bcma_debug(bus, "Target TGT frequency already set\n");
254 + return;
255 + }
256 +
257 + /* Turn off PLL */
258 + switch (bus->chipinfo.id) {
259 + case BCMA_CHIP_ID_BCM43142:
260 + mask = (u32)~(BCMA_RES_4314_HT_AVAIL |
261 + BCMA_RES_4314_MACPHY_CLK_AVAIL);
262 +
263 + bcma_cc_mask32(cc, BCMA_CC_PMU_MINRES_MSK, mask);
264 + bcma_cc_mask32(cc, BCMA_CC_PMU_MAXRES_MSK, mask);
265 + bcma_wait_value(cc->core, BCMA_CLKCTLST,
266 + BCMA_CLKCTLST_HAVEHT, 0, 20000);
267 + break;
268 + }
269 +
270 + pll0 &= ~BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK;
271 + pll0 |= freq_tgt_target << BCMA_CC_PMU15_PLL_PC0_FREQTGT_SHIFT;
272 + bcma_chipco_pll_write(cc, BCMA_CC_PMU15_PLL_PLLCTL0, pll0);
273 +
274 + /* Flush */
275 + if (cc->pmu.rev >= 2)
276 + bcma_cc_set32(cc, BCMA_CC_PMU_CTL, BCMA_CC_PMU_CTL_PLL_UPD);
277 +
278 + /* TODO: Do we need to update OTP? */
279 +}
280 +
281 +static void bcma_pmu_pll_init(struct bcma_drv_cc *cc)
282 +{
283 + struct bcma_bus *bus = cc->core->bus;
284 + u32 xtalfreq = bcma_pmu_xtalfreq(cc);
285 +
286 + switch (bus->chipinfo.id) {
287 + case BCMA_CHIP_ID_BCM43142:
288 + if (xtalfreq == 0)
289 + xtalfreq = 20000;
290 + bcma_pmu2_pll_init0(cc, xtalfreq);
291 + break;
292 + }
293 +}
294 +
295 static void bcma_pmu_resources_init(struct bcma_drv_cc *cc)
296 {
297 struct bcma_bus *bus = cc->core->bus;
298 @@ -66,6 +169,25 @@ static void bcma_pmu_resources_init(stru
299 min_msk = 0x200D;
300 max_msk = 0xFFFF;
301 break;
302 + case BCMA_CHIP_ID_BCM43142:
303 + min_msk = BCMA_RES_4314_LPLDO_PU |
304 + BCMA_RES_4314_PMU_SLEEP_DIS |
305 + BCMA_RES_4314_PMU_BG_PU |
306 + BCMA_RES_4314_CBUCK_LPOM_PU |
307 + BCMA_RES_4314_CBUCK_PFM_PU |
308 + BCMA_RES_4314_CLDO_PU |
309 + BCMA_RES_4314_LPLDO2_LVM |
310 + BCMA_RES_4314_WL_PMU_PU |
311 + BCMA_RES_4314_LDO3P3_PU |
312 + BCMA_RES_4314_OTP_PU |
313 + BCMA_RES_4314_WL_PWRSW_PU |
314 + BCMA_RES_4314_LQ_AVAIL |
315 + BCMA_RES_4314_LOGIC_RET |
316 + BCMA_RES_4314_MEM_SLEEP |
317 + BCMA_RES_4314_MACPHY_RET |
318 + BCMA_RES_4314_WL_CORE_READY;
319 + max_msk = 0x3FFFFFFF;
320 + break;
321 default:
322 bcma_debug(bus, "PMU resource config unknown or not needed for device 0x%04X\n",
323 bus->chipinfo.id);
324 @@ -165,6 +287,7 @@ void bcma_pmu_init(struct bcma_drv_cc *c
325 bcma_cc_set32(cc, BCMA_CC_PMU_CTL,
326 BCMA_CC_PMU_CTL_NOILPONW);
327
328 + bcma_pmu_pll_init(cc);
329 bcma_pmu_resources_init(cc);
330 bcma_pmu_workarounds(cc);
331 }
332 @@ -480,6 +603,8 @@ void bcma_pmu_spuravoid_pllupdate(struct
333 tmp = BCMA_CC_PMU_CTL_PLL_UPD | BCMA_CC_PMU_CTL_NOILPONW;
334 break;
335
336 + case BCMA_CHIP_ID_BCM43131:
337 + case BCMA_CHIP_ID_BCM43217:
338 case BCMA_CHIP_ID_BCM43227:
339 case BCMA_CHIP_ID_BCM43228:
340 case BCMA_CHIP_ID_BCM43428:
341 --- a/drivers/bcma/driver_chipcommon_sflash.c
342 +++ b/drivers/bcma/driver_chipcommon_sflash.c
343 @@ -30,7 +30,7 @@ struct bcma_sflash_tbl_e {
344 u16 numblocks;
345 };
346
347 -static struct bcma_sflash_tbl_e bcma_sflash_st_tbl[] = {
348 +static const struct bcma_sflash_tbl_e bcma_sflash_st_tbl[] = {
349 { "M25P20", 0x11, 0x10000, 4, },
350 { "M25P40", 0x12, 0x10000, 8, },
351
352 @@ -38,10 +38,10 @@ static struct bcma_sflash_tbl_e bcma_sfl
353 { "M25P32", 0x15, 0x10000, 64, },
354 { "M25P64", 0x16, 0x10000, 128, },
355 { "M25FL128", 0x17, 0x10000, 256, },
356 - { 0 },
357 + { NULL },
358 };
359
360 -static struct bcma_sflash_tbl_e bcma_sflash_sst_tbl[] = {
361 +static const struct bcma_sflash_tbl_e bcma_sflash_sst_tbl[] = {
362 { "SST25WF512", 1, 0x1000, 16, },
363 { "SST25VF512", 0x48, 0x1000, 16, },
364 { "SST25WF010", 2, 0x1000, 32, },
365 @@ -56,10 +56,10 @@ static struct bcma_sflash_tbl_e bcma_sfl
366 { "SST25VF016", 0x41, 0x1000, 512, },
367 { "SST25VF032", 0x4a, 0x1000, 1024, },
368 { "SST25VF064", 0x4b, 0x1000, 2048, },
369 - { 0 },
370 + { NULL },
371 };
372
373 -static struct bcma_sflash_tbl_e bcma_sflash_at_tbl[] = {
374 +static const struct bcma_sflash_tbl_e bcma_sflash_at_tbl[] = {
375 { "AT45DB011", 0xc, 256, 512, },
376 { "AT45DB021", 0x14, 256, 1024, },
377 { "AT45DB041", 0x1c, 256, 2048, },
378 @@ -67,7 +67,7 @@ static struct bcma_sflash_tbl_e bcma_sfl
379 { "AT45DB161", 0x2c, 512, 4096, },
380 { "AT45DB321", 0x34, 512, 8192, },
381 { "AT45DB642", 0x3c, 1024, 8192, },
382 - { 0 },
383 + { NULL },
384 };
385
386 static void bcma_sflash_cmd(struct bcma_drv_cc *cc, u32 opcode)
387 @@ -89,7 +89,7 @@ int bcma_sflash_init(struct bcma_drv_cc
388 {
389 struct bcma_bus *bus = cc->core->bus;
390 struct bcma_sflash *sflash = &cc->sflash;
391 - struct bcma_sflash_tbl_e *e;
392 + const struct bcma_sflash_tbl_e *e;
393 u32 id, id2;
394
395 switch (cc->capabilities & BCMA_CC_CAP_FLASHT) {
396 --- a/drivers/bcma/driver_gpio.c
397 +++ b/drivers/bcma/driver_gpio.c
398 @@ -9,6 +9,9 @@
399 */
400
401 #include <linux/gpio.h>
402 +#include <linux/irq.h>
403 +#include <linux/interrupt.h>
404 +#include <linux/irqdomain.h>
405 #include <linux/export.h>
406 #include <linux/bcma/bcma.h>
407
408 @@ -73,19 +76,136 @@ static void bcma_gpio_free(struct gpio_c
409 bcma_chipco_gpio_pullup(cc, 1 << gpio, 0);
410 }
411
412 +#if IS_BUILTIN(CONFIG_BCM47XX)
413 static int bcma_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
414 {
415 struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
416
417 if (cc->core->bus->hosttype == BCMA_HOSTTYPE_SOC)
418 - return bcma_core_irq(cc->core);
419 + return irq_find_mapping(cc->irq_domain, gpio);
420 else
421 return -EINVAL;
422 }
423
424 +static void bcma_gpio_irq_unmask(struct irq_data *d)
425 +{
426 + struct bcma_drv_cc *cc = irq_data_get_irq_chip_data(d);
427 + int gpio = irqd_to_hwirq(d);
428 + u32 val = bcma_chipco_gpio_in(cc, BIT(gpio));
429 +
430 + bcma_chipco_gpio_polarity(cc, BIT(gpio), val);
431 + bcma_chipco_gpio_intmask(cc, BIT(gpio), BIT(gpio));
432 +}
433 +
434 +static void bcma_gpio_irq_mask(struct irq_data *d)
435 +{
436 + struct bcma_drv_cc *cc = irq_data_get_irq_chip_data(d);
437 + int gpio = irqd_to_hwirq(d);
438 +
439 + bcma_chipco_gpio_intmask(cc, BIT(gpio), 0);
440 +}
441 +
442 +static struct irq_chip bcma_gpio_irq_chip = {
443 + .name = "BCMA-GPIO",
444 + .irq_mask = bcma_gpio_irq_mask,
445 + .irq_unmask = bcma_gpio_irq_unmask,
446 +};
447 +
448 +static irqreturn_t bcma_gpio_irq_handler(int irq, void *dev_id)
449 +{
450 + struct bcma_drv_cc *cc = dev_id;
451 + u32 val = bcma_cc_read32(cc, BCMA_CC_GPIOIN);
452 + u32 mask = bcma_cc_read32(cc, BCMA_CC_GPIOIRQ);
453 + u32 pol = bcma_cc_read32(cc, BCMA_CC_GPIOPOL);
454 + unsigned long irqs = (val ^ pol) & mask;
455 + int gpio;
456 +
457 + if (!irqs)
458 + return IRQ_NONE;
459 +
460 + for_each_set_bit(gpio, &irqs, cc->gpio.ngpio)
461 + generic_handle_irq(bcma_gpio_to_irq(&cc->gpio, gpio));
462 + bcma_chipco_gpio_polarity(cc, irqs, val & irqs);
463 +
464 + return IRQ_HANDLED;
465 +}
466 +
467 +static int bcma_gpio_irq_domain_init(struct bcma_drv_cc *cc)
468 +{
469 + struct gpio_chip *chip = &cc->gpio;
470 + int gpio, hwirq, err;
471 +
472 + if (cc->core->bus->hosttype != BCMA_HOSTTYPE_SOC)
473 + return 0;
474 +
475 + cc->irq_domain = irq_domain_add_linear(NULL, chip->ngpio,
476 + &irq_domain_simple_ops, cc);
477 + if (!cc->irq_domain) {
478 + err = -ENODEV;
479 + goto err_irq_domain;
480 + }
481 + for (gpio = 0; gpio < chip->ngpio; gpio++) {
482 + int irq = irq_create_mapping(cc->irq_domain, gpio);
483 +
484 + irq_set_chip_data(irq, cc);
485 + irq_set_chip_and_handler(irq, &bcma_gpio_irq_chip,
486 + handle_simple_irq);
487 + }
488 +
489 + hwirq = bcma_core_irq(cc->core, 0);
490 + err = request_irq(hwirq, bcma_gpio_irq_handler, IRQF_SHARED, "gpio",
491 + cc);
492 + if (err)
493 + goto err_req_irq;
494 +
495 + bcma_chipco_gpio_intmask(cc, ~0, 0);
496 + bcma_cc_set32(cc, BCMA_CC_IRQMASK, BCMA_CC_IRQ_GPIO);
497 +
498 + return 0;
499 +
500 +err_req_irq:
501 + for (gpio = 0; gpio < chip->ngpio; gpio++) {
502 + int irq = irq_find_mapping(cc->irq_domain, gpio);
503 +
504 + irq_dispose_mapping(irq);
505 + }
506 + irq_domain_remove(cc->irq_domain);
507 +err_irq_domain:
508 + return err;
509 +}
510 +
511 +static void bcma_gpio_irq_domain_exit(struct bcma_drv_cc *cc)
512 +{
513 + struct gpio_chip *chip = &cc->gpio;
514 + int gpio;
515 +
516 + if (cc->core->bus->hosttype != BCMA_HOSTTYPE_SOC)
517 + return;
518 +
519 + bcma_cc_mask32(cc, BCMA_CC_IRQMASK, ~BCMA_CC_IRQ_GPIO);
520 + free_irq(bcma_core_irq(cc->core, 0), cc);
521 + for (gpio = 0; gpio < chip->ngpio; gpio++) {
522 + int irq = irq_find_mapping(cc->irq_domain, gpio);
523 +
524 + irq_dispose_mapping(irq);
525 + }
526 + irq_domain_remove(cc->irq_domain);
527 +}
528 +#else
529 +static int bcma_gpio_irq_domain_init(struct bcma_drv_cc *cc)
530 +{
531 + return 0;
532 +}
533 +
534 +static void bcma_gpio_irq_domain_exit(struct bcma_drv_cc *cc)
535 +{
536 +}
537 +#endif
538 +
539 int bcma_gpio_init(struct bcma_drv_cc *cc)
540 {
541 struct gpio_chip *chip = &cc->gpio;
542 + int err;
543
544 chip->label = "bcma_gpio";
545 chip->owner = THIS_MODULE;
546 @@ -95,8 +215,22 @@ int bcma_gpio_init(struct bcma_drv_cc *c
547 chip->set = bcma_gpio_set_value;
548 chip->direction_input = bcma_gpio_direction_input;
549 chip->direction_output = bcma_gpio_direction_output;
550 +#if IS_BUILTIN(CONFIG_BCM47XX)
551 chip->to_irq = bcma_gpio_to_irq;
552 - chip->ngpio = 16;
553 +#endif
554 +#if IS_BUILTIN(CONFIG_OF)
555 + if (cc->core->bus->hosttype == BCMA_HOSTTYPE_SOC)
556 + chip->of_node = cc->core->dev.of_node;
557 +#endif
558 + switch (cc->core->bus->chipinfo.id) {
559 + case BCMA_CHIP_ID_BCM5357:
560 + case BCMA_CHIP_ID_BCM53572:
561 + chip->ngpio = 32;
562 + break;
563 + default:
564 + chip->ngpio = 16;
565 + }
566 +
567 /* There is just one SoC in one device and its GPIO addresses should be
568 * deterministic to address them more easily. The other buses could get
569 * a random base number. */
570 @@ -105,10 +239,22 @@ int bcma_gpio_init(struct bcma_drv_cc *c
571 else
572 chip->base = -1;
573
574 - return gpiochip_add(chip);
575 + err = bcma_gpio_irq_domain_init(cc);
576 + if (err)
577 + return err;
578 +
579 + err = gpiochip_add(chip);
580 + if (err) {
581 + bcma_gpio_irq_domain_exit(cc);
582 + return err;
583 + }
584 +
585 + return 0;
586 }
587
588 int bcma_gpio_unregister(struct bcma_drv_cc *cc)
589 {
590 - return gpiochip_remove(&cc->gpio);
591 + bcma_gpio_irq_domain_exit(cc);
592 + gpiochip_remove(&cc->gpio);
593 + return 0;
594 }
595 --- a/drivers/bcma/driver_pci.c
596 +++ b/drivers/bcma/driver_pci.c
597 @@ -31,7 +31,7 @@ static void bcma_pcie_write(struct bcma_
598 pcicore_write32(pc, BCMA_CORE_PCI_PCIEIND_DATA, data);
599 }
600
601 -static void bcma_pcie_mdio_set_phy(struct bcma_drv_pci *pc, u8 phy)
602 +static void bcma_pcie_mdio_set_phy(struct bcma_drv_pci *pc, u16 phy)
603 {
604 u32 v;
605 int i;
606 @@ -55,7 +55,7 @@ static void bcma_pcie_mdio_set_phy(struc
607 }
608 }
609
610 -static u16 bcma_pcie_mdio_read(struct bcma_drv_pci *pc, u8 device, u8 address)
611 +static u16 bcma_pcie_mdio_read(struct bcma_drv_pci *pc, u16 device, u8 address)
612 {
613 int max_retries = 10;
614 u16 ret = 0;
615 @@ -98,7 +98,7 @@ static u16 bcma_pcie_mdio_read(struct bc
616 return ret;
617 }
618
619 -static void bcma_pcie_mdio_write(struct bcma_drv_pci *pc, u8 device,
620 +static void bcma_pcie_mdio_write(struct bcma_drv_pci *pc, u16 device,
621 u8 address, u16 data)
622 {
623 int max_retries = 10;
624 @@ -137,6 +137,13 @@ static void bcma_pcie_mdio_write(struct
625 pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, 0);
626 }
627
628 +static u16 bcma_pcie_mdio_writeread(struct bcma_drv_pci *pc, u16 device,
629 + u8 address, u16 data)
630 +{
631 + bcma_pcie_mdio_write(pc, device, address, data);
632 + return bcma_pcie_mdio_read(pc, device, address);
633 +}
634 +
635 /**************************************************
636 * Workarounds.
637 **************************************************/
638 @@ -229,6 +236,32 @@ void bcma_core_pci_init(struct bcma_drv_
639 bcma_core_pci_clientmode_init(pc);
640 }
641
642 +void bcma_core_pci_power_save(struct bcma_bus *bus, bool up)
643 +{
644 + struct bcma_drv_pci *pc;
645 + u16 data;
646 +
647 + if (bus->hosttype != BCMA_HOSTTYPE_PCI)
648 + return;
649 +
650 + pc = &bus->drv_pci[0];
651 +
652 + if (pc->core->id.rev >= 15 && pc->core->id.rev <= 20) {
653 + data = up ? 0x74 : 0x7C;
654 + bcma_pcie_mdio_writeread(pc, BCMA_CORE_PCI_MDIO_BLK1,
655 + BCMA_CORE_PCI_MDIO_BLK1_MGMT1, 0x7F64);
656 + bcma_pcie_mdio_writeread(pc, BCMA_CORE_PCI_MDIO_BLK1,
657 + BCMA_CORE_PCI_MDIO_BLK1_MGMT3, data);
658 + } else if (pc->core->id.rev >= 21 && pc->core->id.rev <= 22) {
659 + data = up ? 0x75 : 0x7D;
660 + bcma_pcie_mdio_writeread(pc, BCMA_CORE_PCI_MDIO_BLK1,
661 + BCMA_CORE_PCI_MDIO_BLK1_MGMT1, 0x7E65);
662 + bcma_pcie_mdio_writeread(pc, BCMA_CORE_PCI_MDIO_BLK1,
663 + BCMA_CORE_PCI_MDIO_BLK1_MGMT3, data);
664 + }
665 +}
666 +EXPORT_SYMBOL_GPL(bcma_core_pci_power_save);
667 +
668 int bcma_core_pci_irq_ctl(struct bcma_drv_pci *pc, struct bcma_device *core,
669 bool enable)
670 {
671 @@ -262,7 +295,7 @@ out:
672 }
673 EXPORT_SYMBOL_GPL(bcma_core_pci_irq_ctl);
674
675 -void bcma_core_pci_extend_L1timer(struct bcma_drv_pci *pc, bool extend)
676 +static void bcma_core_pci_extend_L1timer(struct bcma_drv_pci *pc, bool extend)
677 {
678 u32 w;
679
680 @@ -274,4 +307,29 @@ void bcma_core_pci_extend_L1timer(struct
681 bcma_pcie_write(pc, BCMA_CORE_PCI_DLLP_PMTHRESHREG, w);
682 bcma_pcie_read(pc, BCMA_CORE_PCI_DLLP_PMTHRESHREG);
683 }
684 -EXPORT_SYMBOL_GPL(bcma_core_pci_extend_L1timer);
685 +
686 +void bcma_core_pci_up(struct bcma_bus *bus)
687 +{
688 + struct bcma_drv_pci *pc;
689 +
690 + if (bus->hosttype != BCMA_HOSTTYPE_PCI)
691 + return;
692 +
693 + pc = &bus->drv_pci[0];
694 +
695 + bcma_core_pci_extend_L1timer(pc, true);
696 +}
697 +EXPORT_SYMBOL_GPL(bcma_core_pci_up);
698 +
699 +void bcma_core_pci_down(struct bcma_bus *bus)
700 +{
701 + struct bcma_drv_pci *pc;
702 +
703 + if (bus->hosttype != BCMA_HOSTTYPE_PCI)
704 + return;
705 +
706 + pc = &bus->drv_pci[0];
707 +
708 + bcma_core_pci_extend_L1timer(pc, false);
709 +}
710 +EXPORT_SYMBOL_GPL(bcma_core_pci_down);
711 --- a/drivers/bcma/driver_pci_host.c
712 +++ b/drivers/bcma/driver_pci_host.c
713 @@ -581,6 +581,7 @@ DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI
714 int bcma_core_pci_plat_dev_init(struct pci_dev *dev)
715 {
716 struct bcma_drv_pci_host *pc_host;
717 + int readrq;
718
719 if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) {
720 /* This is not a device on the PCI-core bridge. */
721 @@ -592,9 +593,14 @@ int bcma_core_pci_plat_dev_init(struct p
722 pr_info("PCI: Fixing up device %s\n", pci_name(dev));
723
724 /* Fix up interrupt lines */
725 - dev->irq = bcma_core_irq(pc_host->pdev->core);
726 + dev->irq = bcma_core_irq(pc_host->pdev->core, 0);
727 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
728
729 + readrq = pcie_get_readrq(dev);
730 + if (readrq > 128) {
731 + pr_info("change PCIe max read request size from %i to 128\n", readrq);
732 + pcie_set_readrq(dev, 128);
733 + }
734 return 0;
735 }
736 EXPORT_SYMBOL(bcma_core_pci_plat_dev_init);
737 @@ -611,6 +617,6 @@ int bcma_core_pci_pcibios_map_irq(const
738
739 pc_host = container_of(dev->bus->ops, struct bcma_drv_pci_host,
740 pci_ops);
741 - return bcma_core_irq(pc_host->pdev->core);
742 + return bcma_core_irq(pc_host->pdev->core, 0);
743 }
744 EXPORT_SYMBOL(bcma_core_pci_pcibios_map_irq);
745 --- /dev/null
746 +++ b/drivers/bcma/driver_pcie2.c
747 @@ -0,0 +1,175 @@
748 +/*
749 + * Broadcom specific AMBA
750 + * PCIe Gen 2 Core
751 + *
752 + * Copyright 2014, Broadcom Corporation
753 + * Copyright 2014, Rafał Miłecki <zajec5@gmail.com>
754 + *
755 + * Licensed under the GNU/GPL. See COPYING for details.
756 + */
757 +
758 +#include "bcma_private.h"
759 +#include <linux/bcma/bcma.h>
760 +
761 +/**************************************************
762 + * R/W ops.
763 + **************************************************/
764 +
765 +#if 0
766 +static u32 bcma_core_pcie2_cfg_read(struct bcma_drv_pcie2 *pcie2, u32 addr)
767 +{
768 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, addr);
769 + pcie2_read32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR);
770 + return pcie2_read32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA);
771 +}
772 +#endif
773 +
774 +static void bcma_core_pcie2_cfg_write(struct bcma_drv_pcie2 *pcie2, u32 addr,
775 + u32 val)
776 +{
777 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, addr);
778 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, val);
779 +}
780 +
781 +/**************************************************
782 + * Init.
783 + **************************************************/
784 +
785 +static u32 bcma_core_pcie2_war_delay_perst_enab(struct bcma_drv_pcie2 *pcie2,
786 + bool enable)
787 +{
788 + u32 val;
789 +
790 + /* restore back to default */
791 + val = pcie2_read32(pcie2, BCMA_CORE_PCIE2_CLK_CONTROL);
792 + val |= PCIE2_CLKC_DLYPERST;
793 + val &= ~PCIE2_CLKC_DISSPROMLD;
794 + if (enable) {
795 + val &= ~PCIE2_CLKC_DLYPERST;
796 + val |= PCIE2_CLKC_DISSPROMLD;
797 + }
798 + pcie2_write32(pcie2, (BCMA_CORE_PCIE2_CLK_CONTROL), val);
799 + /* flush */
800 + return pcie2_read32(pcie2, BCMA_CORE_PCIE2_CLK_CONTROL);
801 +}
802 +
803 +static void bcma_core_pcie2_set_ltr_vals(struct bcma_drv_pcie2 *pcie2)
804 +{
805 + /* LTR0 */
806 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, 0x844);
807 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x883c883c);
808 + /* LTR1 */
809 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, 0x848);
810 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x88648864);
811 + /* LTR2 */
812 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, 0x84C);
813 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x90039003);
814 +}
815 +
816 +static void bcma_core_pcie2_hw_ltr_war(struct bcma_drv_pcie2 *pcie2)
817 +{
818 + u8 core_rev = pcie2->core->id.rev;
819 + u32 devstsctr2;
820 +
821 + if (core_rev < 2 || core_rev == 10 || core_rev > 13)
822 + return;
823 +
824 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR,
825 + PCIE2_CAP_DEVSTSCTRL2_OFFSET);
826 + devstsctr2 = pcie2_read32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA);
827 + if (devstsctr2 & PCIE2_CAP_DEVSTSCTRL2_LTRENAB) {
828 + /* force the right LTR values */
829 + bcma_core_pcie2_set_ltr_vals(pcie2);
830 +
831 + /* TODO:
832 + si_core_wrapperreg(pcie2, 3, 0x60, 0x8080, 0); */
833 +
834 + /* enable the LTR */
835 + devstsctr2 |= PCIE2_CAP_DEVSTSCTRL2_LTRENAB;
836 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR,
837 + PCIE2_CAP_DEVSTSCTRL2_OFFSET);
838 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, devstsctr2);
839 +
840 + /* set the LTR state to be active */
841 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_LTR_STATE,
842 + PCIE2_LTR_ACTIVE);
843 + usleep_range(1000, 2000);
844 +
845 + /* set the LTR state to be sleep */
846 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_LTR_STATE,
847 + PCIE2_LTR_SLEEP);
848 + usleep_range(1000, 2000);
849 + }
850 +}
851 +
852 +static void pciedev_crwlpciegen2(struct bcma_drv_pcie2 *pcie2)
853 +{
854 + u8 core_rev = pcie2->core->id.rev;
855 + bool pciewar160, pciewar162;
856 +
857 + pciewar160 = core_rev == 7 || core_rev == 9 || core_rev == 11;
858 + pciewar162 = core_rev == 5 || core_rev == 7 || core_rev == 8 ||
859 + core_rev == 9 || core_rev == 11;
860 +
861 + if (!pciewar160 && !pciewar162)
862 + return;
863 +
864 +/* TODO */
865 +#if 0
866 + pcie2_set32(pcie2, BCMA_CORE_PCIE2_CLK_CONTROL,
867 + PCIE_DISABLE_L1CLK_GATING);
868 +#if 0
869 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR,
870 + PCIEGEN2_COE_PVT_TL_CTRL_0);
871 + pcie2_mask32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA,
872 + ~(1 << COE_PVT_TL_CTRL_0_PM_DIS_L1_REENTRY_BIT));
873 +#endif
874 +#endif
875 +}
876 +
877 +static void pciedev_crwlpciegen2_180(struct bcma_drv_pcie2 *pcie2)
878 +{
879 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, PCIE2_PMCR_REFUP);
880 + pcie2_set32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x1f);
881 +}
882 +
883 +static void pciedev_crwlpciegen2_182(struct bcma_drv_pcie2 *pcie2)
884 +{
885 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, PCIE2_SBMBX);
886 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 1 << 0);
887 +}
888 +
889 +static void pciedev_reg_pm_clk_period(struct bcma_drv_pcie2 *pcie2)
890 +{
891 + struct bcma_drv_cc *drv_cc = &pcie2->core->bus->drv_cc;
892 + u8 core_rev = pcie2->core->id.rev;
893 + u32 alp_khz, pm_value;
894 +
895 + if (core_rev <= 13) {
896 + alp_khz = bcma_pmu_get_alp_clock(drv_cc) / 1000;
897 + pm_value = (1000000 * 2) / alp_khz;
898 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR,
899 + PCIE2_PVT_REG_PM_CLK_PERIOD);
900 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, pm_value);
901 + }
902 +}
903 +
904 +void bcma_core_pcie2_init(struct bcma_drv_pcie2 *pcie2)
905 +{
906 + struct bcma_chipinfo *ci = &pcie2->core->bus->chipinfo;
907 + u32 tmp;
908 +
909 + tmp = pcie2_read32(pcie2, BCMA_CORE_PCIE2_SPROM(54));
910 + if ((tmp & 0xe) >> 1 == 2)
911 + bcma_core_pcie2_cfg_write(pcie2, 0x4e0, 0x17);
912 +
913 + /* TODO: Do we need pcie_reqsize? */
914 +
915 + if (ci->id == BCMA_CHIP_ID_BCM4360 && ci->rev > 3)
916 + bcma_core_pcie2_war_delay_perst_enab(pcie2, true);
917 + bcma_core_pcie2_hw_ltr_war(pcie2);
918 + pciedev_crwlpciegen2(pcie2);
919 + pciedev_reg_pm_clk_period(pcie2);
920 + pciedev_crwlpciegen2_180(pcie2);
921 + pciedev_crwlpciegen2_182(pcie2);
922 +}
923 --- a/drivers/bcma/host_pci.c
924 +++ b/drivers/bcma/host_pci.c
925 @@ -188,8 +188,11 @@ static int bcma_host_pci_probe(struct pc
926 pci_write_config_dword(dev, 0x40, val & 0xffff00ff);
927
928 /* SSB needed additional powering up, do we have any AMBA PCI cards? */
929 - if (!pci_is_pcie(dev))
930 - bcma_err(bus, "PCI card detected, report problems.\n");
931 + if (!pci_is_pcie(dev)) {
932 + bcma_err(bus, "PCI card detected, they are not supported.\n");
933 + err = -ENXIO;
934 + goto err_pci_release_regions;
935 + }
936
937 /* Map MMIO */
938 err = -ENOMEM;
939 @@ -205,6 +208,9 @@ static int bcma_host_pci_probe(struct pc
940 bus->boardinfo.vendor = bus->host_pci->subsystem_vendor;
941 bus->boardinfo.type = bus->host_pci->subsystem_device;
942
943 + /* Initialize struct, detect chip */
944 + bcma_init_bus(bus);
945 +
946 /* Register */
947 err = bcma_bus_register(bus);
948 if (err)
949 @@ -235,7 +241,6 @@ static void bcma_host_pci_remove(struct
950 pci_release_regions(dev);
951 pci_disable_device(dev);
952 kfree(bus);
953 - pci_set_drvdata(dev, NULL);
954 }
955
956 #ifdef CONFIG_PM_SLEEP
957 @@ -267,15 +272,21 @@ static SIMPLE_DEV_PM_OPS(bcma_pm_ops, bc
958
959 #endif /* CONFIG_PM_SLEEP */
960
961 -static DEFINE_PCI_DEVICE_TABLE(bcma_pci_bridge_tbl) = {
962 +static const struct pci_device_id bcma_pci_bridge_tbl[] = {
963 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x0576) },
964 - { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 43224) },
965 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4313) },
966 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 43224) }, /* 0xa8d8 */
967 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4331) },
968 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4353) },
969 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4357) },
970 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4358) },
971 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4359) },
972 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4365) },
973 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x43a9) },
974 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x43aa) },
975 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4727) },
976 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 43227) }, /* 0xa8db, BCM43217 (sic!) */
977 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 43228) }, /* 0xa8dc */
978 { 0, },
979 };
980 MODULE_DEVICE_TABLE(pci, bcma_pci_bridge_tbl);
981 --- a/drivers/bcma/main.c
982 +++ b/drivers/bcma/main.c
983 @@ -10,6 +10,8 @@
984 #include <linux/platform_device.h>
985 #include <linux/bcma/bcma.h>
986 #include <linux/slab.h>
987 +#include <linux/of_address.h>
988 +#include <linux/of_irq.h>
989
990 MODULE_DESCRIPTION("Broadcom's specific AMBA driver");
991 MODULE_LICENSE("GPL");
992 @@ -69,28 +71,36 @@ static u16 bcma_cc_core_id(struct bcma_b
993 return BCMA_CORE_CHIPCOMMON;
994 }
995
996 -struct bcma_device *bcma_find_core(struct bcma_bus *bus, u16 coreid)
997 +struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
998 + u8 unit)
999 {
1000 struct bcma_device *core;
1001
1002 list_for_each_entry(core, &bus->cores, list) {
1003 - if (core->id.id == coreid)
1004 + if (core->id.id == coreid && core->core_unit == unit)
1005 return core;
1006 }
1007 return NULL;
1008 }
1009 -EXPORT_SYMBOL_GPL(bcma_find_core);
1010 +EXPORT_SYMBOL_GPL(bcma_find_core_unit);
1011
1012 -struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
1013 - u8 unit)
1014 +bool bcma_wait_value(struct bcma_device *core, u16 reg, u32 mask, u32 value,
1015 + int timeout)
1016 {
1017 - struct bcma_device *core;
1018 + unsigned long deadline = jiffies + timeout;
1019 + u32 val;
1020
1021 - list_for_each_entry(core, &bus->cores, list) {
1022 - if (core->id.id == coreid && core->core_unit == unit)
1023 - return core;
1024 - }
1025 - return NULL;
1026 + do {
1027 + val = bcma_read32(core, reg);
1028 + if ((val & mask) == value)
1029 + return true;
1030 + cpu_relax();
1031 + udelay(10);
1032 + } while (!time_after_eq(jiffies, deadline));
1033 +
1034 + bcma_warn(core->bus, "Timeout waiting for register 0x%04X!\n", reg);
1035 +
1036 + return false;
1037 }
1038
1039 static void bcma_release_core_dev(struct device *dev)
1040 @@ -103,55 +113,195 @@ static void bcma_release_core_dev(struct
1041 kfree(core);
1042 }
1043
1044 -static int bcma_register_cores(struct bcma_bus *bus)
1045 +static bool bcma_is_core_needed_early(u16 core_id)
1046 +{
1047 + switch (core_id) {
1048 + case BCMA_CORE_NS_NAND:
1049 + case BCMA_CORE_NS_QSPI:
1050 + return true;
1051 + }
1052 +
1053 + return false;
1054 +}
1055 +
1056 +#if defined(CONFIG_OF) && defined(CONFIG_OF_ADDRESS)
1057 +static struct device_node *bcma_of_find_child_device(struct platform_device *parent,
1058 + struct bcma_device *core)
1059 +{
1060 + struct device_node *node;
1061 + u64 size;
1062 + const __be32 *reg;
1063 +
1064 + if (!parent || !parent->dev.of_node)
1065 + return NULL;
1066 +
1067 + for_each_child_of_node(parent->dev.of_node, node) {
1068 + reg = of_get_address(node, 0, &size, NULL);
1069 + if (!reg)
1070 + continue;
1071 + if (of_translate_address(node, reg) == core->addr)
1072 + return node;
1073 + }
1074 + return NULL;
1075 +}
1076 +
1077 +static int bcma_of_irq_parse(struct platform_device *parent,
1078 + struct bcma_device *core,
1079 + struct of_phandle_args *out_irq, int num)
1080 +{
1081 + __be32 laddr[1];
1082 + int rc;
1083 +
1084 + if (core->dev.of_node) {
1085 + rc = of_irq_parse_one(core->dev.of_node, num, out_irq);
1086 + if (!rc)
1087 + return rc;
1088 + }
1089 +
1090 + out_irq->np = parent->dev.of_node;
1091 + out_irq->args_count = 1;
1092 + out_irq->args[0] = num;
1093 +
1094 + laddr[0] = cpu_to_be32(core->addr);
1095 + return of_irq_parse_raw(laddr, out_irq);
1096 +}
1097 +
1098 +static unsigned int bcma_of_get_irq(struct platform_device *parent,
1099 + struct bcma_device *core, int num)
1100 +{
1101 + struct of_phandle_args out_irq;
1102 + int ret;
1103 +
1104 + if (!parent || !parent->dev.of_node)
1105 + return 0;
1106 +
1107 + ret = bcma_of_irq_parse(parent, core, &out_irq, num);
1108 + if (ret) {
1109 + bcma_debug(core->bus, "bcma_of_get_irq() failed with rc=%d\n",
1110 + ret);
1111 + return 0;
1112 + }
1113 +
1114 + return irq_create_of_mapping(&out_irq);
1115 +}
1116 +
1117 +static void bcma_of_fill_device(struct platform_device *parent,
1118 + struct bcma_device *core)
1119 +{
1120 + struct device_node *node;
1121 +
1122 + node = bcma_of_find_child_device(parent, core);
1123 + if (node)
1124 + core->dev.of_node = node;
1125 +
1126 + core->irq = bcma_of_get_irq(parent, core, 0);
1127 +}
1128 +#else
1129 +static void bcma_of_fill_device(struct platform_device *parent,
1130 + struct bcma_device *core)
1131 +{
1132 +}
1133 +static inline unsigned int bcma_of_get_irq(struct platform_device *parent,
1134 + struct bcma_device *core, int num)
1135 +{
1136 + return 0;
1137 +}
1138 +#endif /* CONFIG_OF */
1139 +
1140 +unsigned int bcma_core_irq(struct bcma_device *core, int num)
1141 +{
1142 + struct bcma_bus *bus = core->bus;
1143 + unsigned int mips_irq;
1144 +
1145 + switch (bus->hosttype) {
1146 + case BCMA_HOSTTYPE_PCI:
1147 + return bus->host_pci->irq;
1148 + case BCMA_HOSTTYPE_SOC:
1149 + if (bus->drv_mips.core && num == 0) {
1150 + mips_irq = bcma_core_mips_irq(core);
1151 + return mips_irq <= 4 ? mips_irq + 2 : 0;
1152 + }
1153 + if (bus->host_pdev)
1154 + return bcma_of_get_irq(bus->host_pdev, core, num);
1155 + return 0;
1156 + case BCMA_HOSTTYPE_SDIO:
1157 + return 0;
1158 + }
1159 +
1160 + return 0;
1161 +}
1162 +EXPORT_SYMBOL(bcma_core_irq);
1163 +
1164 +void bcma_prepare_core(struct bcma_bus *bus, struct bcma_device *core)
1165 +{
1166 + core->dev.release = bcma_release_core_dev;
1167 + core->dev.bus = &bcma_bus_type;
1168 + dev_set_name(&core->dev, "bcma%d:%d", bus->num, core->core_index);
1169 +
1170 + switch (bus->hosttype) {
1171 + case BCMA_HOSTTYPE_PCI:
1172 + core->dev.parent = &bus->host_pci->dev;
1173 + core->dma_dev = &bus->host_pci->dev;
1174 + core->irq = bus->host_pci->irq;
1175 + break;
1176 + case BCMA_HOSTTYPE_SOC:
1177 + core->dev.dma_mask = &core->dev.coherent_dma_mask;
1178 + if (bus->host_pdev) {
1179 + core->dma_dev = &bus->host_pdev->dev;
1180 + core->dev.parent = &bus->host_pdev->dev;
1181 + bcma_of_fill_device(bus->host_pdev, core);
1182 + } else {
1183 + core->dma_dev = &core->dev;
1184 + }
1185 + break;
1186 + case BCMA_HOSTTYPE_SDIO:
1187 + break;
1188 + }
1189 +}
1190 +
1191 +static void bcma_register_core(struct bcma_bus *bus, struct bcma_device *core)
1192 +{
1193 + int err;
1194 +
1195 + err = device_register(&core->dev);
1196 + if (err) {
1197 + bcma_err(bus, "Could not register dev for core 0x%03X\n",
1198 + core->id.id);
1199 + put_device(&core->dev);
1200 + return;
1201 + }
1202 + core->dev_registered = true;
1203 +}
1204 +
1205 +static int bcma_register_devices(struct bcma_bus *bus)
1206 {
1207 struct bcma_device *core;
1208 - int err, dev_id = 0;
1209 + int err;
1210
1211 list_for_each_entry(core, &bus->cores, list) {
1212 /* We support that cores ourself */
1213 switch (core->id.id) {
1214 case BCMA_CORE_4706_CHIPCOMMON:
1215 case BCMA_CORE_CHIPCOMMON:
1216 + case BCMA_CORE_NS_CHIPCOMMON_B:
1217 case BCMA_CORE_PCI:
1218 case BCMA_CORE_PCIE:
1219 + case BCMA_CORE_PCIE2:
1220 case BCMA_CORE_MIPS_74K:
1221 case BCMA_CORE_4706_MAC_GBIT_COMMON:
1222 continue;
1223 }
1224
1225 + /* Early cores were already registered */
1226 + if (bcma_is_core_needed_early(core->id.id))
1227 + continue;
1228 +
1229 /* Only first GMAC core on BCM4706 is connected and working */
1230 if (core->id.id == BCMA_CORE_4706_MAC_GBIT &&
1231 core->core_unit > 0)
1232 continue;
1233
1234 - core->dev.release = bcma_release_core_dev;
1235 - core->dev.bus = &bcma_bus_type;
1236 - dev_set_name(&core->dev, "bcma%d:%d", bus->num, dev_id);
1237 -
1238 - switch (bus->hosttype) {
1239 - case BCMA_HOSTTYPE_PCI:
1240 - core->dev.parent = &bus->host_pci->dev;
1241 - core->dma_dev = &bus->host_pci->dev;
1242 - core->irq = bus->host_pci->irq;
1243 - break;
1244 - case BCMA_HOSTTYPE_SOC:
1245 - core->dev.dma_mask = &core->dev.coherent_dma_mask;
1246 - core->dma_dev = &core->dev;
1247 - break;
1248 - case BCMA_HOSTTYPE_SDIO:
1249 - break;
1250 - }
1251 -
1252 - err = device_register(&core->dev);
1253 - if (err) {
1254 - bcma_err(bus,
1255 - "Could not register dev for core 0x%03X\n",
1256 - core->id.id);
1257 - continue;
1258 - }
1259 - core->dev_registered = true;
1260 - dev_id++;
1261 + bcma_register_core(bus, core);
1262 }
1263
1264 #ifdef CONFIG_BCMA_DRIVER_MIPS
1265 @@ -218,7 +368,7 @@ int bcma_bus_register(struct bcma_bus *b
1266 err = bcma_bus_scan(bus);
1267 if (err) {
1268 bcma_err(bus, "Failed to scan: %d\n", err);
1269 - return -1;
1270 + return err;
1271 }
1272
1273 /* Early init CC core */
1274 @@ -228,6 +378,12 @@ int bcma_bus_register(struct bcma_bus *b
1275 bcma_core_chipcommon_early_init(&bus->drv_cc);
1276 }
1277
1278 + /* Cores providing flash access go before SPROM init */
1279 + list_for_each_entry(core, &bus->cores, list) {
1280 + if (bcma_is_core_needed_early(core->id.id))
1281 + bcma_register_core(bus, core);
1282 + }
1283 +
1284 /* Try to get SPROM */
1285 err = bcma_sprom_get(bus);
1286 if (err == -ENOENT) {
1287 @@ -242,6 +398,13 @@ int bcma_bus_register(struct bcma_bus *b
1288 bcma_core_chipcommon_init(&bus->drv_cc);
1289 }
1290
1291 + /* Init CC core */
1292 + core = bcma_find_core(bus, BCMA_CORE_NS_CHIPCOMMON_B);
1293 + if (core) {
1294 + bus->drv_cc_b.core = core;
1295 + bcma_core_chipcommon_b_init(&bus->drv_cc_b);
1296 + }
1297 +
1298 /* Init MIPS core */
1299 core = bcma_find_core(bus, BCMA_CORE_MIPS_74K);
1300 if (core) {
1301 @@ -263,6 +426,13 @@ int bcma_bus_register(struct bcma_bus *b
1302 bcma_core_pci_init(&bus->drv_pci[1]);
1303 }
1304
1305 + /* Init PCIe Gen 2 core */
1306 + core = bcma_find_core_unit(bus, BCMA_CORE_PCIE2, 0);
1307 + if (core) {
1308 + bus->drv_pcie2.core = core;
1309 + bcma_core_pcie2_init(&bus->drv_pcie2);
1310 + }
1311 +
1312 /* Init GBIT MAC COMMON core */
1313 core = bcma_find_core(bus, BCMA_CORE_4706_MAC_GBIT_COMMON);
1314 if (core) {
1315 @@ -271,7 +441,7 @@ int bcma_bus_register(struct bcma_bus *b
1316 }
1317
1318 /* Register found cores */
1319 - bcma_register_cores(bus);
1320 + bcma_register_devices(bus);
1321
1322 bcma_info(bus, "Bus registered\n");
1323
1324 @@ -289,6 +459,8 @@ void bcma_bus_unregister(struct bcma_bus
1325 else if (err)
1326 bcma_err(bus, "Can not unregister GPIO driver: %i\n", err);
1327
1328 + bcma_core_chipcommon_b_free(&bus->drv_cc_b);
1329 +
1330 cores[0] = bcma_find_core(bus, BCMA_CORE_MIPS_74K);
1331 cores[1] = bcma_find_core(bus, BCMA_CORE_PCIE);
1332 cores[2] = bcma_find_core(bus, BCMA_CORE_4706_MAC_GBIT_COMMON);
1333 @@ -308,8 +480,6 @@ int __init bcma_bus_early_register(struc
1334 struct bcma_device *core;
1335 struct bcma_device_id match;
1336
1337 - bcma_init_bus(bus);
1338 -
1339 match.manuf = BCMA_MANUF_BCM;
1340 match.id = bcma_cc_core_id(bus);
1341 match.class = BCMA_CL_SIM;
1342 @@ -468,6 +638,11 @@ static int __init bcma_modinit(void)
1343 if (err)
1344 return err;
1345
1346 + err = bcma_host_soc_register_driver();
1347 + if (err) {
1348 + pr_err("SoC host initialization failed\n");
1349 + err = 0;
1350 + }
1351 #ifdef CONFIG_BCMA_HOST_PCI
1352 err = bcma_host_pci_init();
1353 if (err) {
1354 @@ -485,6 +660,7 @@ static void __exit bcma_modexit(void)
1355 #ifdef CONFIG_BCMA_HOST_PCI
1356 bcma_host_pci_exit();
1357 #endif
1358 + bcma_host_soc_unregister_driver();
1359 bus_unregister(&bcma_bus_type);
1360 }
1361 module_exit(bcma_modexit)
1362 --- a/drivers/bcma/scan.c
1363 +++ b/drivers/bcma/scan.c
1364 @@ -32,6 +32,18 @@ static const struct bcma_device_id_name
1365 { BCMA_CORE_4706_CHIPCOMMON, "BCM4706 ChipCommon" },
1366 { BCMA_CORE_4706_SOC_RAM, "BCM4706 SOC RAM" },
1367 { BCMA_CORE_4706_MAC_GBIT, "BCM4706 GBit MAC" },
1368 + { BCMA_CORE_NS_PCIEG2, "PCIe Gen 2" },
1369 + { BCMA_CORE_NS_DMA, "DMA" },
1370 + { BCMA_CORE_NS_SDIO3, "SDIO3" },
1371 + { BCMA_CORE_NS_USB20, "USB 2.0" },
1372 + { BCMA_CORE_NS_USB30, "USB 3.0" },
1373 + { BCMA_CORE_NS_A9JTAG, "ARM Cortex A9 JTAG" },
1374 + { BCMA_CORE_NS_DDR23, "Denali DDR2/DDR3 memory controller" },
1375 + { BCMA_CORE_NS_ROM, "ROM" },
1376 + { BCMA_CORE_NS_NAND, "NAND flash controller" },
1377 + { BCMA_CORE_NS_QSPI, "SPI flash controller" },
1378 + { BCMA_CORE_NS_CHIPCOMMON_B, "Chipcommon B" },
1379 + { BCMA_CORE_ARMCA9, "ARM Cortex A9 core (ihost)" },
1380 { BCMA_CORE_AMEMC, "AMEMC (DDR)" },
1381 { BCMA_CORE_ALTA, "ALTA (I2S)" },
1382 { BCMA_CORE_INVALID, "Invalid" },
1383 @@ -201,7 +213,7 @@ static s32 bcma_erom_get_mst_port(struct
1384 return ent;
1385 }
1386
1387 -static s32 bcma_erom_get_addr_desc(struct bcma_bus *bus, u32 __iomem **eromptr,
1388 +static u32 bcma_erom_get_addr_desc(struct bcma_bus *bus, u32 __iomem **eromptr,
1389 u32 type, u8 port)
1390 {
1391 u32 addrl, addrh, sizel, sizeh = 0;
1392 @@ -213,7 +225,7 @@ static s32 bcma_erom_get_addr_desc(struc
1393 ((ent & SCAN_ADDR_TYPE) != type) ||
1394 (((ent & SCAN_ADDR_PORT) >> SCAN_ADDR_PORT_SHIFT) != port)) {
1395 bcma_erom_push_ent(eromptr);
1396 - return -EINVAL;
1397 + return (u32)-EINVAL;
1398 }
1399
1400 addrl = ent & SCAN_ADDR_ADDR;
1401 @@ -257,12 +269,14 @@ static struct bcma_device *bcma_find_cor
1402 return NULL;
1403 }
1404
1405 +#define IS_ERR_VALUE_U32(x) ((x) >= (u32)-MAX_ERRNO)
1406 +
1407 static int bcma_get_next_core(struct bcma_bus *bus, u32 __iomem **eromptr,
1408 struct bcma_device_id *match, int core_num,
1409 struct bcma_device *core)
1410 {
1411 - s32 tmp;
1412 - u8 i, j;
1413 + u32 tmp;
1414 + u8 i, j, k;
1415 s32 cia, cib;
1416 u8 ports[2], wrappers[2];
1417
1418 @@ -300,6 +314,7 @@ static int bcma_get_next_core(struct bcm
1419 /* Some specific cores don't need wrappers */
1420 switch (core->id.id) {
1421 case BCMA_CORE_4706_MAC_GBIT_COMMON:
1422 + case BCMA_CORE_NS_CHIPCOMMON_B:
1423 /* Not used yet: case BCMA_CORE_OOB_ROUTER: */
1424 break;
1425 default:
1426 @@ -339,11 +354,11 @@ static int bcma_get_next_core(struct bcm
1427 * the main register space for the core
1428 */
1429 tmp = bcma_erom_get_addr_desc(bus, eromptr, SCAN_ADDR_TYPE_SLAVE, 0);
1430 - if (tmp <= 0) {
1431 + if (tmp == 0 || IS_ERR_VALUE_U32(tmp)) {
1432 /* Try again to see if it is a bridge */
1433 tmp = bcma_erom_get_addr_desc(bus, eromptr,
1434 SCAN_ADDR_TYPE_BRIDGE, 0);
1435 - if (tmp <= 0) {
1436 + if (tmp == 0 || IS_ERR_VALUE_U32(tmp)) {
1437 return -EILSEQ;
1438 } else {
1439 bcma_info(bus, "Bridge found\n");
1440 @@ -353,18 +368,19 @@ static int bcma_get_next_core(struct bcm
1441 core->addr = tmp;
1442
1443 /* get & parse slave ports */
1444 + k = 0;
1445 for (i = 0; i < ports[1]; i++) {
1446 for (j = 0; ; j++) {
1447 tmp = bcma_erom_get_addr_desc(bus, eromptr,
1448 SCAN_ADDR_TYPE_SLAVE, i);
1449 - if (tmp < 0) {
1450 + if (IS_ERR_VALUE_U32(tmp)) {
1451 /* no more entries for port _i_ */
1452 /* pr_debug("erom: slave port %d "
1453 * "has %d descriptors\n", i, j); */
1454 break;
1455 - } else {
1456 - if (i == 0 && j == 0)
1457 - core->addr1 = tmp;
1458 + } else if (k < ARRAY_SIZE(core->addr_s)) {
1459 + core->addr_s[k] = tmp;
1460 + k++;
1461 }
1462 }
1463 }
1464 @@ -374,7 +390,7 @@ static int bcma_get_next_core(struct bcm
1465 for (j = 0; ; j++) {
1466 tmp = bcma_erom_get_addr_desc(bus, eromptr,
1467 SCAN_ADDR_TYPE_MWRAP, i);
1468 - if (tmp < 0) {
1469 + if (IS_ERR_VALUE_U32(tmp)) {
1470 /* no more entries for port _i_ */
1471 /* pr_debug("erom: master wrapper %d "
1472 * "has %d descriptors\n", i, j); */
1473 @@ -392,7 +408,7 @@ static int bcma_get_next_core(struct bcm
1474 for (j = 0; ; j++) {
1475 tmp = bcma_erom_get_addr_desc(bus, eromptr,
1476 SCAN_ADDR_TYPE_SWRAP, i + hack);
1477 - if (tmp < 0) {
1478 + if (IS_ERR_VALUE_U32(tmp)) {
1479 /* no more entries for port _i_ */
1480 /* pr_debug("erom: master wrapper %d "
1481 * has %d descriptors\n", i, j); */
1482 @@ -407,10 +423,13 @@ static int bcma_get_next_core(struct bcm
1483 core->io_addr = ioremap_nocache(core->addr, BCMA_CORE_SIZE);
1484 if (!core->io_addr)
1485 return -ENOMEM;
1486 - core->io_wrap = ioremap_nocache(core->wrap, BCMA_CORE_SIZE);
1487 - if (!core->io_wrap) {
1488 - iounmap(core->io_addr);
1489 - return -ENOMEM;
1490 + if (core->wrap) {
1491 + core->io_wrap = ioremap_nocache(core->wrap,
1492 + BCMA_CORE_SIZE);
1493 + if (!core->io_wrap) {
1494 + iounmap(core->io_addr);
1495 + return -ENOMEM;
1496 + }
1497 }
1498 }
1499 return 0;
1500 @@ -420,9 +439,7 @@ void bcma_init_bus(struct bcma_bus *bus)
1501 {
1502 s32 tmp;
1503 struct bcma_chipinfo *chipinfo = &(bus->chipinfo);
1504 -
1505 - if (bus->init_done)
1506 - return;
1507 + char chip_id[8];
1508
1509 INIT_LIST_HEAD(&bus->cores);
1510 bus->nr_cores = 0;
1511 @@ -433,10 +450,11 @@ void bcma_init_bus(struct bcma_bus *bus)
1512 chipinfo->id = (tmp & BCMA_CC_ID_ID) >> BCMA_CC_ID_ID_SHIFT;
1513 chipinfo->rev = (tmp & BCMA_CC_ID_REV) >> BCMA_CC_ID_REV_SHIFT;
1514 chipinfo->pkg = (tmp & BCMA_CC_ID_PKG) >> BCMA_CC_ID_PKG_SHIFT;
1515 - bcma_info(bus, "Found chip with id 0x%04X, rev 0x%02X and package 0x%02X\n",
1516 - chipinfo->id, chipinfo->rev, chipinfo->pkg);
1517
1518 - bus->init_done = true;
1519 + snprintf(chip_id, ARRAY_SIZE(chip_id),
1520 + (chipinfo->id > 0x9999) ? "%d" : "0x%04X", chipinfo->id);
1521 + bcma_info(bus, "Found chip with id %s, rev 0x%02X and package 0x%02X\n",
1522 + chip_id, chipinfo->rev, chipinfo->pkg);
1523 }
1524
1525 int bcma_bus_scan(struct bcma_bus *bus)
1526 @@ -446,8 +464,6 @@ int bcma_bus_scan(struct bcma_bus *bus)
1527
1528 int err, core_num = 0;
1529
1530 - bcma_init_bus(bus);
1531 -
1532 erombase = bcma_scan_read32(bus, 0, BCMA_CC_EROM);
1533 if (bus->hosttype == BCMA_HOSTTYPE_SOC) {
1534 eromptr = ioremap_nocache(erombase, BCMA_CORE_SIZE);
1535 @@ -489,6 +505,7 @@ int bcma_bus_scan(struct bcma_bus *bus)
1536 bus->nr_cores++;
1537 other_core = bcma_find_core_reverse(bus, core->id.id);
1538 core->core_unit = (other_core == NULL) ? 0 : other_core->core_unit + 1;
1539 + bcma_prepare_core(bus, core);
1540
1541 bcma_info(bus, "Core %d found: %s (manuf 0x%03X, id 0x%03X, rev 0x%02X, class 0x%X)\n",
1542 core->core_index, bcma_device_name(&core->id),
1543 --- a/drivers/bcma/sprom.c
1544 +++ b/drivers/bcma/sprom.c
1545 @@ -72,12 +72,12 @@ fail:
1546 * R/W ops.
1547 **************************************************/
1548
1549 -static void bcma_sprom_read(struct bcma_bus *bus, u16 offset, u16 *sprom)
1550 +static void bcma_sprom_read(struct bcma_bus *bus, u16 offset, u16 *sprom,
1551 + size_t words)
1552 {
1553 int i;
1554 - for (i = 0; i < SSB_SPROMSIZE_WORDS_R4; i++)
1555 - sprom[i] = bcma_read16(bus->drv_cc.core,
1556 - offset + (i * 2));
1557 + for (i = 0; i < words; i++)
1558 + sprom[i] = bcma_read16(bus->drv_cc.core, offset + (i * 2));
1559 }
1560
1561 /**************************************************
1562 @@ -124,29 +124,29 @@ static inline u8 bcma_crc8(u8 crc, u8 da
1563 return t[crc ^ data];
1564 }
1565
1566 -static u8 bcma_sprom_crc(const u16 *sprom)
1567 +static u8 bcma_sprom_crc(const u16 *sprom, size_t words)
1568 {
1569 int word;
1570 u8 crc = 0xFF;
1571
1572 - for (word = 0; word < SSB_SPROMSIZE_WORDS_R4 - 1; word++) {
1573 + for (word = 0; word < words - 1; word++) {
1574 crc = bcma_crc8(crc, sprom[word] & 0x00FF);
1575 crc = bcma_crc8(crc, (sprom[word] & 0xFF00) >> 8);
1576 }
1577 - crc = bcma_crc8(crc, sprom[SSB_SPROMSIZE_WORDS_R4 - 1] & 0x00FF);
1578 + crc = bcma_crc8(crc, sprom[words - 1] & 0x00FF);
1579 crc ^= 0xFF;
1580
1581 return crc;
1582 }
1583
1584 -static int bcma_sprom_check_crc(const u16 *sprom)
1585 +static int bcma_sprom_check_crc(const u16 *sprom, size_t words)
1586 {
1587 u8 crc;
1588 u8 expected_crc;
1589 u16 tmp;
1590
1591 - crc = bcma_sprom_crc(sprom);
1592 - tmp = sprom[SSB_SPROMSIZE_WORDS_R4 - 1] & SSB_SPROM_REVISION_CRC;
1593 + crc = bcma_sprom_crc(sprom, words);
1594 + tmp = sprom[words - 1] & SSB_SPROM_REVISION_CRC;
1595 expected_crc = tmp >> SSB_SPROM_REVISION_CRC_SHIFT;
1596 if (crc != expected_crc)
1597 return -EPROTO;
1598 @@ -154,21 +154,25 @@ static int bcma_sprom_check_crc(const u1
1599 return 0;
1600 }
1601
1602 -static int bcma_sprom_valid(const u16 *sprom)
1603 +static int bcma_sprom_valid(struct bcma_bus *bus, const u16 *sprom,
1604 + size_t words)
1605 {
1606 u16 revision;
1607 int err;
1608
1609 - err = bcma_sprom_check_crc(sprom);
1610 + err = bcma_sprom_check_crc(sprom, words);
1611 if (err)
1612 return err;
1613
1614 - revision = sprom[SSB_SPROMSIZE_WORDS_R4 - 1] & SSB_SPROM_REVISION_REV;
1615 - if (revision != 8 && revision != 9) {
1616 + revision = sprom[words - 1] & SSB_SPROM_REVISION_REV;
1617 + if (revision != 8 && revision != 9 && revision != 10) {
1618 pr_err("Unsupported SPROM revision: %d\n", revision);
1619 return -ENOENT;
1620 }
1621
1622 + bus->sprom.revision = revision;
1623 + bcma_debug(bus, "Found SPROM revision %d\n", revision);
1624 +
1625 return 0;
1626 }
1627
1628 @@ -197,6 +201,23 @@ static int bcma_sprom_valid(const u16 *s
1629 SPEX(_field[7], _offset + 14, _mask, _shift); \
1630 } while (0)
1631
1632 +static s8 sprom_extract_antgain(const u16 *in, u16 offset, u16 mask, u16 shift)
1633 +{
1634 + u16 v;
1635 + u8 gain;
1636 +
1637 + v = in[SPOFF(offset)];
1638 + gain = (v & mask) >> shift;
1639 + if (gain == 0xFF) {
1640 + gain = 8; /* If unset use 2dBm */
1641 + } else {
1642 + /* Q5.2 Fractional part is stored in 0xC0 */
1643 + gain = ((gain & 0xC0) >> 6) | ((gain & 0x3F) << 2);
1644 + }
1645 +
1646 + return (s8)gain;
1647 +}
1648 +
1649 static void bcma_sprom_extract_r8(struct bcma_bus *bus, const u16 *sprom)
1650 {
1651 u16 v, o;
1652 @@ -208,9 +229,6 @@ static void bcma_sprom_extract_r8(struct
1653 BUILD_BUG_ON(ARRAY_SIZE(pwr_info_offset) !=
1654 ARRAY_SIZE(bus->sprom.core_pwr_info));
1655
1656 - bus->sprom.revision = sprom[SSB_SPROMSIZE_WORDS_R4 - 1] &
1657 - SSB_SPROM_REVISION_REV;
1658 -
1659 for (i = 0; i < 3; i++) {
1660 v = sprom[SPOFF(SSB_SPROM8_IL0MAC) + i];
1661 *(((__be16 *)bus->sprom.il0mac) + i) = cpu_to_be16(v);
1662 @@ -380,14 +398,22 @@ static void bcma_sprom_extract_r8(struct
1663 SPEX32(ofdm5ghpo, SSB_SPROM8_OFDM5GHPO, ~0, 0);
1664
1665 /* Extract the antenna gain values. */
1666 - SPEX(antenna_gain.a0, SSB_SPROM8_AGAIN01,
1667 - SSB_SPROM8_AGAIN0, SSB_SPROM8_AGAIN0_SHIFT);
1668 - SPEX(antenna_gain.a1, SSB_SPROM8_AGAIN01,
1669 - SSB_SPROM8_AGAIN1, SSB_SPROM8_AGAIN1_SHIFT);
1670 - SPEX(antenna_gain.a2, SSB_SPROM8_AGAIN23,
1671 - SSB_SPROM8_AGAIN2, SSB_SPROM8_AGAIN2_SHIFT);
1672 - SPEX(antenna_gain.a3, SSB_SPROM8_AGAIN23,
1673 - SSB_SPROM8_AGAIN3, SSB_SPROM8_AGAIN3_SHIFT);
1674 + bus->sprom.antenna_gain.a0 = sprom_extract_antgain(sprom,
1675 + SSB_SPROM8_AGAIN01,
1676 + SSB_SPROM8_AGAIN0,
1677 + SSB_SPROM8_AGAIN0_SHIFT);
1678 + bus->sprom.antenna_gain.a1 = sprom_extract_antgain(sprom,
1679 + SSB_SPROM8_AGAIN01,
1680 + SSB_SPROM8_AGAIN1,
1681 + SSB_SPROM8_AGAIN1_SHIFT);
1682 + bus->sprom.antenna_gain.a2 = sprom_extract_antgain(sprom,
1683 + SSB_SPROM8_AGAIN23,
1684 + SSB_SPROM8_AGAIN2,
1685 + SSB_SPROM8_AGAIN2_SHIFT);
1686 + bus->sprom.antenna_gain.a3 = sprom_extract_antgain(sprom,
1687 + SSB_SPROM8_AGAIN23,
1688 + SSB_SPROM8_AGAIN3,
1689 + SSB_SPROM8_AGAIN3_SHIFT);
1690
1691 SPEX(leddc_on_time, SSB_SPROM8_LEDDC, SSB_SPROM8_LEDDC_ON,
1692 SSB_SPROM8_LEDDC_ON_SHIFT);
1693 @@ -502,12 +528,14 @@ static bool bcma_sprom_onchip_available(
1694 case BCMA_CHIP_ID_BCM4331:
1695 present = chip_status & BCMA_CC_CHIPST_4331_OTP_PRESENT;
1696 break;
1697 -
1698 + case BCMA_CHIP_ID_BCM43142:
1699 case BCMA_CHIP_ID_BCM43224:
1700 case BCMA_CHIP_ID_BCM43225:
1701 /* for these chips OTP is always available */
1702 present = true;
1703 break;
1704 + case BCMA_CHIP_ID_BCM43131:
1705 + case BCMA_CHIP_ID_BCM43217:
1706 case BCMA_CHIP_ID_BCM43227:
1707 case BCMA_CHIP_ID_BCM43228:
1708 case BCMA_CHIP_ID_BCM43428:
1709 @@ -550,7 +578,9 @@ int bcma_sprom_get(struct bcma_bus *bus)
1710 {
1711 u16 offset = BCMA_CC_SPROM;
1712 u16 *sprom;
1713 - int err = 0;
1714 + size_t sprom_sizes[] = { SSB_SPROMSIZE_WORDS_R4,
1715 + SSB_SPROMSIZE_WORDS_R10, };
1716 + int i, err = 0;
1717
1718 if (!bus->drv_cc.core)
1719 return -EOPNOTSUPP;
1720 @@ -579,32 +609,37 @@ int bcma_sprom_get(struct bcma_bus *bus)
1721 }
1722 }
1723
1724 - sprom = kcalloc(SSB_SPROMSIZE_WORDS_R4, sizeof(u16),
1725 - GFP_KERNEL);
1726 - if (!sprom)
1727 - return -ENOMEM;
1728 -
1729 if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4331 ||
1730 bus->chipinfo.id == BCMA_CHIP_ID_BCM43431)
1731 bcma_chipco_bcm4331_ext_pa_lines_ctl(&bus->drv_cc, false);
1732
1733 bcma_debug(bus, "SPROM offset 0x%x\n", offset);
1734 - bcma_sprom_read(bus, offset, sprom);
1735 + for (i = 0; i < ARRAY_SIZE(sprom_sizes); i++) {
1736 + size_t words = sprom_sizes[i];
1737 +
1738 + sprom = kcalloc(words, sizeof(u16), GFP_KERNEL);
1739 + if (!sprom)
1740 + return -ENOMEM;
1741 +
1742 + bcma_sprom_read(bus, offset, sprom, words);
1743 + err = bcma_sprom_valid(bus, sprom, words);
1744 + if (!err)
1745 + break;
1746 +
1747 + kfree(sprom);
1748 + }
1749
1750 if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4331 ||
1751 bus->chipinfo.id == BCMA_CHIP_ID_BCM43431)
1752 bcma_chipco_bcm4331_ext_pa_lines_ctl(&bus->drv_cc, true);
1753
1754 - err = bcma_sprom_valid(sprom);
1755 if (err) {
1756 - bcma_warn(bus, "invalid sprom read from the PCIe card, try to use fallback sprom\n");
1757 + bcma_warn(bus, "Invalid SPROM read from the PCIe card, trying to use fallback SPROM\n");
1758 err = bcma_fill_sprom_with_fallback(bus, &bus->sprom);
1759 - goto out;
1760 + } else {
1761 + bcma_sprom_extract_r8(bus, sprom);
1762 + kfree(sprom);
1763 }
1764
1765 - bcma_sprom_extract_r8(bus, sprom);
1766 -
1767 -out:
1768 - kfree(sprom);
1769 return err;
1770 }
1771 --- a/include/linux/bcma/bcma.h
1772 +++ b/include/linux/bcma/bcma.h
1773 @@ -6,6 +6,7 @@
1774
1775 #include <linux/bcma/bcma_driver_chipcommon.h>
1776 #include <linux/bcma/bcma_driver_pci.h>
1777 +#include <linux/bcma/bcma_driver_pcie2.h>
1778 #include <linux/bcma/bcma_driver_mips.h>
1779 #include <linux/bcma/bcma_driver_gmac_cmn.h>
1780 #include <linux/ssb/ssb.h> /* SPROM sharing */
1781 @@ -72,7 +73,19 @@ struct bcma_host_ops {
1782 /* Core-ID values. */
1783 #define BCMA_CORE_OOB_ROUTER 0x367 /* Out of band */
1784 #define BCMA_CORE_4706_CHIPCOMMON 0x500
1785 +#define BCMA_CORE_NS_PCIEG2 0x501
1786 +#define BCMA_CORE_NS_DMA 0x502
1787 +#define BCMA_CORE_NS_SDIO3 0x503
1788 +#define BCMA_CORE_NS_USB20 0x504
1789 +#define BCMA_CORE_NS_USB30 0x505
1790 +#define BCMA_CORE_NS_A9JTAG 0x506
1791 +#define BCMA_CORE_NS_DDR23 0x507
1792 +#define BCMA_CORE_NS_ROM 0x508
1793 +#define BCMA_CORE_NS_NAND 0x509
1794 +#define BCMA_CORE_NS_QSPI 0x50A
1795 +#define BCMA_CORE_NS_CHIPCOMMON_B 0x50B
1796 #define BCMA_CORE_4706_SOC_RAM 0x50E
1797 +#define BCMA_CORE_ARMCA9 0x510
1798 #define BCMA_CORE_4706_MAC_GBIT 0x52D
1799 #define BCMA_CORE_AMEMC 0x52E /* DDR1/2 memory controller core */
1800 #define BCMA_CORE_ALTA 0x534 /* I2S core */
1801 @@ -144,6 +157,10 @@ struct bcma_host_ops {
1802
1803 /* Chip IDs of PCIe devices */
1804 #define BCMA_CHIP_ID_BCM4313 0x4313
1805 +#define BCMA_CHIP_ID_BCM43142 43142
1806 +#define BCMA_CHIP_ID_BCM43131 43131
1807 +#define BCMA_CHIP_ID_BCM43217 43217
1808 +#define BCMA_CHIP_ID_BCM43222 43222
1809 #define BCMA_CHIP_ID_BCM43224 43224
1810 #define BCMA_PKG_ID_BCM43224_FAB_CSM 0x8
1811 #define BCMA_PKG_ID_BCM43224_FAB_SMIC 0xa
1812 @@ -176,6 +193,11 @@ struct bcma_host_ops {
1813 #define BCMA_PKG_ID_BCM5357 11
1814 #define BCMA_CHIP_ID_BCM53572 53572
1815 #define BCMA_PKG_ID_BCM47188 9
1816 +#define BCMA_CHIP_ID_BCM4707 53010
1817 +#define BCMA_PKG_ID_BCM4707 1
1818 +#define BCMA_PKG_ID_BCM4708 2
1819 +#define BCMA_PKG_ID_BCM4709 0
1820 +#define BCMA_CHIP_ID_BCM53018 53018
1821
1822 /* Board types (on PCI usually equals to the subsystem dev id) */
1823 /* BCM4313 */
1824 @@ -245,7 +267,7 @@ struct bcma_device {
1825 u8 core_unit;
1826
1827 u32 addr;
1828 - u32 addr1;
1829 + u32 addr_s[8];
1830 u32 wrap;
1831
1832 void __iomem *io_addr;
1833 @@ -301,6 +323,8 @@ struct bcma_bus {
1834 struct pci_dev *host_pci;
1835 /* Pointer to the SDIO device (only for BCMA_HOSTTYPE_SDIO) */
1836 struct sdio_func *host_sdio;
1837 + /* Pointer to platform device (only for BCMA_HOSTTYPE_SOC) */
1838 + struct platform_device *host_pdev;
1839 };
1840
1841 struct bcma_chipinfo chipinfo;
1842 @@ -310,11 +334,12 @@ struct bcma_bus {
1843 struct bcma_device *mapped_core;
1844 struct list_head cores;
1845 u8 nr_cores;
1846 - u8 init_done:1;
1847 u8 num;
1848
1849 struct bcma_drv_cc drv_cc;
1850 + struct bcma_drv_cc_b drv_cc_b;
1851 struct bcma_drv_pci drv_pci[2];
1852 + struct bcma_drv_pcie2 drv_pcie2;
1853 struct bcma_drv_mips drv_mips;
1854 struct bcma_drv_gmac_cmn drv_gmac_cmn;
1855
1856 @@ -400,7 +425,14 @@ static inline void bcma_maskset16(struct
1857 bcma_write16(cc, offset, (bcma_read16(cc, offset) & mask) | set);
1858 }
1859
1860 -extern struct bcma_device *bcma_find_core(struct bcma_bus *bus, u16 coreid);
1861 +extern struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
1862 + u8 unit);
1863 +static inline struct bcma_device *bcma_find_core(struct bcma_bus *bus,
1864 + u16 coreid)
1865 +{
1866 + return bcma_find_core_unit(bus, coreid, 0);
1867 +}
1868 +
1869 extern bool bcma_core_is_enabled(struct bcma_device *core);
1870 extern void bcma_core_disable(struct bcma_device *core, u32 flags);
1871 extern int bcma_core_enable(struct bcma_device *core, u32 flags);
1872 @@ -415,4 +447,6 @@ extern u32 bcma_chipco_pll_read(struct b
1873 #define BCMA_DMA_TRANSLATION_DMA64_CMT 0x80000000 /* Client Mode Translation for 64-bit DMA */
1874 extern u32 bcma_core_dma_translation(struct bcma_device *core);
1875
1876 +extern unsigned int bcma_core_irq(struct bcma_device *core, int num);
1877 +
1878 #endif /* LINUX_BCMA_H_ */
1879 --- a/include/linux/bcma/bcma_driver_chipcommon.h
1880 +++ b/include/linux/bcma/bcma_driver_chipcommon.h
1881 @@ -330,6 +330,8 @@
1882 #define BCMA_CC_PMU_CAP 0x0604 /* PMU capabilities */
1883 #define BCMA_CC_PMU_CAP_REVISION 0x000000FF /* Revision mask */
1884 #define BCMA_CC_PMU_STAT 0x0608 /* PMU status */
1885 +#define BCMA_CC_PMU_STAT_EXT_LPO_AVAIL 0x00000100
1886 +#define BCMA_CC_PMU_STAT_WDRESET 0x00000080
1887 #define BCMA_CC_PMU_STAT_INTPEND 0x00000040 /* Interrupt pending */
1888 #define BCMA_CC_PMU_STAT_SBCLKST 0x00000030 /* Backplane clock status? */
1889 #define BCMA_CC_PMU_STAT_HAVEALP 0x00000008 /* ALP available */
1890 @@ -355,6 +357,11 @@
1891 #define BCMA_CC_REGCTL_DATA 0x065C
1892 #define BCMA_CC_PLLCTL_ADDR 0x0660
1893 #define BCMA_CC_PLLCTL_DATA 0x0664
1894 +#define BCMA_CC_PMU_STRAPOPT 0x0668 /* (corerev >= 28) */
1895 +#define BCMA_CC_PMU_XTAL_FREQ 0x066C /* (pmurev >= 10) */
1896 +#define BCMA_CC_PMU_XTAL_FREQ_ILPCTL_MASK 0x00001FFF
1897 +#define BCMA_CC_PMU_XTAL_FREQ_MEASURE_MASK 0x80000000
1898 +#define BCMA_CC_PMU_XTAL_FREQ_MEASURE_SHIFT 31
1899 #define BCMA_CC_SPROM 0x0800 /* SPROM beginning */
1900 /* NAND flash MLC controller registers (corerev >= 38) */
1901 #define BCMA_CC_NAND_REVISION 0x0C00
1902 @@ -435,6 +442,23 @@
1903 #define BCMA_CC_PMU6_4706_PROC_NDIV_MODE_MASK 0x00000007
1904 #define BCMA_CC_PMU6_4706_PROC_NDIV_MODE_SHIFT 0
1905
1906 +/* PMU rev 15 */
1907 +#define BCMA_CC_PMU15_PLL_PLLCTL0 0
1908 +#define BCMA_CC_PMU15_PLL_PC0_CLKSEL_MASK 0x00000003
1909 +#define BCMA_CC_PMU15_PLL_PC0_CLKSEL_SHIFT 0
1910 +#define BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK 0x003FFFFC
1911 +#define BCMA_CC_PMU15_PLL_PC0_FREQTGT_SHIFT 2
1912 +#define BCMA_CC_PMU15_PLL_PC0_PRESCALE_MASK 0x00C00000
1913 +#define BCMA_CC_PMU15_PLL_PC0_PRESCALE_SHIFT 22
1914 +#define BCMA_CC_PMU15_PLL_PC0_KPCTRL_MASK 0x07000000
1915 +#define BCMA_CC_PMU15_PLL_PC0_KPCTRL_SHIFT 24
1916 +#define BCMA_CC_PMU15_PLL_PC0_FCNTCTRL_MASK 0x38000000
1917 +#define BCMA_CC_PMU15_PLL_PC0_FCNTCTRL_SHIFT 27
1918 +#define BCMA_CC_PMU15_PLL_PC0_FDCMODE_MASK 0x40000000
1919 +#define BCMA_CC_PMU15_PLL_PC0_FDCMODE_SHIFT 30
1920 +#define BCMA_CC_PMU15_PLL_PC0_CTRLBIAS_MASK 0x80000000
1921 +#define BCMA_CC_PMU15_PLL_PC0_CTRLBIAS_SHIFT 31
1922 +
1923 /* ALP clock on pre-PMU chips */
1924 #define BCMA_CC_PMU_ALP_CLOCK 20000000
1925 /* HT clock for systems with PMU-enabled chipcommon */
1926 @@ -507,6 +531,37 @@
1927 #define BCMA_CHIPCTL_5357_I2S_PINS_ENABLE BIT(18)
1928 #define BCMA_CHIPCTL_5357_I2CSPI_PINS_ENABLE BIT(19)
1929
1930 +#define BCMA_RES_4314_LPLDO_PU BIT(0)
1931 +#define BCMA_RES_4314_PMU_SLEEP_DIS BIT(1)
1932 +#define BCMA_RES_4314_PMU_BG_PU BIT(2)
1933 +#define BCMA_RES_4314_CBUCK_LPOM_PU BIT(3)
1934 +#define BCMA_RES_4314_CBUCK_PFM_PU BIT(4)
1935 +#define BCMA_RES_4314_CLDO_PU BIT(5)
1936 +#define BCMA_RES_4314_LPLDO2_LVM BIT(6)
1937 +#define BCMA_RES_4314_WL_PMU_PU BIT(7)
1938 +#define BCMA_RES_4314_LNLDO_PU BIT(8)
1939 +#define BCMA_RES_4314_LDO3P3_PU BIT(9)
1940 +#define BCMA_RES_4314_OTP_PU BIT(10)
1941 +#define BCMA_RES_4314_XTAL_PU BIT(11)
1942 +#define BCMA_RES_4314_WL_PWRSW_PU BIT(12)
1943 +#define BCMA_RES_4314_LQ_AVAIL BIT(13)
1944 +#define BCMA_RES_4314_LOGIC_RET BIT(14)
1945 +#define BCMA_RES_4314_MEM_SLEEP BIT(15)
1946 +#define BCMA_RES_4314_MACPHY_RET BIT(16)
1947 +#define BCMA_RES_4314_WL_CORE_READY BIT(17)
1948 +#define BCMA_RES_4314_ILP_REQ BIT(18)
1949 +#define BCMA_RES_4314_ALP_AVAIL BIT(19)
1950 +#define BCMA_RES_4314_MISC_PWRSW_PU BIT(20)
1951 +#define BCMA_RES_4314_SYNTH_PWRSW_PU BIT(21)
1952 +#define BCMA_RES_4314_RX_PWRSW_PU BIT(22)
1953 +#define BCMA_RES_4314_RADIO_PU BIT(23)
1954 +#define BCMA_RES_4314_VCO_LDO_PU BIT(24)
1955 +#define BCMA_RES_4314_AFE_LDO_PU BIT(25)
1956 +#define BCMA_RES_4314_RX_LDO_PU BIT(26)
1957 +#define BCMA_RES_4314_TX_LDO_PU BIT(27)
1958 +#define BCMA_RES_4314_HT_AVAIL BIT(28)
1959 +#define BCMA_RES_4314_MACPHY_CLK_AVAIL BIT(29)
1960 +
1961 /* Data for the PMU, if available.
1962 * Check availability with ((struct bcma_chipcommon)->capabilities & BCMA_CC_CAP_PMU)
1963 */
1964 @@ -585,9 +640,16 @@ struct bcma_drv_cc {
1965 spinlock_t gpio_lock;
1966 #ifdef CONFIG_BCMA_DRIVER_GPIO
1967 struct gpio_chip gpio;
1968 + struct irq_domain *irq_domain;
1969 #endif
1970 };
1971
1972 +struct bcma_drv_cc_b {
1973 + struct bcma_device *core;
1974 + u8 setup_done:1;
1975 + void __iomem *mii;
1976 +};
1977 +
1978 /* Register access */
1979 #define bcma_cc_read32(cc, offset) \
1980 bcma_read32((cc)->core, offset)
1981 @@ -643,4 +705,6 @@ extern void bcma_pmu_spuravoid_pllupdate
1982
1983 extern u32 bcma_pmu_get_bus_clock(struct bcma_drv_cc *cc);
1984
1985 +void bcma_chipco_b_mii_write(struct bcma_drv_cc_b *ccb, u32 offset, u32 value);
1986 +
1987 #endif /* LINUX_BCMA_DRIVER_CC_H_ */
1988 --- a/include/linux/bcma/bcma_driver_mips.h
1989 +++ b/include/linux/bcma/bcma_driver_mips.h
1990 @@ -43,12 +43,12 @@ struct bcma_drv_mips {
1991 extern void bcma_core_mips_init(struct bcma_drv_mips *mcore);
1992 extern void bcma_core_mips_early_init(struct bcma_drv_mips *mcore);
1993
1994 -extern unsigned int bcma_core_irq(struct bcma_device *core);
1995 +extern unsigned int bcma_core_mips_irq(struct bcma_device *dev);
1996 #else
1997 static inline void bcma_core_mips_init(struct bcma_drv_mips *mcore) { }
1998 static inline void bcma_core_mips_early_init(struct bcma_drv_mips *mcore) { }
1999
2000 -static inline unsigned int bcma_core_irq(struct bcma_device *core)
2001 +static inline unsigned int bcma_core_mips_irq(struct bcma_device *dev)
2002 {
2003 return 0;
2004 }
2005 --- a/include/linux/bcma/bcma_driver_pci.h
2006 +++ b/include/linux/bcma/bcma_driver_pci.h
2007 @@ -181,10 +181,31 @@ struct pci_dev;
2008
2009 #define BCMA_CORE_PCI_CFG_DEVCTRL 0xd8
2010
2011 +#define BCMA_CORE_PCI_
2012 +
2013 +/* MDIO devices (SERDES modules) */
2014 +#define BCMA_CORE_PCI_MDIO_IEEE0 0x000
2015 +#define BCMA_CORE_PCI_MDIO_IEEE1 0x001
2016 +#define BCMA_CORE_PCI_MDIO_BLK0 0x800
2017 +#define BCMA_CORE_PCI_MDIO_BLK1 0x801
2018 +#define BCMA_CORE_PCI_MDIO_BLK1_MGMT0 0x16
2019 +#define BCMA_CORE_PCI_MDIO_BLK1_MGMT1 0x17
2020 +#define BCMA_CORE_PCI_MDIO_BLK1_MGMT2 0x18
2021 +#define BCMA_CORE_PCI_MDIO_BLK1_MGMT3 0x19
2022 +#define BCMA_CORE_PCI_MDIO_BLK1_MGMT4 0x1A
2023 +#define BCMA_CORE_PCI_MDIO_BLK2 0x802
2024 +#define BCMA_CORE_PCI_MDIO_BLK3 0x803
2025 +#define BCMA_CORE_PCI_MDIO_BLK4 0x804
2026 +#define BCMA_CORE_PCI_MDIO_TXPLL 0x808 /* TXPLL register block idx */
2027 +#define BCMA_CORE_PCI_MDIO_TXCTRL0 0x820
2028 +#define BCMA_CORE_PCI_MDIO_SERDESID 0x831
2029 +#define BCMA_CORE_PCI_MDIO_RXCTRL0 0x840
2030 +
2031 /* PCIE Root Capability Register bits (Host mode only) */
2032 #define BCMA_CORE_PCI_RC_CRS_VISIBILITY 0x0001
2033
2034 struct bcma_drv_pci;
2035 +struct bcma_bus;
2036
2037 #ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
2038 struct bcma_drv_pci_host {
2039 @@ -219,7 +240,9 @@ struct bcma_drv_pci {
2040 extern void bcma_core_pci_init(struct bcma_drv_pci *pc);
2041 extern int bcma_core_pci_irq_ctl(struct bcma_drv_pci *pc,
2042 struct bcma_device *core, bool enable);
2043 -extern void bcma_core_pci_extend_L1timer(struct bcma_drv_pci *pc, bool extend);
2044 +extern void bcma_core_pci_up(struct bcma_bus *bus);
2045 +extern void bcma_core_pci_down(struct bcma_bus *bus);
2046 +extern void bcma_core_pci_power_save(struct bcma_bus *bus, bool up);
2047
2048 extern int bcma_core_pci_pcibios_map_irq(const struct pci_dev *dev);
2049 extern int bcma_core_pci_plat_dev_init(struct pci_dev *dev);
2050 --- /dev/null
2051 +++ b/include/linux/bcma/bcma_driver_pcie2.h
2052 @@ -0,0 +1,158 @@
2053 +#ifndef LINUX_BCMA_DRIVER_PCIE2_H_
2054 +#define LINUX_BCMA_DRIVER_PCIE2_H_
2055 +
2056 +#define BCMA_CORE_PCIE2_CLK_CONTROL 0x0000
2057 +#define PCIE2_CLKC_RST_OE 0x0001 /* When set, drives PCI_RESET out to pin */
2058 +#define PCIE2_CLKC_RST 0x0002 /* Value driven out to pin */
2059 +#define PCIE2_CLKC_SPERST 0x0004 /* SurvivePeRst */
2060 +#define PCIE2_CLKC_DISABLE_L1CLK_GATING 0x0010
2061 +#define PCIE2_CLKC_DLYPERST 0x0100 /* Delay PeRst to CoE Core */
2062 +#define PCIE2_CLKC_DISSPROMLD 0x0200 /* DisableSpromLoadOnPerst */
2063 +#define PCIE2_CLKC_WAKE_MODE_L2 0x1000 /* Wake on L2 */
2064 +#define BCMA_CORE_PCIE2_RC_PM_CONTROL 0x0004
2065 +#define BCMA_CORE_PCIE2_RC_PM_STATUS 0x0008
2066 +#define BCMA_CORE_PCIE2_EP_PM_CONTROL 0x000C
2067 +#define BCMA_CORE_PCIE2_EP_PM_STATUS 0x0010
2068 +#define BCMA_CORE_PCIE2_EP_LTR_CONTROL 0x0014
2069 +#define BCMA_CORE_PCIE2_EP_LTR_STATUS 0x0018
2070 +#define BCMA_CORE_PCIE2_EP_OBFF_STATUS 0x001C
2071 +#define BCMA_CORE_PCIE2_PCIE_ERR_STATUS 0x0020
2072 +#define BCMA_CORE_PCIE2_RC_AXI_CONFIG 0x0100
2073 +#define BCMA_CORE_PCIE2_EP_AXI_CONFIG 0x0104
2074 +#define BCMA_CORE_PCIE2_RXDEBUG_STATUS0 0x0108
2075 +#define BCMA_CORE_PCIE2_RXDEBUG_CONTROL0 0x010C
2076 +#define BCMA_CORE_PCIE2_CONFIGINDADDR 0x0120
2077 +#define BCMA_CORE_PCIE2_CONFIGINDDATA 0x0124
2078 +#define BCMA_CORE_PCIE2_MDIOCONTROL 0x0128
2079 +#define BCMA_CORE_PCIE2_MDIOWRDATA 0x012C
2080 +#define BCMA_CORE_PCIE2_MDIORDDATA 0x0130
2081 +#define BCMA_CORE_PCIE2_DATAINTF 0x0180
2082 +#define BCMA_CORE_PCIE2_D2H_INTRLAZY_0 0x0188
2083 +#define BCMA_CORE_PCIE2_H2D_INTRLAZY_0 0x018c
2084 +#define BCMA_CORE_PCIE2_H2D_INTSTAT_0 0x0190
2085 +#define BCMA_CORE_PCIE2_H2D_INTMASK_0 0x0194
2086 +#define BCMA_CORE_PCIE2_D2H_INTSTAT_0 0x0198
2087 +#define BCMA_CORE_PCIE2_D2H_INTMASK_0 0x019c
2088 +#define BCMA_CORE_PCIE2_LTR_STATE 0x01A0 /* Latency Tolerance Reporting */
2089 +#define PCIE2_LTR_ACTIVE 2
2090 +#define PCIE2_LTR_ACTIVE_IDLE 1
2091 +#define PCIE2_LTR_SLEEP 0
2092 +#define PCIE2_LTR_FINAL_MASK 0x300
2093 +#define PCIE2_LTR_FINAL_SHIFT 8
2094 +#define BCMA_CORE_PCIE2_PWR_INT_STATUS 0x01A4
2095 +#define BCMA_CORE_PCIE2_PWR_INT_MASK 0x01A8
2096 +#define BCMA_CORE_PCIE2_CFG_ADDR 0x01F8
2097 +#define BCMA_CORE_PCIE2_CFG_DATA 0x01FC
2098 +#define BCMA_CORE_PCIE2_SYS_EQ_PAGE 0x0200
2099 +#define BCMA_CORE_PCIE2_SYS_MSI_PAGE 0x0204
2100 +#define BCMA_CORE_PCIE2_SYS_MSI_INTREN 0x0208
2101 +#define BCMA_CORE_PCIE2_SYS_MSI_CTRL0 0x0210
2102 +#define BCMA_CORE_PCIE2_SYS_MSI_CTRL1 0x0214
2103 +#define BCMA_CORE_PCIE2_SYS_MSI_CTRL2 0x0218
2104 +#define BCMA_CORE_PCIE2_SYS_MSI_CTRL3 0x021C
2105 +#define BCMA_CORE_PCIE2_SYS_MSI_CTRL4 0x0220
2106 +#define BCMA_CORE_PCIE2_SYS_MSI_CTRL5 0x0224
2107 +#define BCMA_CORE_PCIE2_SYS_EQ_HEAD0 0x0250
2108 +#define BCMA_CORE_PCIE2_SYS_EQ_TAIL0 0x0254
2109 +#define BCMA_CORE_PCIE2_SYS_EQ_HEAD1 0x0258
2110 +#define BCMA_CORE_PCIE2_SYS_EQ_TAIL1 0x025C
2111 +#define BCMA_CORE_PCIE2_SYS_EQ_HEAD2 0x0260
2112 +#define BCMA_CORE_PCIE2_SYS_EQ_TAIL2 0x0264
2113 +#define BCMA_CORE_PCIE2_SYS_EQ_HEAD3 0x0268
2114 +#define BCMA_CORE_PCIE2_SYS_EQ_TAIL3 0x026C
2115 +#define BCMA_CORE_PCIE2_SYS_EQ_HEAD4 0x0270
2116 +#define BCMA_CORE_PCIE2_SYS_EQ_TAIL4 0x0274
2117 +#define BCMA_CORE_PCIE2_SYS_EQ_HEAD5 0x0278
2118 +#define BCMA_CORE_PCIE2_SYS_EQ_TAIL5 0x027C
2119 +#define BCMA_CORE_PCIE2_SYS_RC_INTX_EN 0x0330
2120 +#define BCMA_CORE_PCIE2_SYS_RC_INTX_CSR 0x0334
2121 +#define BCMA_CORE_PCIE2_SYS_MSI_REQ 0x0340
2122 +#define BCMA_CORE_PCIE2_SYS_HOST_INTR_EN 0x0344
2123 +#define BCMA_CORE_PCIE2_SYS_HOST_INTR_CSR 0x0348
2124 +#define BCMA_CORE_PCIE2_SYS_HOST_INTR0 0x0350
2125 +#define BCMA_CORE_PCIE2_SYS_HOST_INTR1 0x0354
2126 +#define BCMA_CORE_PCIE2_SYS_HOST_INTR2 0x0358
2127 +#define BCMA_CORE_PCIE2_SYS_HOST_INTR3 0x035C
2128 +#define BCMA_CORE_PCIE2_SYS_EP_INT_EN0 0x0360
2129 +#define BCMA_CORE_PCIE2_SYS_EP_INT_EN1 0x0364
2130 +#define BCMA_CORE_PCIE2_SYS_EP_INT_CSR0 0x0370
2131 +#define BCMA_CORE_PCIE2_SYS_EP_INT_CSR1 0x0374
2132 +#define BCMA_CORE_PCIE2_SPROM(wordoffset) (0x0800 + ((wordoffset) * 2))
2133 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_0 0x0C00
2134 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_1 0x0C04
2135 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_2 0x0C08
2136 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_3 0x0C0C
2137 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_4 0x0C10
2138 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_5 0x0C14
2139 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_6 0x0C18
2140 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_7 0x0C1C
2141 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_0 0x0C20
2142 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_1 0x0C24
2143 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_2 0x0C28
2144 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_3 0x0C2C
2145 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_4 0x0C30
2146 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_5 0x0C34
2147 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_6 0x0C38
2148 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_7 0x0C3C
2149 +#define BCMA_CORE_PCIE2_FUNC0_IMAP1 0x0C80
2150 +#define BCMA_CORE_PCIE2_FUNC1_IMAP1 0x0C88
2151 +#define BCMA_CORE_PCIE2_FUNC0_IMAP2 0x0CC0
2152 +#define BCMA_CORE_PCIE2_FUNC1_IMAP2 0x0CC8
2153 +#define BCMA_CORE_PCIE2_IARR0_LOWER 0x0D00
2154 +#define BCMA_CORE_PCIE2_IARR0_UPPER 0x0D04
2155 +#define BCMA_CORE_PCIE2_IARR1_LOWER 0x0D08
2156 +#define BCMA_CORE_PCIE2_IARR1_UPPER 0x0D0C
2157 +#define BCMA_CORE_PCIE2_IARR2_LOWER 0x0D10
2158 +#define BCMA_CORE_PCIE2_IARR2_UPPER 0x0D14
2159 +#define BCMA_CORE_PCIE2_OARR0 0x0D20
2160 +#define BCMA_CORE_PCIE2_OARR1 0x0D28
2161 +#define BCMA_CORE_PCIE2_OARR2 0x0D30
2162 +#define BCMA_CORE_PCIE2_OMAP0_LOWER 0x0D40
2163 +#define BCMA_CORE_PCIE2_OMAP0_UPPER 0x0D44
2164 +#define BCMA_CORE_PCIE2_OMAP1_LOWER 0x0D48
2165 +#define BCMA_CORE_PCIE2_OMAP1_UPPER 0x0D4C
2166 +#define BCMA_CORE_PCIE2_OMAP2_LOWER 0x0D50
2167 +#define BCMA_CORE_PCIE2_OMAP2_UPPER 0x0D54
2168 +#define BCMA_CORE_PCIE2_FUNC1_IARR1_SIZE 0x0D58
2169 +#define BCMA_CORE_PCIE2_FUNC1_IARR2_SIZE 0x0D5C
2170 +#define BCMA_CORE_PCIE2_MEM_CONTROL 0x0F00
2171 +#define BCMA_CORE_PCIE2_MEM_ECC_ERRLOG0 0x0F04
2172 +#define BCMA_CORE_PCIE2_MEM_ECC_ERRLOG1 0x0F08
2173 +#define BCMA_CORE_PCIE2_LINK_STATUS 0x0F0C
2174 +#define BCMA_CORE_PCIE2_STRAP_STATUS 0x0F10
2175 +#define BCMA_CORE_PCIE2_RESET_STATUS 0x0F14
2176 +#define BCMA_CORE_PCIE2_RESETEN_IN_LINKDOWN 0x0F18
2177 +#define BCMA_CORE_PCIE2_MISC_INTR_EN 0x0F1C
2178 +#define BCMA_CORE_PCIE2_TX_DEBUG_CFG 0x0F20
2179 +#define BCMA_CORE_PCIE2_MISC_CONFIG 0x0F24
2180 +#define BCMA_CORE_PCIE2_MISC_STATUS 0x0F28
2181 +#define BCMA_CORE_PCIE2_INTR_EN 0x0F30
2182 +#define BCMA_CORE_PCIE2_INTR_CLEAR 0x0F34
2183 +#define BCMA_CORE_PCIE2_INTR_STATUS 0x0F38
2184 +
2185 +/* PCIE gen2 config regs */
2186 +#define PCIE2_INTSTATUS 0x090
2187 +#define PCIE2_INTMASK 0x094
2188 +#define PCIE2_SBMBX 0x098
2189 +
2190 +#define PCIE2_PMCR_REFUP 0x1814 /* Trefup time */
2191 +
2192 +#define PCIE2_CAP_DEVSTSCTRL2_OFFSET 0xD4
2193 +#define PCIE2_CAP_DEVSTSCTRL2_LTRENAB 0x400
2194 +#define PCIE2_PVT_REG_PM_CLK_PERIOD 0x184c
2195 +
2196 +struct bcma_drv_pcie2 {
2197 + struct bcma_device *core;
2198 +};
2199 +
2200 +#define pcie2_read16(pcie2, offset) bcma_read16((pcie2)->core, offset)
2201 +#define pcie2_read32(pcie2, offset) bcma_read32((pcie2)->core, offset)
2202 +#define pcie2_write16(pcie2, offset, val) bcma_write16((pcie2)->core, offset, val)
2203 +#define pcie2_write32(pcie2, offset, val) bcma_write32((pcie2)->core, offset, val)
2204 +
2205 +#define pcie2_set32(pcie2, offset, set) bcma_set32((pcie2)->core, offset, set)
2206 +#define pcie2_mask32(pcie2, offset, mask) bcma_mask32((pcie2)->core, offset, mask)
2207 +
2208 +void bcma_core_pcie2_init(struct bcma_drv_pcie2 *pcie2);
2209 +
2210 +#endif /* LINUX_BCMA_DRIVER_PCIE2_H_ */
2211 --- a/drivers/net/wireless/brcm80211/brcmsmac/aiutils.c
2212 +++ b/drivers/net/wireless/brcm80211/brcmsmac/aiutils.c
2213 @@ -679,27 +679,6 @@ bool ai_clkctl_cc(struct si_pub *sih, en
2214 return mode == BCMA_CLKMODE_FAST;
2215 }
2216
2217 -void ai_pci_up(struct si_pub *sih)
2218 -{
2219 - struct si_info *sii;
2220 -
2221 - sii = container_of(sih, struct si_info, pub);
2222 -
2223 - if (sii->icbus->hosttype == BCMA_HOSTTYPE_PCI)
2224 - bcma_core_pci_extend_L1timer(&sii->icbus->drv_pci[0], true);
2225 -}
2226 -
2227 -/* Unconfigure and/or apply various WARs when going down */
2228 -void ai_pci_down(struct si_pub *sih)
2229 -{
2230 - struct si_info *sii;
2231 -
2232 - sii = container_of(sih, struct si_info, pub);
2233 -
2234 - if (sii->icbus->hosttype == BCMA_HOSTTYPE_PCI)
2235 - bcma_core_pci_extend_L1timer(&sii->icbus->drv_pci[0], false);
2236 -}
2237 -
2238 /* Enable BT-COEX & Ex-PA for 4313 */
2239 void ai_epa_4313war(struct si_pub *sih)
2240 {
2241 --- a/drivers/net/wireless/brcm80211/brcmsmac/aiutils.h
2242 +++ b/drivers/net/wireless/brcm80211/brcmsmac/aiutils.h
2243 @@ -183,9 +183,6 @@ extern u16 ai_clkctl_fast_pwrup_delay(st
2244 extern bool ai_clkctl_cc(struct si_pub *sih, enum bcma_clkmode mode);
2245 extern bool ai_deviceremoved(struct si_pub *sih);
2246
2247 -extern void ai_pci_down(struct si_pub *sih);
2248 -extern void ai_pci_up(struct si_pub *sih);
2249 -
2250 /* Enable Ex-PA for 4313 */
2251 extern void ai_epa_4313war(struct si_pub *sih);
2252
2253 --- a/drivers/net/wireless/brcm80211/brcmsmac/main.c
2254 +++ b/drivers/net/wireless/brcm80211/brcmsmac/main.c
2255 @@ -4667,7 +4667,7 @@ static int brcms_b_attach(struct brcms_c
2256 brcms_c_coredisable(wlc_hw);
2257
2258 /* Match driver "down" state */
2259 - ai_pci_down(wlc_hw->sih);
2260 + bcma_core_pci_down(wlc_hw->d11core->bus);
2261
2262 /* turn off pll and xtal to match driver "down" state */
2263 brcms_b_xtal(wlc_hw, OFF);
2264 @@ -5010,12 +5010,12 @@ static int brcms_b_up_prep(struct brcms_
2265 */
2266 if (brcms_b_radio_read_hwdisabled(wlc_hw)) {
2267 /* put SB PCI in down state again */
2268 - ai_pci_down(wlc_hw->sih);
2269 + bcma_core_pci_down(wlc_hw->d11core->bus);
2270 brcms_b_xtal(wlc_hw, OFF);
2271 return -ENOMEDIUM;
2272 }
2273
2274 - ai_pci_up(wlc_hw->sih);
2275 + bcma_core_pci_up(wlc_hw->d11core->bus);
2276
2277 /* reset the d11 core */
2278 brcms_b_corereset(wlc_hw, BRCMS_USE_COREFLAGS);
2279 @@ -5212,7 +5212,7 @@ static int brcms_b_down_finish(struct br
2280
2281 /* turn off primary xtal and pll */
2282 if (!wlc_hw->noreset) {
2283 - ai_pci_down(wlc_hw->sih);
2284 + bcma_core_pci_down(wlc_hw->d11core->bus);
2285 brcms_b_xtal(wlc_hw, OFF);
2286 }
2287 }
2288 --- a/drivers/bcma/driver_mips.c
2289 +++ b/drivers/bcma/driver_mips.c
2290 @@ -21,6 +21,14 @@
2291 #include <linux/serial_reg.h>
2292 #include <linux/time.h>
2293
2294 +enum bcma_boot_dev {
2295 + BCMA_BOOT_DEV_UNK = 0,
2296 + BCMA_BOOT_DEV_ROM,
2297 + BCMA_BOOT_DEV_PARALLEL,
2298 + BCMA_BOOT_DEV_SERIAL,
2299 + BCMA_BOOT_DEV_NAND,
2300 +};
2301 +
2302 static const char * const part_probes[] = { "bcm47xxpart", NULL };
2303
2304 static struct physmap_flash_data bcma_pflash_data = {
2305 @@ -107,7 +115,7 @@ static u32 bcma_core_mips_irqflag(struct
2306 * If disabled, 5 is returned.
2307 * If not supported, 6 is returned.
2308 */
2309 -static unsigned int bcma_core_mips_irq(struct bcma_device *dev)
2310 +unsigned int bcma_core_mips_irq(struct bcma_device *dev)
2311 {
2312 struct bcma_device *mdev = dev->bus->drv_mips.core;
2313 u32 irqflag;
2314 @@ -125,13 +133,6 @@ static unsigned int bcma_core_mips_irq(s
2315 return 5;
2316 }
2317
2318 -unsigned int bcma_core_irq(struct bcma_device *dev)
2319 -{
2320 - unsigned int mips_irq = bcma_core_mips_irq(dev);
2321 - return mips_irq <= 4 ? mips_irq + 2 : 0;
2322 -}
2323 -EXPORT_SYMBOL(bcma_core_irq);
2324 -
2325 static void bcma_core_mips_set_irq(struct bcma_device *dev, unsigned int irq)
2326 {
2327 unsigned int oldirq = bcma_core_mips_irq(dev);
2328 @@ -229,11 +230,51 @@ u32 bcma_cpu_clock(struct bcma_drv_mips
2329 }
2330 EXPORT_SYMBOL(bcma_cpu_clock);
2331
2332 +static enum bcma_boot_dev bcma_boot_dev(struct bcma_bus *bus)
2333 +{
2334 + struct bcma_drv_cc *cc = &bus->drv_cc;
2335 + u8 cc_rev = cc->core->id.rev;
2336 +
2337 + if (cc_rev == 42) {
2338 + struct bcma_device *core;
2339 +
2340 + core = bcma_find_core(bus, BCMA_CORE_NS_ROM);
2341 + if (core) {
2342 + switch (bcma_aread32(core, BCMA_IOST) &
2343 + BCMA_NS_ROM_IOST_BOOT_DEV_MASK) {
2344 + case BCMA_NS_ROM_IOST_BOOT_DEV_NOR:
2345 + return BCMA_BOOT_DEV_SERIAL;
2346 + case BCMA_NS_ROM_IOST_BOOT_DEV_NAND:
2347 + return BCMA_BOOT_DEV_NAND;
2348 + case BCMA_NS_ROM_IOST_BOOT_DEV_ROM:
2349 + default:
2350 + return BCMA_BOOT_DEV_ROM;
2351 + }
2352 + }
2353 + } else {
2354 + if (cc_rev == 38) {
2355 + if (cc->status & BCMA_CC_CHIPST_5357_NAND_BOOT)
2356 + return BCMA_BOOT_DEV_NAND;
2357 + else if (cc->status & BIT(5))
2358 + return BCMA_BOOT_DEV_ROM;
2359 + }
2360 +
2361 + if ((cc->capabilities & BCMA_CC_CAP_FLASHT) ==
2362 + BCMA_CC_FLASHT_PARA)
2363 + return BCMA_BOOT_DEV_PARALLEL;
2364 + else
2365 + return BCMA_BOOT_DEV_SERIAL;
2366 + }
2367 +
2368 + return BCMA_BOOT_DEV_SERIAL;
2369 +}
2370 +
2371 static void bcma_core_mips_flash_detect(struct bcma_drv_mips *mcore)
2372 {
2373 struct bcma_bus *bus = mcore->core->bus;
2374 struct bcma_drv_cc *cc = &bus->drv_cc;
2375 struct bcma_pflash *pflash = &cc->pflash;
2376 + enum bcma_boot_dev boot_dev;
2377
2378 switch (cc->capabilities & BCMA_CC_CAP_FLASHT) {
2379 case BCMA_CC_FLASHT_STSER:
2380 @@ -269,6 +310,20 @@ static void bcma_core_mips_flash_detect(
2381 bcma_nflash_init(cc);
2382 }
2383 }
2384 +
2385 + /* Determine flash type this SoC boots from */
2386 + boot_dev = bcma_boot_dev(bus);
2387 + switch (boot_dev) {
2388 + case BCMA_BOOT_DEV_PARALLEL:
2389 + case BCMA_BOOT_DEV_SERIAL:
2390 + /* TODO: Init NVRAM using BCMA_SOC_FLASH2 window */
2391 + break;
2392 + case BCMA_BOOT_DEV_NAND:
2393 + /* TODO: Init NVRAM using BCMA_SOC_FLASH1 window */
2394 + break;
2395 + default:
2396 + break;
2397 + }
2398 }
2399
2400 void bcma_core_mips_early_init(struct bcma_drv_mips *mcore)
2401 @@ -361,7 +416,7 @@ void bcma_core_mips_init(struct bcma_drv
2402 break;
2403 default:
2404 list_for_each_entry(core, &bus->cores, list) {
2405 - core->irq = bcma_core_irq(core);
2406 + core->irq = bcma_core_irq(core, 0);
2407 }
2408 bcma_err(bus,
2409 "Unknown device (0x%x) found, can not configure IRQs\n",
2410 --- a/drivers/bcma/host_soc.c
2411 +++ b/drivers/bcma/host_soc.c
2412 @@ -7,6 +7,9 @@
2413
2414 #include "bcma_private.h"
2415 #include "scan.h"
2416 +#include <linux/slab.h>
2417 +#include <linux/module.h>
2418 +#include <linux/of_address.h>
2419 #include <linux/bcma/bcma.h>
2420 #include <linux/bcma/bcma_soc.h>
2421
2422 @@ -134,12 +137,16 @@ static void bcma_host_soc_block_write(st
2423
2424 static u32 bcma_host_soc_aread32(struct bcma_device *core, u16 offset)
2425 {
2426 + if (WARN_ONCE(!core->io_wrap, "Accessed core has no wrapper/agent\n"))
2427 + return ~0;
2428 return readl(core->io_wrap + offset);
2429 }
2430
2431 static void bcma_host_soc_awrite32(struct bcma_device *core, u16 offset,
2432 u32 value)
2433 {
2434 + if (WARN_ONCE(!core->io_wrap, "Accessed core has no wrapper/agent\n"))
2435 + return;
2436 writel(value, core->io_wrap + offset);
2437 }
2438
2439 @@ -161,7 +168,6 @@ static const struct bcma_host_ops bcma_h
2440 int __init bcma_host_soc_register(struct bcma_soc *soc)
2441 {
2442 struct bcma_bus *bus = &soc->bus;
2443 - int err;
2444
2445 /* iomap only first core. We have to read some register on this core
2446 * to scan the bus.
2447 @@ -173,11 +179,100 @@ int __init bcma_host_soc_register(struct
2448 /* Host specific */
2449 bus->hosttype = BCMA_HOSTTYPE_SOC;
2450 bus->ops = &bcma_host_soc_ops;
2451 + bus->host_pdev = NULL;
2452
2453 - /* Register */
2454 + /* Initialize struct, detect chip */
2455 + bcma_init_bus(bus);
2456 +
2457 + return 0;
2458 +}
2459 +
2460 +int __init bcma_host_soc_init(struct bcma_soc *soc)
2461 +{
2462 + struct bcma_bus *bus = &soc->bus;
2463 + int err;
2464 +
2465 + /* Scan bus and initialize it */
2466 err = bcma_bus_early_register(bus, &soc->core_cc, &soc->core_mips);
2467 if (err)
2468 iounmap(bus->mmio);
2469
2470 return err;
2471 }
2472 +
2473 +#ifdef CONFIG_OF
2474 +static int bcma_host_soc_probe(struct platform_device *pdev)
2475 +{
2476 + struct device *dev = &pdev->dev;
2477 + struct device_node *np = dev->of_node;
2478 + struct bcma_bus *bus;
2479 + int err;
2480 +
2481 + /* Alloc */
2482 + bus = devm_kzalloc(dev, sizeof(*bus), GFP_KERNEL);
2483 + if (!bus)
2484 + return -ENOMEM;
2485 +
2486 + /* Map MMIO */
2487 + bus->mmio = of_iomap(np, 0);
2488 + if (!bus->mmio)
2489 + return -ENOMEM;
2490 +
2491 + /* Host specific */
2492 + bus->hosttype = BCMA_HOSTTYPE_SOC;
2493 + bus->ops = &bcma_host_soc_ops;
2494 + bus->host_pdev = pdev;
2495 +
2496 + /* Initialize struct, detect chip */
2497 + bcma_init_bus(bus);
2498 +
2499 + /* Register */
2500 + err = bcma_bus_register(bus);
2501 + if (err)
2502 + goto err_unmap_mmio;
2503 +
2504 + platform_set_drvdata(pdev, bus);
2505 +
2506 + return err;
2507 +
2508 +err_unmap_mmio:
2509 + iounmap(bus->mmio);
2510 + return err;
2511 +}
2512 +
2513 +static int bcma_host_soc_remove(struct platform_device *pdev)
2514 +{
2515 + struct bcma_bus *bus = platform_get_drvdata(pdev);
2516 +
2517 + bcma_bus_unregister(bus);
2518 + iounmap(bus->mmio);
2519 + platform_set_drvdata(pdev, NULL);
2520 +
2521 + return 0;
2522 +}
2523 +
2524 +static const struct of_device_id bcma_host_soc_of_match[] = {
2525 + { .compatible = "brcm,bus-axi", },
2526 + {},
2527 +};
2528 +MODULE_DEVICE_TABLE(of, bcma_host_soc_of_match);
2529 +
2530 +static struct platform_driver bcma_host_soc_driver = {
2531 + .driver = {
2532 + .name = "bcma-host-soc",
2533 + .of_match_table = bcma_host_soc_of_match,
2534 + },
2535 + .probe = bcma_host_soc_probe,
2536 + .remove = bcma_host_soc_remove,
2537 +};
2538 +
2539 +int __init bcma_host_soc_register_driver(void)
2540 +{
2541 + return platform_driver_register(&bcma_host_soc_driver);
2542 +}
2543 +
2544 +void __exit bcma_host_soc_unregister_driver(void)
2545 +{
2546 + platform_driver_unregister(&bcma_host_soc_driver);
2547 +}
2548 +#endif /* CONFIG_OF */
2549 --- a/include/linux/bcma/bcma_regs.h
2550 +++ b/include/linux/bcma/bcma_regs.h
2551 @@ -39,6 +39,11 @@
2552 #define BCMA_RESET_CTL_RESET 0x0001
2553 #define BCMA_RESET_ST 0x0804
2554
2555 +#define BCMA_NS_ROM_IOST_BOOT_DEV_MASK 0x0003
2556 +#define BCMA_NS_ROM_IOST_BOOT_DEV_NOR 0x0000
2557 +#define BCMA_NS_ROM_IOST_BOOT_DEV_NAND 0x0001
2558 +#define BCMA_NS_ROM_IOST_BOOT_DEV_ROM 0x0002
2559 +
2560 /* BCMA PCI config space registers. */
2561 #define BCMA_PCI_PMCSR 0x44
2562 #define BCMA_PCI_PE 0x100
2563 --- a/drivers/usb/host/bcma-hcd.c
2564 +++ b/drivers/usb/host/bcma-hcd.c
2565 @@ -238,7 +238,7 @@ static int bcma_hcd_probe(struct bcma_de
2566 bcma_hcd_init_chip(dev);
2567
2568 /* In AI chips EHCI is addrspace 0, OHCI is 1 */
2569 - ohci_addr = dev->addr1;
2570 + ohci_addr = dev->addr_s[0];
2571 if ((chipinfo->id == 0x5357 || chipinfo->id == 0x4749)
2572 && chipinfo->rev == 0)
2573 ohci_addr = 0x18009000;
2574 --- /dev/null
2575 +++ b/drivers/bcma/driver_chipcommon_b.c
2576 @@ -0,0 +1,61 @@
2577 +/*
2578 + * Broadcom specific AMBA
2579 + * ChipCommon B Unit driver
2580 + *
2581 + * Copyright 2014, Hauke Mehrtens <hauke@hauke-m.de>
2582 + *
2583 + * Licensed under the GNU/GPL. See COPYING for details.
2584 + */
2585 +
2586 +#include "bcma_private.h"
2587 +#include <linux/export.h>
2588 +#include <linux/bcma/bcma.h>
2589 +
2590 +static bool bcma_wait_reg(struct bcma_bus *bus, void __iomem *addr, u32 mask,
2591 + u32 value, int timeout)
2592 +{
2593 + unsigned long deadline = jiffies + timeout;
2594 + u32 val;
2595 +
2596 + do {
2597 + val = readl(addr);
2598 + if ((val & mask) == value)
2599 + return true;
2600 + cpu_relax();
2601 + udelay(10);
2602 + } while (!time_after_eq(jiffies, deadline));
2603 +
2604 + bcma_err(bus, "Timeout waiting for register %p\n", addr);
2605 +
2606 + return false;
2607 +}
2608 +
2609 +void bcma_chipco_b_mii_write(struct bcma_drv_cc_b *ccb, u32 offset, u32 value)
2610 +{
2611 + struct bcma_bus *bus = ccb->core->bus;
2612 +
2613 + writel(offset, ccb->mii + 0x00);
2614 + bcma_wait_reg(bus, ccb->mii + 0x00, 0x0100, 0x0000, 100);
2615 + writel(value, ccb->mii + 0x04);
2616 + bcma_wait_reg(bus, ccb->mii + 0x00, 0x0100, 0x0000, 100);
2617 +}
2618 +EXPORT_SYMBOL_GPL(bcma_chipco_b_mii_write);
2619 +
2620 +int bcma_core_chipcommon_b_init(struct bcma_drv_cc_b *ccb)
2621 +{
2622 + if (ccb->setup_done)
2623 + return 0;
2624 +
2625 + ccb->setup_done = 1;
2626 + ccb->mii = ioremap_nocache(ccb->core->addr_s[1], BCMA_CORE_SIZE);
2627 + if (!ccb->mii)
2628 + return -ENOMEM;
2629 +
2630 + return 0;
2631 +}
2632 +
2633 +void bcma_core_chipcommon_b_free(struct bcma_drv_cc_b *ccb)
2634 +{
2635 + if (ccb->mii)
2636 + iounmap(ccb->mii);
2637 +}
2638 --- a/include/linux/bcma/bcma_soc.h
2639 +++ b/include/linux/bcma/bcma_soc.h
2640 @@ -10,6 +10,7 @@ struct bcma_soc {
2641 };
2642
2643 int __init bcma_host_soc_register(struct bcma_soc *soc);
2644 +int __init bcma_host_soc_init(struct bcma_soc *soc);
2645
2646 int bcma_bus_register(struct bcma_bus *bus);
2647
2648 --- a/arch/mips/bcm47xx/setup.c
2649 +++ b/arch/mips/bcm47xx/setup.c
2650 @@ -194,6 +194,10 @@ static void __init bcm47xx_register_bcma
2651
2652 err = bcma_host_soc_register(&bcm47xx_bus.bcma);
2653 if (err)
2654 + panic("Failed to register BCMA bus (err %d)", err);
2655 +
2656 + err = bcma_host_soc_init(&bcm47xx_bus.bcma);
2657 + if (err)
2658 panic("Failed to initialize BCMA bus (err %d)", err);
2659
2660 bcm47xx_fill_bcma_boardinfo(&bcm47xx_bus.bcma.bus.boardinfo, NULL);
2661 --- /dev/null
2662 +++ b/Documentation/devicetree/bindings/bus/bcma.txt
2663 @@ -0,0 +1,53 @@
2664 +Driver for ARM AXI Bus with Broadcom Plugins (bcma)
2665 +
2666 +Required properties:
2667 +
2668 +- compatible : brcm,bus-axi
2669 +
2670 +- reg : iomem address range of chipcommon core
2671 +
2672 +The cores on the AXI bus are automatically detected by bcma with the
2673 +memory ranges they are using and they get registered afterwards.
2674 +Automatic detection of the IRQ number is not working on
2675 +BCM47xx/BCM53xx ARM SoCs. To assign IRQ numbers to the cores, provide
2676 +them manually through device tree. Use an interrupt-map to specify the
2677 +IRQ used by the devices on the bus. The first address is just an index,
2678 +because we do not have any special register.
2679 +
2680 +The top-level axi bus may contain children representing attached cores
2681 +(devices). This is needed since some hardware details can't be auto
2682 +detected (e.g. IRQ numbers). Also some of the cores may be responsible
2683 +for extra things, e.g. ChipCommon providing access to the GPIO chip.
2684 +
2685 +Example:
2686 +
2687 + axi@18000000 {
2688 + compatible = "brcm,bus-axi";
2689 + reg = <0x18000000 0x1000>;
2690 + ranges = <0x00000000 0x18000000 0x00100000>;
2691 + #address-cells = <1>;
2692 + #size-cells = <1>;
2693 + #interrupt-cells = <1>;
2694 + interrupt-map-mask = <0x000fffff 0xffff>;
2695 + interrupt-map =
2696 + /* Ethernet Controller 0 */
2697 + <0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
2698 +
2699 + /* Ethernet Controller 1 */
2700 + <0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
2701 +
2702 + /* PCIe Controller 0 */
2703 + <0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
2704 + <0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
2705 + <0x00012000 2 &gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
2706 + <0x00012000 3 &gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
2707 + <0x00012000 4 &gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
2708 + <0x00012000 5 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
2709 +
2710 + chipcommon {
2711 + reg = <0x00000000 0x1000>;
2712 +
2713 + gpio-controller;
2714 + #gpio-cells = <2>;
2715 + };
2716 + };
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