target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-cs-w3-wd1200g-eup.dts

   1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
   2
   3 #include "qcom-ipq4019.dtsi"
   4 #include <dt-bindings/gpio/gpio.h>
   5 #include <dt-bindings/input/input.h>
   6 #include <dt-bindings/leds/common.h>
   7 #include <dt-bindings/soc/qcom,tcsr.h>
   8
   9 / {
  10         model = "EZVIZ CS-W3-WD1200G EUP";
  11         compatible = "ezviz,cs-w3-wd1200g-eup";
  12
  13         aliases {
  14                 led-boot = &led_status_green;
  15                 led-failsafe = &led_status_red;
  16                 led-running = &led_status_blue;
  17                 led-upgrade = &led_status_green;
  18         };
  19
  20         soc {
  21                 rng@22000 {
  22                         status = "okay";
  23                 };
  24
  25                 mdio@90000 {
  26                         status = "okay";
  27                         pinctrl-0 = <&mdio_pins>;
  28                         pinctrl-names = "default";
  29                         reset-gpios = <&tlmm 59 GPIO_ACTIVE_LOW>;
  30                         reset-delay-us = <5000>;
  31                 };
  32
  33                 tcsr@1949000 {
  34                         compatible = "qcom,tcsr";
  35                         reg = <0x1949000 0x100>;
  36                         qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
  37                 };
  38
  39                 tcsr@194b000 {
  40                         compatible = "qcom,tcsr";
  41                         reg = <0x194b000 0x100>;
  42                         qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
  43                 };
  44
  45                 ess_tcsr@1953000 {
  46                         compatible = "qcom,tcsr";
  47                         reg = <0x1953000 0x1000>;
  48                         qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
  49                 };
  50
  51                 tcsr@1957000 {
  52                         compatible = "qcom,tcsr";
  53                         reg = <0x1957000 0x100>;
  54                         qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
  55                 };
  56
  57                 crypto@8e3a000 {
  58                         status = "okay";
  59                 };
  60
  61                 watchdog@b017000 {
  62                         status = "okay";
  63                 };
  64         };
  65
  66         leds {
  67                 compatible = "gpio-leds";
  68
  69                 led_status_red: status_red {
  70                         function = LED_FUNCTION_STATUS;
  71                         color = <LED_COLOR_ID_RED>;
  72                         gpios = <&tlmm 0 GPIO_ACTIVE_LOW>;
  73                 };
  74
  75                 led_status_green: status_green {
  76                         function = LED_FUNCTION_STATUS;
  77                         color = <LED_COLOR_ID_GREEN>;
  78                         gpios = <&tlmm 3 GPIO_ACTIVE_LOW>;
  79                 };
  80
  81                 led_status_blue: status_blue {
  82                         function = LED_FUNCTION_STATUS;
  83                         color = <LED_COLOR_ID_BLUE>;
  84                         gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;
  85                 };
  86         };
  87
  88         keys {
  89                 compatible = "gpio-keys";
  90
  91                 reset {
  92                         label = "reset";
  93                         gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
  94                         linux,code = <KEY_RESTART>;
  95                 };
  96         };
  97 };
  98
  99 &tlmm {
 100         serial_pins: serial_pinmux {
 101                 mux {
 102                         pins = "gpio60", "gpio61";
 103                         function = "blsp_uart0";
 104                         bias-disable;
 105                 };
 106         };
 107
 108         mdio_pins: mdio_pinmux {
 109                 mux_1 {
 110                         pins = "gpio53";
 111                         function = "mdio";
 112                         bias-pull-up;
 113                 };
 114
 115                 mux_2 {
 116                         pins = "gpio52";
 117                         function = "mdc";
 118                         bias-pull-up;
 119                 };
 120         };
 121
 122         spi_0_pins: spi_0_pinmux {
 123                 pin {
 124                         function = "blsp_spi0";
 125                         pins = "gpio55", "gpio56", "gpio57";
 126                         drive-strength = <12>;
 127                         bias-disable;
 128                 };
 129                 pin_cs {
 130                         function = "gpio";
 131                         pins = "gpio54";
 132                         drive-strength = <2>;
 133                         bias-disable;
 134                         output-high;
 135                 };
 136         };
 137 };
 138
 139 &blsp_dma {
 140         status = "okay";
 141 };
 142
 143 &blsp1_spi1 {
 144         pinctrl-0 = <&spi_0_pins>;
 145         pinctrl-names = "default";
 146         status = "okay";
 147         cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
 148
 149         flash@0 {
 150                 compatible = "jedec,spi-nor";
 151                 reg = <0>;
 152                 spi-max-frequency = <24000000>;
 153
 154                 partitions {
 155                         compatible = "fixed-partitions";
 156                         #address-cells = <1>;
 157                         #size-cells = <1>;
 158
 159                         partition0@0 {
 160                                 label = "SBL1";
 161                                 reg = <0x00000000 0x00040000>;
 162                                 read-only;
 163                         };
 164
 165                         partition1@40000 {
 166                                 label = "MIBIB";
 167                                 reg = <0x00040000 0x00020000>;
 168                                 read-only;
 169                         };
 170
 171                         partition2@60000 {
 172                                 label = "QSEE";
 173                                 reg = <0x00060000 0x00060000>;
 174                                 read-only;
 175                         };
 176
 177                         partition3@c0000 {
 178                                 label = "CDT";
 179                                 reg = <0x000c0000 0x00010000>;
 180                                 read-only;
 181                         };
 182
 183                         partition4@d0000 {
 184                                 label = "DDRPARAMS";
 185                                 reg = <0x000d0000 0x00010000>;
 186                                 read-only;
 187                         };
 188
 189                         partition5@E0000 {
 190                                 label = "APPSBLENV";
 191                                 reg = <0x000e0000 0x00010000>;
 192                                 read-only;
 193                         };
 194
 195                         partition6@F0000 {
 196                                 label = "APPSBL";
 197                                 reg = <0x000f0000 0x00080000>;
 198                                 read-only;
 199                         };
 200
 201                         partition7@170000 {
 202                                 label = "ART";
 203                                 reg = <0x00170000 0x00010000>;
 204                                 read-only;
 205
 206                                 nvmem-layout {
 207                                         compatible = "fixed-layout";
 208                                         #address-cells = <1>;
 209                                         #size-cells = <1>;
 210
 211                                         macaddr_art_0: macaddr@0 {
 212                                                 reg = <0x0 0x6>;
 213                                         };
 214
 215                                         macaddr_art_6: macaddr@6 {
 216                                                 reg = <0x6 0x6>;
 217                                         };
 218
 219                                         precal_art_1000: precal@1000 {
 220                                                 reg = <0x1000 0x2f20>;
 221                                         };
 222
 223                                         precal_art_5000: precal@5000 {
 224                                                 reg = <0x5000 0x2f20>;
 225                                         };
 226                                 };
 227                         };
 228
 229                         partition9@580000 {
 230                                 compatible = "denx,fit";
 231                                 label = "firmware";
 232                                 reg = <0x00180000 0x00e80000>;
 233                         };
 234                 };
 235         };
 236 };
 237
 238 &blsp1_uart1 {
 239         pinctrl-0 = <&serial_pins>;
 240         pinctrl-names = "default";
 241         status = "okay";
 242 };
 243
 244 &cryptobam {
 245         status = "okay";
 246 };
 247
 248 &gmac {
 249         status = "okay";
 250         nvmem-cells = <&macaddr_art_0>;
 251         nvmem-cell-names = "mac-address";
 252 };
 253
 254 &switch {
 255         status = "okay";
 256 };
 257
 258 &swport2 {
 259         status = "okay";
 260         label = "lan3";
 261 };
 262
 263 &swport3 {
 264         status = "okay";
 265         label = "lan2";
 266 };
 267
 268 &swport4 {
 269         status = "okay";
 270         label = "lan1";
 271 };
 272
 273 &swport5 {
 274         status = "okay";
 275         label = "wan";
 276         nvmem-cells = <&macaddr_art_6>;
 277         nvmem-cell-names = "mac-address";
 278 };
 279
 280 &ethphy0 {
 281         status = "disabled";
 282 };
 283
 284 &wifi0 {
 285         status = "okay";
 286         qcom,ath10k-calibration-variant = "ezviz-cs-w3-wd1200g-eup";
 287         nvmem-cell-names = "pre-calibration";
 288         nvmem-cells = <&precal_art_1000>;
 289 };
 290
 291 &wifi1 {
 292         status = "okay";
 293         qcom,ath10k-calibration-variant = "ezviz-cs-w3-wd1200g-eup";
 294         nvmem-cell-names = "pre-calibration";
 295         nvmem-cells = <&precal_art_5000>;
 296 };