target/linux/ipq40xx/patches-6.1/422-firmware-qcom-scm-fix-SCM-cold-boot-address.patch

   1 From aaa675f07e781e248fcf169ce9a917b48bc2cc9b Mon Sep 17 00:00:00 2001
   2 From: Brian Norris <computersforpeace@gmail.com>
   3 Date: Fri, 28 Jul 2023 12:06:23 +0200
   4 Subject: [PATCH 3/3] firmware: qcom: scm: fix SCM cold boot address
   5
   6 This effectively reverts upstream Linux commit 13e77747800e ("firmware:
   7 qcom: scm: Use atomic SCM for cold boot"), because Google WiFi boot
   8 firmwares don't support the atomic variant.
   9
  10 This fixes SMP support for Google WiFi.
  11
  12 Signed-off-by: Brian Norris <computersforpeace@gmail.com>
  13 ---
  14  drivers/firmware/qcom_scm-legacy.c | 62 +++++++++++++++++++++++++-----
  15  drivers/firmware/qcom_scm.c        | 11 ++++++
  16  2 files changed, 63 insertions(+), 10 deletions(-)
  17
  18 --- a/drivers/firmware/qcom_scm-legacy.c
  19 +++ b/drivers/firmware/qcom_scm-legacy.c
  20 @@ -13,6 +13,9 @@
  21  #include <linux/arm-smccc.h>
  22  #include <linux/dma-mapping.h>
  23
  24 +#include <asm/cacheflush.h>
  25 +#include <asm/outercache.h>
  26 +
  27  #include "qcom_scm.h"
  28
  29  static DEFINE_MUTEX(qcom_scm_lock);
  30 @@ -117,6 +120,25 @@ static void __scm_legacy_do(const struct
  31         } while (res->a0 == QCOM_SCM_INTERRUPTED);
  32  }
  33
  34 +static void qcom_scm_inv_range(unsigned long start, unsigned long end)
  35 +{
  36 +       u32 cacheline_size, ctr;
  37 +
  38 +       asm volatile("mrc p15, 0, %0, c0, c0, 1" : "=r" (ctr));
  39 +       cacheline_size = 4 << ((ctr >> 16) & 0xf);
  40 +
  41 +       start = round_down(start, cacheline_size);
  42 +       end = round_up(end, cacheline_size);
  43 +       outer_inv_range(start, end);
  44 +       while (start < end) {
  45 +               asm ("mcr p15, 0, %0, c7, c6, 1" : : "r" (start)
  46 +                    : "memory");
  47 +               start += cacheline_size;
  48 +       }
  49 +       dsb();
  50 +       isb();
  51 +}
  52 +
  53  /**
  54   * scm_legacy_call() - Sends a command to the SCM and waits for the command to
  55   * finish processing.
  56 @@ -163,10 +185,16 @@ int scm_legacy_call(struct device *dev,
  57
  58         rsp = scm_legacy_command_to_response(cmd);
  59
  60 -       cmd_phys = dma_map_single(dev, cmd, alloc_len, DMA_TO_DEVICE);
  61 -       if (dma_mapping_error(dev, cmd_phys)) {
  62 -               kfree(cmd);
  63 -               return -ENOMEM;
  64 +       if (dev) {
  65 +               cmd_phys = dma_map_single(dev, cmd, alloc_len, DMA_TO_DEVICE);
  66 +               if (dma_mapping_error(dev, cmd_phys)) {
  67 +                       kfree(cmd);
  68 +                       return -ENOMEM;
  69 +               }
  70 +       } else {
  71 +               cmd_phys = virt_to_phys(cmd);
  72 +               __cpuc_flush_dcache_area(cmd, alloc_len);
  73 +               outer_flush_range(cmd_phys, cmd_phys + alloc_len);
  74         }
  75
  76         smc.args[0] = 1;
  77 @@ -182,13 +210,26 @@ int scm_legacy_call(struct device *dev,
  78                 goto out;
  79
  80         do {
  81 -               dma_sync_single_for_cpu(dev, cmd_phys + sizeof(*cmd) + cmd_len,
  82 -                                       sizeof(*rsp), DMA_FROM_DEVICE);
  83 +               if (dev) {
  84 +                       dma_sync_single_for_cpu(dev, cmd_phys + sizeof(*cmd) +
  85 +                                               cmd_len, sizeof(*rsp),
  86 +                                               DMA_FROM_DEVICE);
  87 +               } else {
  88 +                       unsigned long start = (uintptr_t)cmd + sizeof(*cmd) +
  89 +                                             cmd_len;
  90 +                       qcom_scm_inv_range(start, start + sizeof(*rsp));
  91 +               }
  92         } while (!rsp->is_complete);
  93
  94 -       dma_sync_single_for_cpu(dev, cmd_phys + sizeof(*cmd) + cmd_len +
  95 -                               le32_to_cpu(rsp->buf_offset),
  96 -                               resp_len, DMA_FROM_DEVICE);
  97 +       if (dev) {
  98 +               dma_sync_single_for_cpu(dev, cmd_phys + sizeof(*cmd) + cmd_len +
  99 +                                       le32_to_cpu(rsp->buf_offset),
 100 +                                       resp_len, DMA_FROM_DEVICE);
 101 +       } else {
 102 +               unsigned long start = (uintptr_t)cmd + sizeof(*cmd) + cmd_len +
 103 +                                     le32_to_cpu(rsp->buf_offset);
 104 +               qcom_scm_inv_range(start, start + resp_len);
 105 +       }
 106
 107         if (res) {
 108                 res_buf = scm_legacy_get_response_buffer(rsp);
 109 @@ -196,7 +237,8 @@ int scm_legacy_call(struct device *dev,
 110                         res->result[i] = le32_to_cpu(res_buf[i]);
 111         }
 112  out:
 113 -       dma_unmap_single(dev, cmd_phys, alloc_len, DMA_TO_DEVICE);
 114 +       if (dev)
 115 +               dma_unmap_single(dev, cmd_phys, alloc_len, DMA_TO_DEVICE);
 116         kfree(cmd);
 117         return ret;
 118  }
 119 --- a/drivers/firmware/qcom_scm.c
 120 +++ b/drivers/firmware/qcom_scm.c
 121 @@ -312,6 +312,17 @@ static int qcom_scm_set_boot_addr(void *
 122         desc.args[0] = flags;
 123         desc.args[1] = virt_to_phys(entry);
 124
 125 +       /*
 126 +        * Factory firmware doesn't support the atomic variant. Non-atomic SCMs
 127 +        * require ugly DMA invalidation support that was dropped upstream a
 128 +        * while ago. For more info, see:
 129 +        *
 130 +        *  [RFC] qcom_scm: IPQ4019 firmware does not support atomic API?
 131 +        *  https://lore.kernel.org/linux-arm-msm/20200913201608.GA3162100@bDebian/
 132 +        */
 133 +       if (of_machine_is_compatible("google,wifi"))
 134 +               return qcom_scm_call(__scm ? __scm->dev : NULL, &desc, NULL);
 135 +
 136         return qcom_scm_call_atomic(__scm ? __scm->dev : NULL, &desc, NULL);
 137  }
 138