target/linux/ipq806x/files-5.10/arch/arm/boot/dts/qcom-ipq8065-rt4230w-rev6.dts

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2
   3 #include "qcom-ipq8065.dtsi"
   4 #include <dt-bindings/input/input.h>
   5
   6 / {
   7         model = "Askey RT4230W REV6";
   8         compatible = "askey,rt4230w-rev6", "qcom,ipq8065", "qcom,ipq8064";
   9
  10         memory@0 {
  11                 reg = <0x42000000 0x3e000000>;
  12                 device_type = "memory";
  13         };
  14
  15         aliases {
  16                 led-boot = &ledctrl3;
  17                 led-failsafe = &ledctrl1;
  18                 led-running = &ledctrl2;
  19                 led-upgrade = &ledctrl3;
  20         };
  21
  22         chosen {
  23                 bootargs = "rootfstype=squashfs noinitrd";
  24         };
  25
  26         keys {
  27                 compatible = "gpio-keys";
  28                 pinctrl-0 = <&button_pins>;
  29                 pinctrl-names = "default";
  30
  31                 reset {
  32                         label = "reset";
  33                         gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
  34                         linux,code = <KEY_RESTART>;
  35                 };
  36
  37                 wps {
  38                         label = "wps";
  39                         gpios = <&qcom_pinmux 68 GPIO_ACTIVE_LOW>;
  40                         linux,code = <KEY_WPS_BUTTON>;
  41                 };
  42         };
  43
  44         leds {
  45                 compatible = "gpio-leds";
  46                 pinctrl-0 = <&led_pins>;
  47                 pinctrl-names = "default";
  48
  49                 ledctrl1: ledctrl1 {
  50                         label = "ledctrl1";
  51                         gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>;
  52                 };
  53
  54                 ledctrl2: ledctrl2 {
  55                         label = "ledctrl2";
  56                         gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>;
  57                 };
  58
  59                 ledctrl3: ledctrl3 {
  60                         label = "ledctrl3";
  61                         gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>;
  62                 };
  63         };
  64 };
  65
  66 &qcom_pinmux {
  67         button_pins: button_pins {
  68                 mux {
  69                         pins = "gpio54", "gpio68";
  70                         function = "gpio";
  71                         drive-strength = <2>;
  72                         bias-pull-up;
  73                 };
  74         };
  75
  76         led_pins: led_pins {
  77                 mux {
  78                         pins = "gpio22", "gpio23", "gpio24";
  79                         function = "gpio";
  80                         drive-strength = <2>;
  81                         bias-pull-down;
  82                 };
  83         };
  84
  85         rgmii2_pins: rgmii2_pins {
  86                 mux {
  87                         pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31",
  88                                 "gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62";
  89                         function = "rgmii2";
  90                         drive-strength = <8>;
  91                         bias-disable;
  92                 };
  93
  94                 tx {
  95                         pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32";
  96                         input-disable;
  97                 };
  98         };
  99
 100         spi_pins: spi_pins {
 101                 cs {
 102                         pins = "gpio20";
 103                         drive-strength = <12>;
 104                 };
 105         };
 106 };
 107
 108 &gsbi5 {
 109         qcom,mode = <GSBI_PROT_SPI>;
 110         status = "okay";
 111
 112         spi@1a280000 {
 113                 status = "okay";
 114
 115                 pinctrl-0 = <&spi_pins>;
 116                 pinctrl-names = "default";
 117
 118                 cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>;
 119
 120                 flash@0 {
 121                         compatible = "everspin,mr25h256";
 122                         #address-cells = <1>;
 123                         #size-cells = <1>;
 124                         spi-max-frequency = <40000000>;
 125                         reg = <0>;
 126                 };
 127         };
 128 };
 129
 130 &nand {
 131         status = "okay";
 132
 133         pinctrl-0 = <&nand_pins>;
 134         pinctrl-names = "default";
 135
 136         nand@0 {
 137                 reg = <0>;
 138                 compatible = "qcom,nandcs";
 139
 140                 nand-ecc-strength = <4>;
 141                 nand-bus-width = <8>;
 142                 nand-ecc-step-size = <512>;
 143
 144                 partitions {
 145                         compatible = "fixed-partitions";
 146                         #address-cells = <1>;
 147                         #size-cells = <1>;
 148
 149                         partition@0 {
 150                                 label = "0:SBL1";
 151                                 reg = <0x0000000 0x0040000>;
 152                                 read-only;
 153                         };
 154
 155                         partition@40000 {
 156                                 label = "0:MIBIB";
 157                                 reg = <0x0040000 0x0140000>;
 158                                 read-only;
 159                         };
 160
 161                         partition@180000 {
 162                                 label = "0:SBL2";
 163                                 reg = <0x0180000 0x0140000>;
 164                                 read-only;
 165                         };
 166
 167                         partition@2c0000 {
 168                                 label = "0:SBL3";
 169                                 reg = <0x02c0000 0x0280000>;
 170                                 read-only;
 171                         };
 172
 173                         partition@540000 {
 174                                 label = "0:DDRCONFIG";
 175                                 reg = <0x0540000 0x0120000>;
 176                                 read-only;
 177                         };
 178
 179                         partition@660000 {
 180                                 label = "0:SSD";
 181                                 reg = <0x0660000 0x0120000>;
 182                                 read-only;
 183                         };
 184
 185                         partition@780000 {
 186                                 label = "0:TZ";
 187                                 reg = <0x0780000 0x0280000>;
 188                                 read-only;
 189                         };
 190
 191                         partition@a00000 {
 192                                 label = "0:RPM";
 193                                 reg = <0x0a00000 0x0280000>;
 194                                 read-only;
 195                         };
 196
 197                         partition@c80000 {
 198                                 label = "0:APPSBL";
 199                                 reg = <0x0c80000 0x0500000>;
 200                                 read-only;
 201                         };
 202
 203                         partition@1180000 {
 204                                 label = "0:APPSBLENV";
 205                                 reg = <0x1180000 0x0080000>;
 206                         };
 207
 208                         partition@1200000 {
 209                                 label = "0:ART";
 210                                 reg = <0x1200000 0x0140000>;
 211                                 read-only;
 212                                 compatible = "nvmem-cells";
 213                                 #address-cells = <1>;
 214                                 #size-cells = <1>;
 215
 216                                 macaddr_ART_0: macaddr@0 {
 217                                         reg = <0x0 0x6>;
 218                                 };
 219
 220                                 macaddr_ART_6: macaddr@6 {
 221                                         reg = <0x6 0x6>;
 222                                 };
 223
 224                                 precal_ART_1000: precal@1000 {
 225                                         reg = <0x1000 0x2f20>;
 226                                 };
 227
 228                                 precal_ART_5000: precal@5000 {
 229                                         reg = <0x5000 0x2f20>;
 230                                 };
 231                         };
 232
 233                         partition@1340000 {
 234                                 label = "0:BOOTCONFIG";
 235                                 reg = <0x1340000 0x0060000>;
 236                                 read-only;
 237                         };
 238
 239                         partition@13a0000 {
 240                                 label = "0:SBL2_1";
 241                                 reg = <0x13a0000 0x0140000>;
 242                                 read-only;
 243                         };
 244
 245                         partition@14e0000 {
 246                                 label = "0:SBL3_1";
 247                                 reg = <0x14e0000 0x0280000>;
 248                                 read-only;
 249                         };
 250
 251                         partition@1760000 {
 252                                 label = "0:DDRCONFIG_1";
 253                                 reg = <0x1760000 0x0120000>;
 254                                 read-only;
 255                         };
 256
 257                         partition@1880000 {
 258                                 label = "0:SSD_1";
 259                                 reg = <0x1880000 0x0120000>;
 260                                 read-only;
 261                         };
 262
 263                         partition@19a0000 {
 264                                 label = "0:TZ_1";
 265                                 reg = <0x19a0000 0x0280000>;
 266                                 read-only;
 267                         };
 268
 269                         partition@1c20000 {
 270                                 label = "0:RPM_1";
 271                                 reg = <0x1c20000 0x0280000>;
 272                                 read-only;
 273                         };
 274
 275                         partition@1ea0000 {
 276                                 label = "0:BOOTCONFIG1";
 277                                 reg = <0x1ea0000 0x0060000>;
 278                                 read-only;
 279                         };
 280
 281                         partition@1f00000 {
 282                                 label = "0:APPSBL_1";
 283                                 reg = <0x1f00000 0x0500000>;
 284                                 read-only;
 285                         };
 286
 287                         partition@2400000 {
 288                                 label = "ubi";
 289                                 reg = <0x2400000 0x1a000000>;
 290                         };
 291                 };
 292         };
 293 };
 294
 295 &mdio0 {
 296         status = "okay";
 297
 298         pinctrl-0 = <&mdio0_pins>;
 299         pinctrl-names = "default";
 300
 301         phy0: ethernet-phy@0 {
 302                 reg = <0x0>;
 303                 qca,ar8327-initvals = <
 304                         0x00004 0x7600000   /* PAD0_MODE */
 305                         0x00008 0x1000000   /* PAD5_MODE */
 306                         0x0000c 0x80        /* PAD6_MODE */
 307                         0x000e4 0xaa545     /* MAC_POWER_SEL */
 308                         0x000e0 0xc74164de  /* SGMII_CTRL */
 309                         0x0007c 0x4e        /* PORT0_STATUS */
 310                         0x00094 0x4e        /* PORT6_STATUS */
 311                         0x00050 0xcf02cf02  /* LED_CTRL_0 */
 312                         0x00054 0xc832c832  /* LED_CTRL_1 */
 313                         >;
 314         };
 315 };
 316
 317 &gmac0 {
 318         status = "okay";
 319         phy-mode = "rgmii";
 320         qcom,id = <0>;
 321
 322         nvmem-cells = <&macaddr_ART_0>;
 323         nvmem-cell-names = "mac-address";
 324
 325         pinctrl-0 = <&rgmii2_pins>;
 326         pinctrl-names = "default";
 327
 328         fixed-link {
 329                 speed = <1000>;
 330                 full-duplex;
 331         };
 332 };
 333
 334 &gmac1 {
 335         status = "okay";
 336         phy-mode = "sgmii";
 337         qcom,id = <1>;
 338
 339         nvmem-cells = <&macaddr_ART_6>;
 340         nvmem-cell-names = "mac-address";
 341
 342         fixed-link {
 343                 speed = <1000>;
 344                 full-duplex;
 345         };
 346 };
 347
 348 &adm_dma {
 349         status = "okay";
 350 };
 351
 352 &usb3_0 {
 353         status = "okay";
 354 };
 355
 356 &usb3_1 {
 357         status = "okay";
 358 };
 359
 360 &pcie0 {
 361         status = "okay";
 362         reset-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_HIGH>;
 363         pinctrl-0 = <&pcie0_pins>;
 364         pinctrl-names = "default";
 365
 366         bridge@0,0 {
 367                 reg = <0x00000000 0 0 0 0>;
 368                 #address-cells = <3>;
 369                 #size-cells = <2>;
 370                 ranges;
 371
 372                 wifi0: wifi@1,0 {
 373                         compatible = "pci168c,0046";
 374                         reg = <0x00010000 0 0 0 0>;
 375
 376                         nvmem-cells = <&precal_ART_1000>;
 377                         nvmem-cell-names = "pre-calibration";
 378                 };
 379         };
 380 };
 381
 382 &pcie1 {
 383         status = "okay";
 384         reset-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_HIGH>;
 385         pinctrl-0 = <&pcie1_pins>;
 386         pinctrl-names = "default";
 387         max-link-speed = <1>;
 388
 389         bridge@0,0 {
 390                 reg = <0x00000000 0 0 0 0>;
 391                 #address-cells = <3>;
 392                 #size-cells = <2>;
 393                 ranges;
 394
 395                 wifi1: wifi@1,0 {
 396                         compatible = "pci168c,0046";
 397                         reg = <0x00010000 0 0 0 0>;
 398
 399                         nvmem-cells = <&precal_ART_5000>;
 400                         nvmem-cell-names = "pre-calibration";
 401                 };
 402         };
 403 };