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ipq806x: move mdio node to ipq8064 dts
[openwrt/openwrt.git] / target / linux / ipq806x / files-5.4 / arch / arm / boot / dts / qcom-ipq8064.dtsi
1 /dts-v1/;
2
3 #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
4 #include <dt-bindings/mfd/qcom-rpm.h>
5 #include <dt-bindings/clock/qcom,rpmcc.h>
6 #include <dt-bindings/clock/qcom,lcc-ipq806x.h>
7 #include <dt-bindings/soc/qcom,gsbi.h>
8 #include <dt-bindings/reset/qcom,gcc-ipq806x.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/gpio/gpio.h>
11
12 / {
13 model = "Qualcomm IPQ8064";
14 compatible = "qcom,ipq8064";
15 interrupt-parent = <&intc>;
16
17 #address-cells = <1>;
18 #size-cells = <1>;
19 memory { device_type = "memory"; reg = <0 0>; };
20
21 cpus {
22 #address-cells = <1>;
23 #size-cells = <0>;
24
25 cpu0: cpu@0 {
26 compatible = "qcom,krait";
27 enable-method = "qcom,kpss-acc-v1";
28 device_type = "cpu";
29 reg = <0>;
30 next-level-cache = <&L2>;
31 qcom,acc = <&acpu0_aux>;
32 qcom,saw = <&saw0>;
33 clocks = <&kraitcc 0>, <&kraitcc 4>;
34 clock-names = "cpu", "l2";
35 clock-latency = <100000>;
36 cpu-supply = <&smb208_s2a>;
37 operating-points-v2 = <&opp_table0>;
38 voltage-tolerance = <5>;
39 cooling-min-state = <0>;
40 cooling-max-state = <10>;
41 #cooling-cells = <2>;
42 cpu-idle-states = <&CPU_SPC>;
43 };
44
45 cpu1: cpu@1 {
46 compatible = "qcom,krait";
47 enable-method = "qcom,kpss-acc-v1";
48 device_type = "cpu";
49 reg = <1>;
50 next-level-cache = <&L2>;
51 qcom,acc = <&acpu1_aux>;
52 qcom,saw = <&saw1>;
53 clocks = <&kraitcc 1>, <&kraitcc 4>;
54 clock-names = "cpu", "l2";
55 clock-latency = <100000>;
56 cpu-supply = <&smb208_s2b>;
57 operating-points-v2 = <&opp_table0>;
58 voltage-tolerance = <5>;
59 cooling-min-state = <0>;
60 cooling-max-state = <10>;
61 #cooling-cells = <2>;
62 cpu-idle-states = <&CPU_SPC>;
63 };
64
65 L2: l2-cache {
66 compatible = "cache";
67 cache-level = <2>;
68 qcom,saw = <&saw_l2>;
69 };
70
71 qcom,l2 {
72 qcom,l2-rates = <384000000 1000000000 1200000000>;
73 qcom,l2-cpufreq = <384000000 600000000 1200000000>;
74 qcom,l2-volt = <1100000 1100000 1150000>;
75 qcom,l2-supply = <&smb208_s1a>;
76 };
77
78 idle-states {
79 CPU_SPC: spc {
80 compatible = "qcom,idle-state-spc",
81 "arm,idle-state";
82 status = "okay";
83 entry-latency-us = <400>;
84 exit-latency-us = <900>;
85 min-residency-us = <3000>;
86 };
87 };
88 };
89
90 opp_table0: opp_table0 {
91 compatible = "operating-points-v2-qcom-cpu";
92 nvmem-cells = <&speedbin_efuse>;
93
94 opp-384000000 {
95 opp-hz = /bits/ 64 <384000000>;
96 opp-microvolt-speed0-pvs0-v0 = <1000000>;
97 opp-microvolt-speed0-pvs1-v0 = <925000>;
98 opp-microvolt-speed0-pvs2-v0 = <875000>;
99 opp-microvolt-speed0-pvs3-v0 = <800000>;
100 opp-supported-hw = <0x1>;
101 clock-latency-ns = <100000>;
102 };
103
104 opp-600000000 {
105 opp-hz = /bits/ 64 <600000000>;
106 opp-microvolt-speed0-pvs0-v0 = <1050000>;
107 opp-microvolt-speed0-pvs1-v0 = <975000>;
108 opp-microvolt-speed0-pvs2-v0 = <925000>;
109 opp-microvolt-speed0-pvs3-v0 = <850000>;
110 opp-supported-hw = <0x1>;
111 clock-latency-ns = <100000>;
112 };
113
114 opp-800000000 {
115 opp-hz = /bits/ 64 <800000000>;
116 opp-microvolt-speed0-pvs0-v0 = <1100000>;
117 opp-microvolt-speed0-pvs1-v0 = <1025000>;
118 opp-microvolt-speed0-pvs2-v0 = <995000>;
119 opp-microvolt-speed0-pvs3-v0 = <900000>;
120 opp-supported-hw = <0x1>;
121 clock-latency-ns = <100000>;
122 };
123
124 opp-1000000000 {
125 opp-hz = /bits/ 64 <1000000000>;
126 opp-microvolt-speed0-pvs0-v0 = <1150000>;
127 opp-microvolt-speed0-pvs1-v0 = <1075000>;
128 opp-microvolt-speed0-pvs2-v0 = <1025000>;
129 opp-microvolt-speed0-pvs3-v0 = <950000>;
130 opp-supported-hw = <0x1>;
131 clock-latency-ns = <100000>;
132 };
133
134 opp-1200000000 {
135 opp-hz = /bits/ 64 <1200000000>;
136 opp-microvolt-speed0-pvs0-v0 = <1200000>;
137 opp-microvolt-speed0-pvs1-v0 = <1125000>;
138 opp-microvolt-speed0-pvs2-v0 = <1075000>;
139 opp-microvolt-speed0-pvs3-v0 = <1000000>;
140 opp-supported-hw = <0x1>;
141 clock-latency-ns = <100000>;
142 };
143
144 opp-1400000000 {
145 opp-hz = /bits/ 64 <1400000000>;
146 opp-microvolt-speed0-pvs0-v0 = <1250000>;
147 opp-microvolt-speed0-pvs1-v0 = <1175000>;
148 opp-microvolt-speed0-pvs2-v0 = <1125000>;
149 opp-microvolt-speed0-pvs3-v0 = <1050000>;
150 opp-supported-hw = <0x1>;
151 clock-latency-ns = <100000>;
152 };
153
154 };
155
156 thermal-zones {
157 tsens_tz_sensor0 {
158 polling-delay-passive = <0>;
159 polling-delay = <0>;
160 thermal-sensors = <&tsens 0>;
161
162 trips {
163 cpu-critical-hi {
164 temperature = <125000>;
165 hysteresis = <2000>;
166 type = "critical_high";
167 };
168
169 cpu-config-hi {
170 temperature = <105000>;
171 hysteresis = <2000>;
172 type = "configurable_hi";
173 };
174
175 cpu-config-lo {
176 temperature = <95000>;
177 hysteresis = <2000>;
178 type = "configurable_lo";
179 };
180
181 cpu-critical-low {
182 temperature = <0>;
183 hysteresis = <2000>;
184 type = "critical_low";
185 };
186 };
187 };
188
189 tsens_tz_sensor1 {
190 polling-delay-passive = <0>;
191 polling-delay = <0>;
192 thermal-sensors = <&tsens 1>;
193
194 trips {
195 cpu-critical-hi {
196 temperature = <125000>;
197 hysteresis = <2000>;
198 type = "critical_high";
199 };
200
201 cpu-config-hi {
202 temperature = <105000>;
203 hysteresis = <2000>;
204 type = "configurable_hi";
205 };
206
207 cpu-config-lo {
208 temperature = <95000>;
209 hysteresis = <2000>;
210 type = "configurable_lo";
211 };
212
213 cpu-critical-low {
214 temperature = <0>;
215 hysteresis = <2000>;
216 type = "critical_low";
217 };
218 };
219 };
220
221 tsens_tz_sensor2 {
222 polling-delay-passive = <0>;
223 polling-delay = <0>;
224 thermal-sensors = <&tsens 2>;
225
226 trips {
227 cpu-critical-hi {
228 temperature = <125000>;
229 hysteresis = <2000>;
230 type = "critical_high";
231 };
232
233 cpu-config-hi {
234 temperature = <105000>;
235 hysteresis = <2000>;
236 type = "configurable_hi";
237 };
238
239 cpu-config-lo {
240 temperature = <95000>;
241 hysteresis = <2000>;
242 type = "configurable_lo";
243 };
244
245 cpu-critical-low {
246 temperature = <0>;
247 hysteresis = <2000>;
248 type = "critical_low";
249 };
250 };
251 };
252
253 tsens_tz_sensor3 {
254 polling-delay-passive = <0>;
255 polling-delay = <0>;
256 thermal-sensors = <&tsens 3>;
257
258 trips {
259 cpu-critical-hi {
260 temperature = <125000>;
261 hysteresis = <2000>;
262 type = "critical_high";
263 };
264
265 cpu-config-hi {
266 temperature = <105000>;
267 hysteresis = <2000>;
268 type = "configurable_hi";
269 };
270
271 cpu-config-lo {
272 temperature = <95000>;
273 hysteresis = <2000>;
274 type = "configurable_lo";
275 };
276
277 cpu-critical-low {
278 temperature = <0>;
279 hysteresis = <2000>;
280 type = "critical_low";
281 };
282 };
283 };
284
285 tsens_tz_sensor4 {
286 polling-delay-passive = <0>;
287 polling-delay = <0>;
288 thermal-sensors = <&tsens 4>;
289
290 trips {
291 cpu-critical-hi {
292 temperature = <125000>;
293 hysteresis = <2000>;
294 type = "critical_high";
295 };
296
297 cpu-config-hi {
298 temperature = <105000>;
299 hysteresis = <2000>;
300 type = "configurable_hi";
301 };
302
303 cpu-config-lo {
304 temperature = <95000>;
305 hysteresis = <2000>;
306 type = "configurable_lo";
307 };
308
309 cpu-critical-low {
310 temperature = <0>;
311 hysteresis = <2000>;
312 type = "critical_low";
313 };
314 };
315 };
316
317 tsens_tz_sensor5 {
318 polling-delay-passive = <0>;
319 polling-delay = <0>;
320 thermal-sensors = <&tsens 5>;
321
322 trips {
323 cpu-critical-hi {
324 temperature = <125000>;
325 hysteresis = <2000>;
326 type = "critical_high";
327 };
328
329 cpu-config-hi {
330 temperature = <105000>;
331 hysteresis = <2000>;
332 type = "configurable_hi";
333 };
334
335 cpu-config-lo {
336 temperature = <95000>;
337 hysteresis = <2000>;
338 type = "configurable_lo";
339 };
340
341 cpu-critical-low {
342 temperature = <0>;
343 hysteresis = <2000>;
344 type = "critical_low";
345 };
346 };
347 };
348
349 tsens_tz_sensor6 {
350 polling-delay-passive = <0>;
351 polling-delay = <0>;
352 thermal-sensors = <&tsens 6>;
353
354 trips {
355 cpu-critical-hi {
356 temperature = <125000>;
357 hysteresis = <2000>;
358 type = "critical_high";
359 };
360
361 cpu-config-hi {
362 temperature = <105000>;
363 hysteresis = <2000>;
364 type = "configurable_hi";
365 };
366
367 cpu-config-lo {
368 temperature = <95000>;
369 hysteresis = <2000>;
370 type = "configurable_lo";
371 };
372
373 cpu-critical-low {
374 temperature = <0>;
375 hysteresis = <2000>;
376 type = "critical_low";
377 };
378 };
379 };
380
381 tsens_tz_sensor7 {
382 polling-delay-passive = <0>;
383 polling-delay = <0>;
384 thermal-sensors = <&tsens 7>;
385
386 trips {
387 cpu-critical-hi {
388 temperature = <125000>;
389 hysteresis = <2000>;
390 type = "critical_high";
391 };
392
393 cpu-config-hi {
394 temperature = <105000>;
395 hysteresis = <2000>;
396 type = "configurable_hi";
397 };
398
399 cpu-config-lo {
400 temperature = <95000>;
401 hysteresis = <2000>;
402 type = "configurable_lo";
403 };
404
405 cpu-critical-low {
406 temperature = <0>;
407 hysteresis = <2000>;
408 type = "critical_low";
409 };
410 };
411 };
412
413 tsens_tz_sensor8 {
414 polling-delay-passive = <0>;
415 polling-delay = <0>;
416 thermal-sensors = <&tsens 8>;
417
418 trips {
419 cpu-critical-hi {
420 temperature = <125000>;
421 hysteresis = <2000>;
422 type = "critical_high";
423 };
424
425 cpu-config-hi {
426 temperature = <105000>;
427 hysteresis = <2000>;
428 type = "configurable_hi";
429 };
430
431 cpu-config-lo {
432 temperature = <95000>;
433 hysteresis = <2000>;
434 type = "configurable_lo";
435 };
436
437 cpu-critical-low {
438 temperature = <0>;
439 hysteresis = <2000>;
440 type = "critical_low";
441 };
442 };
443 };
444
445 tsens_tz_sensor9 {
446 polling-delay-passive = <0>;
447 polling-delay = <0>;
448 thermal-sensors = <&tsens 9>;
449
450 trips {
451 cpu-critical-hi {
452 temperature = <125000>;
453 hysteresis = <2000>;
454 type = "critical_high";
455 };
456
457 cpu-config-hi {
458 temperature = <105000>;
459 hysteresis = <2000>;
460 type = "configurable_hi";
461 };
462
463 cpu-config-lo {
464 temperature = <95000>;
465 hysteresis = <2000>;
466 type = "configurable_lo";
467 };
468
469 cpu-critical-low {
470 temperature = <0>;
471 hysteresis = <2000>;
472 type = "critical_low";
473 };
474 };
475 };
476
477 tsens_tz_sensor10 {
478 polling-delay-passive = <0>;
479 polling-delay = <0>;
480 thermal-sensors = <&tsens 10>;
481
482 trips {
483 cpu-critical-hi {
484 temperature = <125000>;
485 hysteresis = <2000>;
486 type = "critical_high";
487 };
488
489 cpu-config-hi {
490 temperature = <105000>;
491 hysteresis = <2000>;
492 type = "configurable_hi";
493 };
494
495 cpu-config-lo {
496 temperature = <95000>;
497 hysteresis = <2000>;
498 type = "configurable_lo";
499 };
500
501 cpu-critical-low {
502 temperature = <0>;
503 hysteresis = <2000>;
504 type = "critical_low";
505 };
506 };
507 };
508 };
509
510 cpu-pmu {
511 compatible = "qcom,krait-pmu";
512 interrupts = <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
513 IRQ_TYPE_LEVEL_HIGH)>;
514 };
515
516 reserved-memory {
517 #address-cells = <1>;
518 #size-cells = <1>;
519 ranges;
520
521 nss@40000000 {
522 reg = <0x40000000 0x1000000>;
523 no-map;
524 };
525
526 smem: smem@41000000 {
527 reg = <0x41000000 0x200000>;
528 no-map;
529 };
530 };
531
532 clocks {
533 cxo_board {
534 compatible = "fixed-clock";
535 #clock-cells = <0>;
536 clock-frequency = <25000000>;
537 };
538
539 pxo_board {
540 compatible = "fixed-clock";
541 #clock-cells = <0>;
542 clock-frequency = <25000000>;
543 };
544
545 sleep_clk: sleep_clk {
546 compatible = "fixed-clock";
547 clock-frequency = <32768>;
548 #clock-cells = <0>;
549 };
550 };
551
552 fab-scaling {
553 compatible = "qcom,fab-scaling";
554 clocks = <&rpmcc RPM_APPS_FABRIC_A_CLK>, <&rpmcc RPM_EBI1_A_CLK>;
555 clock-names = "apps-fab-clk", "ddr-fab-clk";
556 fab_freq_high = <533000000>;
557 fab_freq_nominal = <400000000>;
558 cpu_freq_threshold = <1000000000>;
559 };
560
561 firmware {
562 scm {
563 compatible = "qcom,scm-ipq806x";
564 };
565 };
566
567 soc: soc {
568 #address-cells = <1>;
569 #size-cells = <1>;
570 ranges;
571 compatible = "simple-bus";
572
573 lpass@28100000 {
574 compatible = "qcom,lpass-cpu";
575 status = "disabled";
576 clocks = <&lcc AHBIX_CLK>,
577 <&lcc MI2S_OSR_CLK>,
578 <&lcc MI2S_BIT_CLK>;
579 clock-names = "ahbix-clk",
580 "mi2s-osr-clk",
581 "mi2s-bit-clk";
582 interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>;
583 interrupt-names = "lpass-irq-lpaif";
584 reg = <0x28100000 0x10000>;
585 reg-names = "lpass-lpaif";
586 };
587
588 qfprom: qfprom@700000 {
589 compatible = "qcom,qfprom", "syscon";
590 reg = <0x700000 0x1000>;
591 #address-cells = <1>;
592 #size-cells = <1>;
593 status = "okay";
594 tsens_calib: calib@400 {
595 reg = <0x400 0xb>;
596 };
597 tsens_backup: backup@410 {
598 reg = <0x410 0xb>;
599 };
600 speedbin_efuse: speedbin@0c0 {
601 reg = <0x0c0 0x4>;
602 };
603 };
604
605 rpm: rpm@108000 {
606 compatible = "qcom,rpm-ipq8064";
607 reg = <0x108000 0x1000>;
608 qcom,ipc = <&l2cc 0x8 2>;
609
610 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
611 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
612 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
613 interrupt-names = "ack",
614 "err",
615 "wakeup";
616
617 clocks = <&gcc RPM_MSG_RAM_H_CLK>;
618 clock-names = "ram";
619
620 #address-cells = <1>;
621 #size-cells = <0>;
622
623 rpmcc: clock-controller {
624 compatible = "qcom,rpmcc-ipq806x", "qcom,rpmcc";
625 #clock-cells = <1>;
626 };
627
628 regulators {
629 compatible = "qcom,rpm-smb208-regulators";
630
631 smb208_s1a: s1a {
632 regulator-min-microvolt = <1050000>;
633 regulator-max-microvolt = <1150000>;
634
635 qcom,switch-mode-frequency = <1200000>;
636
637 };
638
639 smb208_s1b: s1b {
640 regulator-min-microvolt = <1050000>;
641 regulator-max-microvolt = <1150000>;
642
643 qcom,switch-mode-frequency = <1200000>;
644 };
645
646 smb208_s2a: s2a {
647 regulator-min-microvolt = < 800000>;
648 regulator-max-microvolt = <1250000>;
649
650 qcom,switch-mode-frequency = <1200000>;
651 };
652
653 smb208_s2b: s2b {
654 regulator-min-microvolt = < 800000>;
655 regulator-max-microvolt = <1250000>;
656
657 qcom,switch-mode-frequency = <1200000>;
658 };
659 };
660 };
661
662 rng@1a500000 {
663 compatible = "qcom,prng";
664 reg = <0x1a500000 0x200>;
665 clocks = <&gcc PRNG_CLK>;
666 clock-names = "core";
667 };
668
669 qcom_pinmux: pinmux@800000 {
670 compatible = "qcom,ipq8064-pinctrl";
671 reg = <0x800000 0x4000>;
672
673 gpio-controller;
674 #gpio-cells = <2>;
675 interrupt-controller;
676 #interrupt-cells = <2>;
677 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
678
679 pcie0_pins: pcie0_pinmux {
680 mux {
681 pins = "gpio3";
682 function = "pcie1_rst";
683 drive-strength = <12>;
684 bias-disable;
685 };
686 };
687
688 pcie1_pins: pcie1_pinmux {
689 mux {
690 pins = "gpio48";
691 function = "pcie2_rst";
692 drive-strength = <12>;
693 bias-disable;
694 };
695 };
696
697 pcie2_pins: pcie2_pinmux {
698 mux {
699 pins = "gpio63";
700 function = "pcie3_rst";
701 drive-strength = <12>;
702 bias-disable;
703 output-low;
704 };
705 };
706
707 spi_pins: spi_pins {
708 mux {
709 pins = "gpio18", "gpio19", "gpio21";
710 function = "gsbi5";
711 drive-strength = <10>;
712 bias-none;
713 };
714 };
715
716 leds_pins: leds_pins {
717 mux {
718 pins = "gpio7", "gpio8", "gpio9",
719 "gpio26", "gpio53";
720 function = "gpio";
721 drive-strength = <2>;
722 bias-pull-down;
723 output-low;
724 };
725 };
726
727 buttons_pins: buttons_pins {
728 mux {
729 pins = "gpio54";
730 drive-strength = <2>;
731 bias-pull-up;
732 };
733 };
734 };
735
736 intc: interrupt-controller@2000000 {
737 compatible = "qcom,msm-qgic2";
738 interrupt-controller;
739 #interrupt-cells = <3>;
740 reg = <0x02000000 0x1000>,
741 <0x02002000 0x1000>;
742 };
743
744 timer@200a000 {
745 compatible = "qcom,kpss-timer", "qcom,msm-timer";
746 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(2) |
747 IRQ_TYPE_EDGE_RISING)>,
748 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(2) |
749 IRQ_TYPE_EDGE_RISING)>,
750 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(2) |
751 IRQ_TYPE_EDGE_RISING)>,
752 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(2) |
753 IRQ_TYPE_EDGE_RISING)>,
754 <GIC_PPI 5 (GIC_CPU_MASK_SIMPLE(2) |
755 IRQ_TYPE_EDGE_RISING)>;
756 reg = <0x0200a000 0x100>;
757 clock-frequency = <25000000>,
758 <32768>;
759 clocks = <&sleep_clk>;
760 clock-names = "sleep";
761 cpu-offset = <0x80000>;
762 };
763
764 acpu0_aux: clock-controller@2088000 {
765 compatible = "qcom,kpss-acc-v1";
766 reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
767 clock-output-names = "acpu0_aux";
768 };
769
770 acpu1_aux: clock-controller@2098000 {
771 compatible = "qcom,kpss-acc-v1";
772 reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
773 clock-output-names = "acpu1_aux";
774 };
775
776 l2cc: clock-controller@2011000 {
777 compatible = "qcom,kpss-gcc", "syscon";
778 reg = <0x2011000 0x1000>;
779 clock-output-names = "acpu_l2_aux";
780 };
781
782 kraitcc: clock-controller {
783 compatible = "qcom,krait-cc-v1";
784 #clock-cells = <1>;
785 };
786
787 saw0: regulator@2089000 {
788 compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon";
789 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
790 regulator;
791 };
792
793 saw1: regulator@2099000 {
794 compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon";
795 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
796 regulator;
797 };
798
799 saw_l2: regulator@02012000 {
800 compatible = "qcom,saw2", "syscon";
801 reg = <0x02012000 0x1000>;
802 regulator;
803 };
804
805 sic_non_secure: sic-non-secure@12100000 {
806 compatible = "syscon";
807 reg = <0x12100000 0x10000>;
808 };
809
810 gsbi2: gsbi@12480000 {
811 compatible = "qcom,gsbi-v1.0.0";
812 cell-index = <2>;
813 reg = <0x12480000 0x100>;
814 clocks = <&gcc GSBI2_H_CLK>;
815 clock-names = "iface";
816 #address-cells = <1>;
817 #size-cells = <1>;
818 ranges;
819 status = "disabled";
820
821 syscon-tcsr = <&tcsr>;
822
823 uart2: serial@12490000 {
824 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
825 reg = <0x12490000 0x1000>,
826 <0x12480000 0x1000>;
827 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
828 clocks = <&gcc GSBI2_UART_CLK>, <&gcc GSBI2_H_CLK>;
829 clock-names = "core", "iface";
830 status = "disabled";
831 };
832
833 i2c@124a0000 {
834 compatible = "qcom,i2c-qup-v1.1.1";
835 reg = <0x124a0000 0x1000>;
836 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
837
838 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
839 clock-names = "core", "iface";
840 status = "disabled";
841
842 #address-cells = <1>;
843 #size-cells = <0>;
844 };
845
846 };
847
848 gsbi4: gsbi@16300000 {
849 compatible = "qcom,gsbi-v1.0.0";
850 cell-index = <4>;
851 reg = <0x16300000 0x100>;
852 clocks = <&gcc GSBI4_H_CLK>;
853 clock-names = "iface";
854 #address-cells = <1>;
855 #size-cells = <1>;
856 ranges;
857 status = "disabled";
858
859 syscon-tcsr = <&tcsr>;
860
861 gsbi4_serial: serial@16340000 {
862 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
863 reg = <0x16340000 0x1000>,
864 <0x16300000 0x1000>;
865 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
866 clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
867 clock-names = "core", "iface";
868 status = "disabled";
869 };
870
871 i2c@16380000 {
872 compatible = "qcom,i2c-qup-v1.1.1";
873 reg = <0x16380000 0x1000>;
874 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
875
876 clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>;
877 clock-names = "core", "iface";
878 status = "disabled";
879
880 #address-cells = <1>;
881 #size-cells = <0>;
882 };
883 };
884
885 gsbi5: gsbi@1a200000 {
886 compatible = "qcom,gsbi-v1.0.0";
887 cell-index = <5>;
888 reg = <0x1a200000 0x100>;
889 clocks = <&gcc GSBI5_H_CLK>;
890 clock-names = "iface";
891 #address-cells = <1>;
892 #size-cells = <1>;
893 ranges;
894 status = "disabled";
895
896 syscon-tcsr = <&tcsr>;
897
898 uart5: serial@1a240000 {
899 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
900 reg = <0x1a240000 0x1000>,
901 <0x1a200000 0x1000>;
902 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
903 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
904 clock-names = "core", "iface";
905 status = "disabled";
906 };
907
908 i2c@1a280000 {
909 compatible = "qcom,i2c-qup-v1.1.1";
910 reg = <0x1a280000 0x1000>;
911 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
912
913 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
914 clock-names = "core", "iface";
915 status = "disabled";
916
917 #address-cells = <1>;
918 #size-cells = <0>;
919 };
920
921 spi@1a280000 {
922 compatible = "qcom,spi-qup-v1.1.1";
923 reg = <0x1a280000 0x1000>;
924 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
925
926 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
927 clock-names = "core", "iface";
928 status = "disabled";
929
930 #address-cells = <1>;
931 #size-cells = <0>;
932 };
933 };
934
935 gsbi7: gsbi@16600000 {
936 status = "disabled";
937 compatible = "qcom,gsbi-v1.0.0";
938 cell-index = <7>;
939 reg = <0x16600000 0x100>;
940 clocks = <&gcc GSBI7_H_CLK>;
941 clock-names = "iface";
942 #address-cells = <1>;
943 #size-cells = <1>;
944 ranges;
945 syscon-tcsr = <&tcsr>;
946
947 gsbi7_serial: serial@16640000 {
948 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
949 reg = <0x16640000 0x1000>,
950 <0x16600000 0x1000>;
951 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
952 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
953 clock-names = "core", "iface";
954 status = "disabled";
955 };
956 };
957
958 sata_phy: sata-phy@1b400000 {
959 compatible = "qcom,ipq806x-sata-phy";
960 reg = <0x1b400000 0x200>;
961
962 clocks = <&gcc SATA_PHY_CFG_CLK>;
963 clock-names = "cfg";
964
965 #phy-cells = <0>;
966 status = "disabled";
967 };
968
969 sata: sata@29000000 {
970 compatible = "qcom,ipq806x-ahci", "generic-ahci";
971 reg = <0x29000000 0x180>;
972
973 ports-implemented = <0x1>;
974
975 interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
976
977 clocks = <&gcc SFAB_SATA_S_H_CLK>,
978 <&gcc SATA_H_CLK>,
979 <&gcc SATA_A_CLK>,
980 <&gcc SATA_RXOOB_CLK>,
981 <&gcc SATA_PMALIVE_CLK>;
982 clock-names = "slave_face", "iface", "core",
983 "rxoob", "pmalive";
984
985 assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>;
986 assigned-clock-rates = <100000000>, <100000000>;
987
988 phys = <&sata_phy>;
989 phy-names = "sata-phy";
990 status = "disabled";
991 };
992
993 qcom,ssbi@500000 {
994 compatible = "qcom,ssbi";
995 reg = <0x00500000 0x1000>;
996 qcom,controller-type = "pmic-arbiter";
997 };
998
999 gcc: clock-controller@900000 {
1000 compatible = "qcom,gcc-ipq8064";
1001 reg = <0x00900000 0x4000>;
1002 #clock-cells = <1>;
1003 #reset-cells = <1>;
1004 #power-domain-cells = <1>;
1005 };
1006
1007 tsens: thermal-sensor@900000 {
1008 compatible = "qcom,ipq8064-tsens";
1009 reg = <0x900000 0x3680>;
1010 nvmem-cells = <&tsens_calib>, <&tsens_backup>;
1011 nvmem-cell-names = "calib", "calib_backup";
1012 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
1013 #thermal-sensor-cells = <1>;
1014 };
1015
1016 tcsr: syscon@1a400000 {
1017 compatible = "qcom,tcsr-ipq8064", "syscon";
1018 reg = <0x1a400000 0x100>;
1019 };
1020
1021 lcc: clock-controller@28000000 {
1022 compatible = "qcom,lcc-ipq8064";
1023 reg = <0x28000000 0x1000>;
1024 #clock-cells = <1>;
1025 #reset-cells = <1>;
1026 };
1027
1028 sfpb_mutex_block: syscon@1200600 {
1029 compatible = "syscon";
1030 reg = <0x01200600 0x100>;
1031 };
1032
1033 hs_phy_0: hs_phy_0 {
1034 compatible = "qcom,dwc3-hs-usb-phy";
1035 regmap = <&usb3_0>;
1036 clocks = <&gcc USB30_0_UTMI_CLK>;
1037 clock-names = "ref";
1038 #phy-cells = <0>;
1039 };
1040
1041 ss_phy_0: ss_phy_0 {
1042 compatible = "qcom,dwc3-ss-usb-phy";
1043 regmap = <&usb3_0>;
1044 clocks = <&gcc USB30_0_MASTER_CLK>;
1045 clock-names = "ref";
1046 #phy-cells = <0>;
1047 };
1048
1049 usb3_0: usb3@110f8800 {
1050 compatible = "qcom,dwc3", "syscon";
1051 #address-cells = <1>;
1052 #size-cells = <1>;
1053 reg = <0x110f8800 0x8000>;
1054 clocks = <&gcc USB30_0_MASTER_CLK>;
1055 clock-names = "core";
1056
1057 ranges;
1058
1059 resets = <&gcc USB30_0_MASTER_RESET>;
1060 reset-names = "master";
1061
1062 status = "disabled";
1063
1064 dwc3_0: dwc3@11000000 {
1065 compatible = "snps,dwc3";
1066 reg = <0x11000000 0xcd00>;
1067 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
1068 phys = <&hs_phy_0>, <&ss_phy_0>;
1069 phy-names = "usb2-phy", "usb3-phy";
1070 dr_mode = "host";
1071 snps,dis_u3_susphy_quirk;
1072 };
1073 };
1074
1075 hs_phy_1: hs_phy_1 {
1076 compatible = "qcom,dwc3-hs-usb-phy";
1077 regmap = <&usb3_1>;
1078 clocks = <&gcc USB30_1_UTMI_CLK>;
1079 clock-names = "ref";
1080 #phy-cells = <0>;
1081 };
1082
1083 ss_phy_1: ss_phy_1 {
1084 compatible = "qcom,dwc3-ss-usb-phy";
1085 regmap = <&usb3_1>;
1086 clocks = <&gcc USB30_1_MASTER_CLK>;
1087 clock-names = "ref";
1088 #phy-cells = <0>;
1089 };
1090
1091 usb3_1: usb3@100f8800 {
1092 compatible = "qcom,dwc3", "syscon";
1093 #address-cells = <1>;
1094 #size-cells = <1>;
1095 reg = <0x100f8800 0x8000>;
1096 clocks = <&gcc USB30_1_MASTER_CLK>;
1097 clock-names = "core";
1098
1099 ranges;
1100
1101 resets = <&gcc USB30_1_MASTER_RESET>;
1102 reset-names = "master";
1103
1104 status = "disabled";
1105
1106 dwc3_1: dwc3@10000000 {
1107 compatible = "snps,dwc3";
1108 reg = <0x10000000 0xcd00>;
1109 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
1110 phys = <&hs_phy_1>, <&ss_phy_1>;
1111 phy-names = "usb2-phy", "usb3-phy";
1112 dr_mode = "host";
1113 snps,dis_u3_susphy_quirk;
1114 };
1115 };
1116
1117 pcie0: pci@1b500000 {
1118 compatible = "qcom,pcie-ipq8064";
1119 reg = <0x1b500000 0x1000
1120 0x1b502000 0x80
1121 0x1b600000 0x100
1122 0x0ff00000 0x100000>;
1123 reg-names = "dbi", "elbi", "parf", "config";
1124 device_type = "pci";
1125 linux,pci-domain = <0>;
1126 bus-range = <0x00 0xff>;
1127 num-lanes = <1>;
1128 #address-cells = <3>;
1129 #size-cells = <2>;
1130
1131 ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00100000 /* downstream I/O */
1132 0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */
1133
1134 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1135 interrupt-names = "msi";
1136 #interrupt-cells = <1>;
1137 interrupt-map-mask = <0 0 0 0x7>;
1138 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1139 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1140 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1141 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1142
1143 clocks = <&gcc PCIE_A_CLK>,
1144 <&gcc PCIE_H_CLK>,
1145 <&gcc PCIE_PHY_CLK>,
1146 <&gcc PCIE_AUX_CLK>,
1147 <&gcc PCIE_ALT_REF_CLK>;
1148 clock-names = "core", "iface", "phy", "aux", "ref";
1149
1150 assigned-clocks = <&gcc PCIE_ALT_REF_CLK>;
1151 assigned-clock-rates = <100000000>;
1152
1153 resets = <&gcc PCIE_ACLK_RESET>,
1154 <&gcc PCIE_HCLK_RESET>,
1155 <&gcc PCIE_POR_RESET>,
1156 <&gcc PCIE_PCI_RESET>,
1157 <&gcc PCIE_PHY_RESET>,
1158 <&gcc PCIE_EXT_RESET>;
1159 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
1160
1161 pinctrl-0 = <&pcie0_pins>;
1162 pinctrl-names = "default";
1163
1164 perst-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
1165
1166 phy-tx0-term-offset = <7>;
1167
1168 status = "disabled";
1169 };
1170
1171 pcie1: pci@1b700000 {
1172 compatible = "qcom,pcie-ipq8064";
1173 reg = <0x1b700000 0x1000
1174 0x1b702000 0x80
1175 0x1b800000 0x100
1176 0x31f00000 0x100000>;
1177 reg-names = "dbi", "elbi", "parf", "config";
1178 device_type = "pci";
1179 linux,pci-domain = <1>;
1180 bus-range = <0x00 0xff>;
1181 num-lanes = <1>;
1182 #address-cells = <3>;
1183 #size-cells = <2>;
1184
1185 ranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00100000 /* downstream I/O */
1186 0x82000000 0 0x2e000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */
1187
1188 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
1189 interrupt-names = "msi";
1190 #interrupt-cells = <1>;
1191 interrupt-map-mask = <0 0 0 0x7>;
1192 interrupt-map = <0 0 0 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1193 <0 0 0 2 &intc 0 59 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1194 <0 0 0 3 &intc 0 60 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1195 <0 0 0 4 &intc 0 61 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1196
1197 clocks = <&gcc PCIE_1_A_CLK>,
1198 <&gcc PCIE_1_H_CLK>,
1199 <&gcc PCIE_1_PHY_CLK>,
1200 <&gcc PCIE_1_AUX_CLK>,
1201 <&gcc PCIE_1_ALT_REF_CLK>;
1202 clock-names = "core", "iface", "phy", "aux", "ref";
1203
1204 assigned-clocks = <&gcc PCIE_1_ALT_REF_CLK>;
1205 assigned-clock-rates = <100000000>;
1206
1207 resets = <&gcc PCIE_1_ACLK_RESET>,
1208 <&gcc PCIE_1_HCLK_RESET>,
1209 <&gcc PCIE_1_POR_RESET>,
1210 <&gcc PCIE_1_PCI_RESET>,
1211 <&gcc PCIE_1_PHY_RESET>,
1212 <&gcc PCIE_1_EXT_RESET>;
1213 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
1214
1215 pinctrl-0 = <&pcie1_pins>;
1216 pinctrl-names = "default";
1217
1218 perst-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
1219
1220 phy-tx0-term-offset = <7>;
1221
1222 status = "disabled";
1223 };
1224
1225 pcie2: pci@1b900000 {
1226 compatible = "qcom,pcie-ipq8064";
1227 reg = <0x1b900000 0x1000
1228 0x1b902000 0x80
1229 0x1ba00000 0x100
1230 0x35f00000 0x100000>;
1231 reg-names = "dbi", "elbi", "parf", "config";
1232 device_type = "pci";
1233 linux,pci-domain = <2>;
1234 bus-range = <0x00 0xff>;
1235 num-lanes = <1>;
1236 #address-cells = <3>;
1237 #size-cells = <2>;
1238
1239 ranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00100000 /* downstream I/O */
1240 0x82000000 0 0x32000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */
1241
1242 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
1243 interrupt-names = "msi";
1244 #interrupt-cells = <1>;
1245 interrupt-map-mask = <0 0 0 0x7>;
1246 interrupt-map = <0 0 0 1 &intc 0 72 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1247 <0 0 0 2 &intc 0 73 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1248 <0 0 0 3 &intc 0 74 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1249 <0 0 0 4 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1250
1251 clocks = <&gcc PCIE_2_A_CLK>,
1252 <&gcc PCIE_2_H_CLK>,
1253 <&gcc PCIE_2_PHY_CLK>,
1254 <&gcc PCIE_2_AUX_CLK>,
1255 <&gcc PCIE_2_ALT_REF_CLK>;
1256 clock-names = "core", "iface", "phy", "aux", "ref";
1257
1258 assigned-clocks = <&gcc PCIE_2_ALT_REF_CLK>;
1259 assigned-clock-rates = <100000000>;
1260
1261 resets = <&gcc PCIE_2_ACLK_RESET>,
1262 <&gcc PCIE_2_HCLK_RESET>,
1263 <&gcc PCIE_2_POR_RESET>,
1264 <&gcc PCIE_2_PCI_RESET>,
1265 <&gcc PCIE_2_PHY_RESET>,
1266 <&gcc PCIE_2_EXT_RESET>;
1267 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
1268
1269 pinctrl-0 = <&pcie2_pins>;
1270 pinctrl-names = "default";
1271
1272 perst-gpios = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>;
1273
1274 phy-tx0-term-offset = <7>;
1275
1276 status = "disabled";
1277 };
1278
1279 adm_dma: dma@18300000 {
1280 compatible = "qcom,adm";
1281 reg = <0x18300000 0x100000>;
1282 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
1283 #dma-cells = <1>;
1284
1285 clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>;
1286 clock-names = "core", "iface";
1287
1288 resets = <&gcc ADM0_RESET>,
1289 <&gcc ADM0_PBUS_RESET>,
1290 <&gcc ADM0_C0_RESET>,
1291 <&gcc ADM0_C1_RESET>,
1292 <&gcc ADM0_C2_RESET>;
1293 reset-names = "clk", "pbus", "c0", "c1", "c2";
1294 qcom,ee = <0>;
1295
1296 status = "disabled";
1297 };
1298
1299 nand_controller: nand-controller@1ac00000 {
1300 compatible = "qcom,ipq806x-nand";
1301 reg = <0x1ac00000 0x800>;
1302
1303 clocks = <&gcc EBI2_CLK>,
1304 <&gcc EBI2_AON_CLK>;
1305 clock-names = "core", "aon";
1306
1307 dmas = <&adm_dma 3>;
1308 dma-names = "rxtx";
1309 qcom,cmd-crci = <15>;
1310 qcom,data-crci = <3>;
1311
1312 status = "disabled";
1313
1314 #address-cells = <1>;
1315 #size-cells = <0>;
1316 };
1317
1318 nss_common: syscon@03000000 {
1319 compatible = "syscon";
1320 reg = <0x03000000 0x0000FFFF>;
1321 };
1322
1323 qsgmii_csr: syscon@1bb00000 {
1324 compatible = "syscon";
1325 reg = <0x1bb00000 0x000001FF>;
1326 };
1327
1328 stmmac_axi_setup: stmmac-axi-config {
1329 snps,wr_osr_lmt = <7>;
1330 snps,rd_osr_lmt = <7>;
1331 snps,blen = <16 0 0 0 0 0 0>;
1332 };
1333
1334 mdio0: mdio@37000000 {
1335 #address-cells = <1>;
1336 #size-cells = <0>;
1337
1338 compatible = "qcom,ipq8064-mdio", "syscon";
1339 reg = <0x37000000 0x200000>;
1340 resets = <&gcc GMAC_CORE1_RESET>;
1341 reset-names = "stmmaceth";
1342 clocks = <&gcc GMAC_CORE1_CLK>;
1343 clock-names = "stmmaceth";
1344
1345 status = "disabled";
1346 };
1347
1348 gmac0: ethernet@37000000 {
1349 device_type = "network";
1350 compatible = "qcom,ipq806x-gmac";
1351 reg = <0x37000000 0x200000>;
1352 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
1353 interrupt-names = "macirq";
1354
1355 snps,axi-config = <&stmmac_axi_setup>;
1356 snps,pbl = <32>;
1357 snps,aal = <1>;
1358
1359 qcom,nss-common = <&nss_common>;
1360 qcom,qsgmii-csr = <&qsgmii_csr>;
1361
1362 clocks = <&gcc GMAC_CORE1_CLK>;
1363 clock-names = "stmmaceth";
1364
1365 resets = <&gcc GMAC_CORE1_RESET>;
1366 reset-names = "stmmaceth";
1367
1368 status = "disabled";
1369 };
1370
1371 gmac1: ethernet@37200000 {
1372 device_type = "network";
1373 compatible = "qcom,ipq806x-gmac";
1374 reg = <0x37200000 0x200000>;
1375 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
1376 interrupt-names = "macirq";
1377
1378 snps,axi-config = <&stmmac_axi_setup>;
1379 snps,pbl = <32>;
1380 snps,aal = <1>;
1381
1382 qcom,nss-common = <&nss_common>;
1383 qcom,qsgmii-csr = <&qsgmii_csr>;
1384
1385 clocks = <&gcc GMAC_CORE2_CLK>;
1386 clock-names = "stmmaceth";
1387
1388 resets = <&gcc GMAC_CORE2_RESET>;
1389 reset-names = "stmmaceth";
1390
1391 status = "disabled";
1392 };
1393
1394 gmac2: ethernet@37400000 {
1395 device_type = "network";
1396 compatible = "qcom,ipq806x-gmac", "snps,dwmac";
1397 reg = <0x37400000 0x200000>;
1398 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
1399 interrupt-names = "macirq";
1400
1401 snps,axi-config = <&stmmac_axi_setup>;
1402 snps,pbl = <32>;
1403 snps,aal = <1>;
1404
1405 qcom,nss-common = <&nss_common>;
1406 qcom,qsgmii-csr = <&qsgmii_csr>;
1407
1408 clocks = <&gcc GMAC_CORE3_CLK>;
1409 clock-names = "stmmaceth";
1410
1411 resets = <&gcc GMAC_CORE3_RESET>;
1412 reset-names = "stmmaceth";
1413
1414 status = "disabled";
1415 };
1416
1417 gmac3: ethernet@37600000 {
1418 device_type = "network";
1419 compatible = "qcom,ipq806x-gmac", "snps,dwmac";
1420 reg = <0x37600000 0x200000>;
1421 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
1422 interrupt-names = "macirq";
1423
1424 snps,axi-config = <&stmmac_axi_setup>;
1425 snps,pbl = <32>;
1426 snps,aal = <1>;
1427
1428 qcom,nss-common = <&nss_common>;
1429 qcom,qsgmii-csr = <&qsgmii_csr>;
1430
1431 clocks = <&gcc GMAC_CORE4_CLK>;
1432 clock-names = "stmmaceth";
1433
1434 resets = <&gcc GMAC_CORE4_RESET>;
1435 reset-names = "stmmaceth";
1436
1437 status = "disabled";
1438 };
1439
1440 /* Temporary fixed regulator */
1441 vsdcc_fixed: vsdcc-regulator {
1442 compatible = "regulator-fixed";
1443 regulator-name = "SDCC Power";
1444 regulator-min-microvolt = <3300000>;
1445 regulator-max-microvolt = <3300000>;
1446 regulator-always-on;
1447 };
1448
1449 sdcc1bam: dma@12402000 {
1450 compatible = "qcom,bam-v1.3.0";
1451 reg = <0x12402000 0x8000>;
1452 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1453 clocks = <&gcc SDC1_H_CLK>;
1454 clock-names = "bam_clk";
1455 #dma-cells = <1>;
1456 qcom,ee = <0>;
1457 };
1458
1459 sdcc3bam: dma@12182000 {
1460 compatible = "qcom,bam-v1.3.0";
1461 reg = <0x12182000 0x8000>;
1462 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1463 clocks = <&gcc SDC3_H_CLK>;
1464 clock-names = "bam_clk";
1465 #dma-cells = <1>;
1466 qcom,ee = <0>;
1467 };
1468
1469 amba: amba {
1470 compatible = "arm,amba-bus";
1471 #address-cells = <1>;
1472 #size-cells = <1>;
1473 ranges;
1474 sdcc1: sdcc@12400000 {
1475 status = "disabled";
1476 compatible = "arm,pl18x", "arm,primecell";
1477 arm,primecell-periphid = <0x00051180>;
1478 reg = <0x12400000 0x2000>;
1479 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
1480 interrupt-names = "cmd_irq";
1481 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
1482 clock-names = "mclk", "apb_pclk";
1483 bus-width = <8>;
1484 max-frequency = <96000000>;
1485 non-removable;
1486 cap-sd-highspeed;
1487 cap-mmc-highspeed;
1488 vmmc-supply = <&vsdcc_fixed>;
1489 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
1490 dma-names = "tx", "rx";
1491 };
1492
1493 sdcc3: sdcc@12180000 {
1494 compatible = "arm,pl18x", "arm,primecell";
1495 arm,primecell-periphid = <0x00051180>;
1496 status = "disabled";
1497 reg = <0x12180000 0x2000>;
1498 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1499 interrupt-names = "cmd_irq";
1500 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
1501 clock-names = "mclk", "apb_pclk";
1502 bus-width = <8>;
1503 cap-sd-highspeed;
1504 cap-mmc-highspeed;
1505 max-frequency = <192000000>;
1506 #mmc-ddr-1_8v;
1507 sd-uhs-sdr104;
1508 sd-uhs-ddr50;
1509 vqmmc-supply = <&vsdcc_fixed>;
1510 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
1511 dma-names = "tx", "rx";
1512 };
1513 };
1514 };
1515
1516 sfpb_mutex: sfpb-mutex {
1517 compatible = "qcom,sfpb-mutex";
1518 syscon = <&sfpb_mutex_block 4 4>;
1519
1520 #hwlock-cells = <1>;
1521 };
1522
1523 smem {
1524 compatible = "qcom,smem";
1525 memory-region = <&smem>;
1526 hwlocks = <&sfpb_mutex 3>;
1527 };
1528 };
OpenWrt Source Repository