target/linux/ipq806x/patches-4.19/0034-0008-clk-qcom-Add-KPSS-ACC-GCC-driver.patch

   1 From 3ddc3564d3c9f097986bd4ccbe34152413811335 Mon Sep 17 00:00:00 2001
   2 From: Stephen Boyd <sboyd@codeaurora.org>
   3 Date: Tue, 14 Aug 2018 17:42:27 +0530
   4 Subject: [PATCH 08/12] clk: qcom: Add KPSS ACC/GCC driver
   5
   6 The ACC and GCC regions present in KPSSv1 contain registers to
   7 control clocks and power to each Krait CPU and L2. For CPUfreq
   8 purposes probe these devices and expose a mux clock that chooses
   9 between PXO and PLL8.
  10
  11 Cc: <devicetree@vger.kernel.org>
  12 Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
  13 Signed-off-by: Sricharan R <sricharan@codeaurora.org>
  14 Tested-by: Craig Tatlor <ctatlor97@gmail.com>
  15 Signed-off-by: Stephen Boyd <sboyd@kernel.org>
  16 ---
  17  drivers/clk/qcom/Kconfig    |  8 ++++
  18  drivers/clk/qcom/Makefile   |  1 +
  19  drivers/clk/qcom/kpss-xcc.c | 87 +++++++++++++++++++++++++++++++++++++
  20  3 files changed, 96 insertions(+)
  21  create mode 100644 drivers/clk/qcom/kpss-xcc.c
  22
  23 --- a/drivers/clk/qcom/Kconfig
  24 +++ b/drivers/clk/qcom/Kconfig
  25 @@ -284,3 +284,11 @@ config QCOM_HFPLL
  26           Support for the high-frequency PLLs present on Qualcomm devices.
  27           Say Y if you want to support CPU frequency scaling on devices
  28           such as MSM8974, APQ8084, etc.
  29 +
  30 +config KPSS_XCC
  31 +       tristate "KPSS Clock Controller"
  32 +       depends on COMMON_CLK_QCOM
  33 +       help
  34 +         Support for the Krait ACC and GCC clock controllers. Say Y
  35 +         if you want to support CPU frequency scaling on devices such
  36 +         as MSM8960, APQ8064, etc.
  37 --- a/drivers/clk/qcom/Makefile
  38 +++ b/drivers/clk/qcom/Makefile
  39 @@ -45,4 +45,5 @@ obj-$(CONFIG_SDM_DISPCC_845) += dispcc-s
  40  obj-$(CONFIG_SDM_GCC_845) += gcc-sdm845.o
  41  obj-$(CONFIG_SDM_VIDEOCC_845) += videocc-sdm845.o
  42  obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o
  43 +obj-$(CONFIG_KPSS_XCC) += kpss-xcc.o
  44  obj-$(CONFIG_QCOM_HFPLL) += hfpll.o
  45 --- /dev/null
  46 +++ b/drivers/clk/qcom/kpss-xcc.c
  47 @@ -0,0 +1,87 @@
  48 +// SPDX-License-Identifier: GPL-2.0
  49 +// Copyright (c) 2018, The Linux Foundation. All rights reserved.
  50 +
  51 +#include <linux/kernel.h>
  52 +#include <linux/init.h>
  53 +#include <linux/module.h>
  54 +#include <linux/platform_device.h>
  55 +#include <linux/err.h>
  56 +#include <linux/io.h>
  57 +#include <linux/of.h>
  58 +#include <linux/of_device.h>
  59 +#include <linux/clk.h>
  60 +#include <linux/clk-provider.h>
  61 +
  62 +static const char *aux_parents[] = {
  63 +       "pll8_vote",
  64 +       "pxo",
  65 +};
  66 +
  67 +static unsigned int aux_parent_map[] = {
  68 +       3,
  69 +       0,
  70 +};
  71 +
  72 +static const struct of_device_id kpss_xcc_match_table[] = {
  73 +       { .compatible = "qcom,kpss-acc-v1", .data = (void *)1UL },
  74 +       { .compatible = "qcom,kpss-gcc" },
  75 +       {}
  76 +};
  77 +MODULE_DEVICE_TABLE(of, kpss_xcc_match_table);
  78 +
  79 +static int kpss_xcc_driver_probe(struct platform_device *pdev)
  80 +{
  81 +       const struct of_device_id *id;
  82 +       struct clk *clk;
  83 +       struct resource *res;
  84 +       void __iomem *base;
  85 +       const char *name;
  86 +
  87 +       id = of_match_device(kpss_xcc_match_table, &pdev->dev);
  88 +       if (!id)
  89 +               return -ENODEV;
  90 +
  91 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  92 +       base = devm_ioremap_resource(&pdev->dev, res);
  93 +       if (IS_ERR(base))
  94 +               return PTR_ERR(base);
  95 +
  96 +       if (id->data) {
  97 +               if (of_property_read_string_index(pdev->dev.of_node,
  98 +                                                 "clock-output-names",
  99 +                                                 0, &name))
 100 +                       return -ENODEV;
 101 +               base += 0x14;
 102 +       } else {
 103 +               name = "acpu_l2_aux";
 104 +               base += 0x28;
 105 +       }
 106 +
 107 +       clk = clk_register_mux_table(&pdev->dev, name, aux_parents,
 108 +                                    ARRAY_SIZE(aux_parents), 0, base, 0, 0x3,
 109 +                                    0, aux_parent_map, NULL);
 110 +
 111 +       platform_set_drvdata(pdev, clk);
 112 +
 113 +       return PTR_ERR_OR_ZERO(clk);
 114 +}
 115 +
 116 +static int kpss_xcc_driver_remove(struct platform_device *pdev)
 117 +{
 118 +       clk_unregister_mux(platform_get_drvdata(pdev));
 119 +       return 0;
 120 +}
 121 +
 122 +static struct platform_driver kpss_xcc_driver = {
 123 +       .probe = kpss_xcc_driver_probe,
 124 +       .remove = kpss_xcc_driver_remove,
 125 +       .driver = {
 126 +               .name = "kpss-xcc",
 127 +               .of_match_table = kpss_xcc_match_table,
 128 +       },
 129 +};
 130 +module_platform_driver(kpss_xcc_driver);
 131 +
 132 +MODULE_DESCRIPTION("Krait Processor Sub System (KPSS) Clock Driver");
 133 +MODULE_LICENSE("GPL v2");
 134 +MODULE_ALIAS("platform:kpss-xcc");