target/linux/ipq806x/patches-5.4/093-3-v5.8-ipq806x-PCI-qcom-Add-missing-reset-for-ipq806x.patch

   1 From ee367e2cdd2202b5714982739e684543cd2cee0e Mon Sep 17 00:00:00 2001
   2 From: Ansuel Smith <ansuelsmth@gmail.com>
   3 Date: Mon, 15 Jun 2020 23:06:00 +0200
   4 Subject: PCI: qcom: Add missing reset for ipq806x
   5
   6 Add missing ext reset used by ipq8064 SoC in PCIe qcom driver.
   7
   8 Link: https://lore.kernel.org/r/20200615210608.21469-5-ansuelsmth@gmail.com
   9 Fixes: 82a823833f4e ("PCI: qcom: Add Qualcomm PCIe controller driver")
  10 Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
  11 Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
  12 Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
  13 Reviewed-by: Rob Herring <robh@kernel.org>
  14 Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
  15 Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>
  16 Cc: stable@vger.kernel.org # v4.5+
  17 ---
  18  drivers/pci/controller/dwc/pcie-qcom.c | 12 ++++++++++++
  19  1 file changed, 12 insertions(+)
  20
  21 --- a/drivers/pci/controller/dwc/pcie-qcom.c
  22 +++ b/drivers/pci/controller/dwc/pcie-qcom.c
  23 @@ -92,6 +92,7 @@ struct qcom_pcie_resources_2_1_0 {
  24         struct reset_control *ahb_reset;
  25         struct reset_control *por_reset;
  26         struct reset_control *phy_reset;
  27 +       struct reset_control *ext_reset;
  28         struct regulator_bulk_data supplies[QCOM_PCIE_2_1_0_MAX_SUPPLY];
  29  };
  30
  31 @@ -261,6 +262,10 @@ static int qcom_pcie_get_resources_2_1_0
  32         if (IS_ERR(res->por_reset))
  33                 return PTR_ERR(res->por_reset);
  34
  35 +       res->ext_reset = devm_reset_control_get_optional_exclusive(dev, "ext");
  36 +       if (IS_ERR(res->ext_reset))
  37 +               return PTR_ERR(res->ext_reset);
  38 +
  39         res->phy_reset = devm_reset_control_get_exclusive(dev, "phy");
  40         return PTR_ERR_OR_ZERO(res->phy_reset);
  41  }
  42 @@ -274,6 +279,7 @@ static void qcom_pcie_deinit_2_1_0(struc
  43         reset_control_assert(res->axi_reset);
  44         reset_control_assert(res->ahb_reset);
  45         reset_control_assert(res->por_reset);
  46 +       reset_control_assert(res->ext_reset);
  47         reset_control_assert(res->phy_reset);
  48         clk_disable_unprepare(res->iface_clk);
  49         clk_disable_unprepare(res->core_clk);
  50 @@ -332,6 +338,12 @@ static int qcom_pcie_init_2_1_0(struct q
  51                 goto err_deassert_ahb;
  52         }
  53
  54 +       ret = reset_control_deassert(res->ext_reset);
  55 +       if (ret) {
  56 +               dev_err(dev, "cannot deassert ext reset\n");
  57 +               goto err_deassert_ahb;
  58 +       }
  59 +
  60         /* enable PCIe clocks and resets */
  61         val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
  62         val &= ~BIT(0);