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[openwrt/openwrt.git] / target / linux / ipq806x / patches / 0105-clk-qcom-Support-display-RCG-clocks.patch
1 From 3123079878e29eb8c541111e30de4d1bb42ac6f9 Mon Sep 17 00:00:00 2001
2 From: Stephen Boyd <sboyd@codeaurora.org>
3 Date: Fri, 16 May 2014 16:07:11 -0700
4 Subject: [PATCH 105/182] clk: qcom: Support display RCG clocks
5
6 Add support for the DSI/EDP/HDMI RCG clocks. With the proper
7 display driver in place this should allow us to support display
8 clocks on msm8974 based devices.
9
10 Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
11 Signed-off-by: Mike Turquette <mturquette@linaro.org>
12 ---
13 drivers/clk/qcom/clk-rcg.h | 3 +
14 drivers/clk/qcom/clk-rcg2.c | 299 ++++++++++++++++++++++++++++++++++++++++---
15 2 files changed, 287 insertions(+), 15 deletions(-)
16
17 diff --git a/drivers/clk/qcom/clk-rcg.h b/drivers/clk/qcom/clk-rcg.h
18 index 1d6b6de..b9ec11d 100644
19 --- a/drivers/clk/qcom/clk-rcg.h
20 +++ b/drivers/clk/qcom/clk-rcg.h
21 @@ -155,5 +155,8 @@ struct clk_rcg2 {
22 #define to_clk_rcg2(_hw) container_of(to_clk_regmap(_hw), struct clk_rcg2, clkr)
23
24 extern const struct clk_ops clk_rcg2_ops;
25 +extern const struct clk_ops clk_edp_pixel_ops;
26 +extern const struct clk_ops clk_byte_ops;
27 +extern const struct clk_ops clk_pixel_ops;
28
29 #endif
30 diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c
31 index cbecaec..cd185d5 100644
32 --- a/drivers/clk/qcom/clk-rcg2.c
33 +++ b/drivers/clk/qcom/clk-rcg2.c
34 @@ -19,6 +19,7 @@
35 #include <linux/clk-provider.h>
36 #include <linux/delay.h>
37 #include <linux/regmap.h>
38 +#include <linux/math64.h>
39
40 #include <asm/div64.h>
41
42 @@ -225,31 +226,25 @@ static long clk_rcg2_determine_rate(struct clk_hw *hw, unsigned long rate,
43 return _freq_tbl_determine_rate(hw, rcg->freq_tbl, rate, p_rate, p);
44 }
45
46 -static int __clk_rcg2_set_rate(struct clk_hw *hw, unsigned long rate)
47 +static int clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f)
48 {
49 - struct clk_rcg2 *rcg = to_clk_rcg2(hw);
50 - const struct freq_tbl *f;
51 u32 cfg, mask;
52 int ret;
53
54 - f = find_freq(rcg->freq_tbl, rate);
55 - if (!f)
56 - return -EINVAL;
57 -
58 if (rcg->mnd_width && f->n) {
59 mask = BIT(rcg->mnd_width) - 1;
60 - ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + M_REG,
61 - mask, f->m);
62 + ret = regmap_update_bits(rcg->clkr.regmap,
63 + rcg->cmd_rcgr + M_REG, mask, f->m);
64 if (ret)
65 return ret;
66
67 - ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + N_REG,
68 - mask, ~(f->n - f->m));
69 + ret = regmap_update_bits(rcg->clkr.regmap,
70 + rcg->cmd_rcgr + N_REG, mask, ~(f->n - f->m));
71 if (ret)
72 return ret;
73
74 - ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + D_REG,
75 - mask, ~f->n);
76 + ret = regmap_update_bits(rcg->clkr.regmap,
77 + rcg->cmd_rcgr + D_REG, mask, ~f->n);
78 if (ret)
79 return ret;
80 }
81 @@ -260,14 +255,26 @@ static int __clk_rcg2_set_rate(struct clk_hw *hw, unsigned long rate)
82 cfg |= rcg->parent_map[f->src] << CFG_SRC_SEL_SHIFT;
83 if (rcg->mnd_width && f->n)
84 cfg |= CFG_MODE_DUAL_EDGE;
85 - ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, mask,
86 - cfg);
87 + ret = regmap_update_bits(rcg->clkr.regmap,
88 + rcg->cmd_rcgr + CFG_REG, mask, cfg);
89 if (ret)
90 return ret;
91
92 return update_config(rcg);
93 }
94
95 +static int __clk_rcg2_set_rate(struct clk_hw *hw, unsigned long rate)
96 +{
97 + struct clk_rcg2 *rcg = to_clk_rcg2(hw);
98 + const struct freq_tbl *f;
99 +
100 + f = find_freq(rcg->freq_tbl, rate);
101 + if (!f)
102 + return -EINVAL;
103 +
104 + return clk_rcg2_configure(rcg, f);
105 +}
106 +
107 static int clk_rcg2_set_rate(struct clk_hw *hw, unsigned long rate,
108 unsigned long parent_rate)
109 {
110 @@ -290,3 +297,265 @@ const struct clk_ops clk_rcg2_ops = {
111 .set_rate_and_parent = clk_rcg2_set_rate_and_parent,
112 };
113 EXPORT_SYMBOL_GPL(clk_rcg2_ops);
114 +
115 +struct frac_entry {
116 + int num;
117 + int den;
118 +};
119 +
120 +static const struct frac_entry frac_table_675m[] = { /* link rate of 270M */
121 + { 52, 295 }, /* 119 M */
122 + { 11, 57 }, /* 130.25 M */
123 + { 63, 307 }, /* 138.50 M */
124 + { 11, 50 }, /* 148.50 M */
125 + { 47, 206 }, /* 154 M */
126 + { 31, 100 }, /* 205.25 M */
127 + { 107, 269 }, /* 268.50 M */
128 + { },
129 +};
130 +
131 +static struct frac_entry frac_table_810m[] = { /* Link rate of 162M */
132 + { 31, 211 }, /* 119 M */
133 + { 32, 199 }, /* 130.25 M */
134 + { 63, 307 }, /* 138.50 M */
135 + { 11, 60 }, /* 148.50 M */
136 + { 50, 263 }, /* 154 M */
137 + { 31, 120 }, /* 205.25 M */
138 + { 119, 359 }, /* 268.50 M */
139 + { },
140 +};
141 +
142 +static int clk_edp_pixel_set_rate(struct clk_hw *hw, unsigned long rate,
143 + unsigned long parent_rate)
144 +{
145 + struct clk_rcg2 *rcg = to_clk_rcg2(hw);
146 + struct freq_tbl f = *rcg->freq_tbl;
147 + const struct frac_entry *frac;
148 + int delta = 100000;
149 + s64 src_rate = parent_rate;
150 + s64 request;
151 + u32 mask = BIT(rcg->hid_width) - 1;
152 + u32 hid_div;
153 +
154 + if (src_rate == 810000000)
155 + frac = frac_table_810m;
156 + else
157 + frac = frac_table_675m;
158 +
159 + for (; frac->num; frac++) {
160 + request = rate;
161 + request *= frac->den;
162 + request = div_s64(request, frac->num);
163 + if ((src_rate < (request - delta)) ||
164 + (src_rate > (request + delta)))
165 + continue;
166 +
167 + regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,
168 + &hid_div);
169 + f.pre_div = hid_div;
170 + f.pre_div >>= CFG_SRC_DIV_SHIFT;
171 + f.pre_div &= mask;
172 + f.m = frac->num;
173 + f.n = frac->den;
174 +
175 + return clk_rcg2_configure(rcg, &f);
176 + }
177 +
178 + return -EINVAL;
179 +}
180 +
181 +static int clk_edp_pixel_set_rate_and_parent(struct clk_hw *hw,
182 + unsigned long rate, unsigned long parent_rate, u8 index)
183 +{
184 + /* Parent index is set statically in frequency table */
185 + return clk_edp_pixel_set_rate(hw, rate, parent_rate);
186 +}
187 +
188 +static long clk_edp_pixel_determine_rate(struct clk_hw *hw, unsigned long rate,
189 + unsigned long *p_rate, struct clk **p)
190 +{
191 + struct clk_rcg2 *rcg = to_clk_rcg2(hw);
192 + const struct freq_tbl *f = rcg->freq_tbl;
193 + const struct frac_entry *frac;
194 + int delta = 100000;
195 + s64 src_rate = *p_rate;
196 + s64 request;
197 + u32 mask = BIT(rcg->hid_width) - 1;
198 + u32 hid_div;
199 +
200 + /* Force the correct parent */
201 + *p = clk_get_parent_by_index(hw->clk, f->src);
202 +
203 + if (src_rate == 810000000)
204 + frac = frac_table_810m;
205 + else
206 + frac = frac_table_675m;
207 +
208 + for (; frac->num; frac++) {
209 + request = rate;
210 + request *= frac->den;
211 + request = div_s64(request, frac->num);
212 + if ((src_rate < (request - delta)) ||
213 + (src_rate > (request + delta)))
214 + continue;
215 +
216 + regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,
217 + &hid_div);
218 + hid_div >>= CFG_SRC_DIV_SHIFT;
219 + hid_div &= mask;
220 +
221 + return calc_rate(src_rate, frac->num, frac->den, !!frac->den,
222 + hid_div);
223 + }
224 +
225 + return -EINVAL;
226 +}
227 +
228 +const struct clk_ops clk_edp_pixel_ops = {
229 + .is_enabled = clk_rcg2_is_enabled,
230 + .get_parent = clk_rcg2_get_parent,
231 + .set_parent = clk_rcg2_set_parent,
232 + .recalc_rate = clk_rcg2_recalc_rate,
233 + .set_rate = clk_edp_pixel_set_rate,
234 + .set_rate_and_parent = clk_edp_pixel_set_rate_and_parent,
235 + .determine_rate = clk_edp_pixel_determine_rate,
236 +};
237 +EXPORT_SYMBOL_GPL(clk_edp_pixel_ops);
238 +
239 +static long clk_byte_determine_rate(struct clk_hw *hw, unsigned long rate,
240 + unsigned long *p_rate, struct clk **p)
241 +{
242 + struct clk_rcg2 *rcg = to_clk_rcg2(hw);
243 + const struct freq_tbl *f = rcg->freq_tbl;
244 + unsigned long parent_rate, div;
245 + u32 mask = BIT(rcg->hid_width) - 1;
246 +
247 + if (rate == 0)
248 + return -EINVAL;
249 +
250 + *p = clk_get_parent_by_index(hw->clk, f->src);
251 + *p_rate = parent_rate = __clk_round_rate(*p, rate);
252 +
253 + div = DIV_ROUND_UP((2 * parent_rate), rate) - 1;
254 + div = min_t(u32, div, mask);
255 +
256 + return calc_rate(parent_rate, 0, 0, 0, div);
257 +}
258 +
259 +static int clk_byte_set_rate(struct clk_hw *hw, unsigned long rate,
260 + unsigned long parent_rate)
261 +{
262 + struct clk_rcg2 *rcg = to_clk_rcg2(hw);
263 + struct freq_tbl f = *rcg->freq_tbl;
264 + unsigned long div;
265 + u32 mask = BIT(rcg->hid_width) - 1;
266 +
267 + div = DIV_ROUND_UP((2 * parent_rate), rate) - 1;
268 + div = min_t(u32, div, mask);
269 +
270 + f.pre_div = div;
271 +
272 + return clk_rcg2_configure(rcg, &f);
273 +}
274 +
275 +static int clk_byte_set_rate_and_parent(struct clk_hw *hw,
276 + unsigned long rate, unsigned long parent_rate, u8 index)
277 +{
278 + /* Parent index is set statically in frequency table */
279 + return clk_byte_set_rate(hw, rate, parent_rate);
280 +}
281 +
282 +const struct clk_ops clk_byte_ops = {
283 + .is_enabled = clk_rcg2_is_enabled,
284 + .get_parent = clk_rcg2_get_parent,
285 + .set_parent = clk_rcg2_set_parent,
286 + .recalc_rate = clk_rcg2_recalc_rate,
287 + .set_rate = clk_byte_set_rate,
288 + .set_rate_and_parent = clk_byte_set_rate_and_parent,
289 + .determine_rate = clk_byte_determine_rate,
290 +};
291 +EXPORT_SYMBOL_GPL(clk_byte_ops);
292 +
293 +static const struct frac_entry frac_table_pixel[] = {
294 + { 3, 8 },
295 + { 2, 9 },
296 + { 4, 9 },
297 + { 1, 1 },
298 + { }
299 +};
300 +
301 +static long clk_pixel_determine_rate(struct clk_hw *hw, unsigned long rate,
302 + unsigned long *p_rate, struct clk **p)
303 +{
304 + struct clk_rcg2 *rcg = to_clk_rcg2(hw);
305 + unsigned long request, src_rate;
306 + int delta = 100000;
307 + const struct freq_tbl *f = rcg->freq_tbl;
308 + const struct frac_entry *frac = frac_table_pixel;
309 + struct clk *parent = *p = clk_get_parent_by_index(hw->clk, f->src);
310 +
311 + for (; frac->num; frac++) {
312 + request = (rate * frac->den) / frac->num;
313 +
314 + src_rate = __clk_round_rate(parent, request);
315 + if ((src_rate < (request - delta)) ||
316 + (src_rate > (request + delta)))
317 + continue;
318 +
319 + *p_rate = src_rate;
320 + return (src_rate * frac->num) / frac->den;
321 + }
322 +
323 + return -EINVAL;
324 +}
325 +
326 +static int clk_pixel_set_rate(struct clk_hw *hw, unsigned long rate,
327 + unsigned long parent_rate)
328 +{
329 + struct clk_rcg2 *rcg = to_clk_rcg2(hw);
330 + struct freq_tbl f = *rcg->freq_tbl;
331 + const struct frac_entry *frac = frac_table_pixel;
332 + unsigned long request, src_rate;
333 + int delta = 100000;
334 + u32 mask = BIT(rcg->hid_width) - 1;
335 + u32 hid_div;
336 + struct clk *parent = clk_get_parent_by_index(hw->clk, f.src);
337 +
338 + for (; frac->num; frac++) {
339 + request = (rate * frac->den) / frac->num;
340 +
341 + src_rate = __clk_round_rate(parent, request);
342 + if ((src_rate < (request - delta)) ||
343 + (src_rate > (request + delta)))
344 + continue;
345 +
346 + regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,
347 + &hid_div);
348 + f.pre_div = hid_div;
349 + f.pre_div >>= CFG_SRC_DIV_SHIFT;
350 + f.pre_div &= mask;
351 + f.m = frac->num;
352 + f.n = frac->den;
353 +
354 + return clk_rcg2_configure(rcg, &f);
355 + }
356 + return -EINVAL;
357 +}
358 +
359 +static int clk_pixel_set_rate_and_parent(struct clk_hw *hw, unsigned long rate,
360 + unsigned long parent_rate, u8 index)
361 +{
362 + /* Parent index is set statically in frequency table */
363 + return clk_pixel_set_rate(hw, rate, parent_rate);
364 +}
365 +
366 +const struct clk_ops clk_pixel_ops = {
367 + .is_enabled = clk_rcg2_is_enabled,
368 + .get_parent = clk_rcg2_get_parent,
369 + .set_parent = clk_rcg2_set_parent,
370 + .recalc_rate = clk_rcg2_recalc_rate,
371 + .set_rate = clk_pixel_set_rate,
372 + .set_rate_and_parent = clk_pixel_set_rate_and_parent,
373 + .determine_rate = clk_pixel_determine_rate,
374 +};
375 +EXPORT_SYMBOL_GPL(clk_pixel_ops);
376 --
377 1.7.10.4
378
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