target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9.dtsi

   1 /dts-v1/;
   2
   3 #include <dt-bindings/gpio/gpio.h>
   4 #include <dt-bindings/phy/phy-lantiq-vrx200-pcie.h>
   5
   6 / {
   7         #address-cells = <1>;
   8         #size-cells = <1>;
   9         compatible = "lantiq,xway", "lantiq,vr9";
  10
  11         aliases {
  12                 serial0 = &asc1;
  13         };
  14
  15         chosen {
  16                 stdout-path = "serial0:115200n8";
  17         };
  18
  19         cpus {
  20                 #address-cells = <1>;
  21                 #size-cells = <0>;
  22
  23                 cpu@0 {
  24                         compatible = "mips,mips34Kc";
  25                         reg = <0>;
  26                 };
  27         };
  28
  29         cputemp {
  30                 compatible = "lantiq,cputemp";
  31         };
  32
  33         reboot {
  34                 compatible = "syscon-reboot";
  35
  36                 regmap = <&rcu0>;
  37                 offset = <0x10>;
  38                 mask = <0xe0000000>;
  39         };
  40
  41         biu@1f800000 {
  42                 #address-cells = <1>;
  43                 #size-cells = <1>;
  44                 compatible = "lantiq,biu", "simple-bus";
  45                 reg = <0x1f800000 0x800000>;
  46                 ranges = <0x0 0x1f800000 0x7fffff>;
  47
  48                 icu0: icu@80200 {
  49                         #interrupt-cells = <1>;
  50                         interrupt-controller;
  51                         compatible = "lantiq,icu";
  52                         reg = <0x80200 0xc8     /* icu0 */
  53                                0x80300 0xc8>;   /* icu1 */
  54                 };
  55
  56                 watchdog@803f0 {
  57                         compatible = "lantiq,xrx100-wdt", "lantiq,xrx100-wdt";
  58                         reg = <0x803f0 0x10>;
  59
  60                         regmap = <&rcu0>;
  61                 };
  62         };
  63
  64         sram@1f000000 {
  65                 #address-cells = <1>;
  66                 #size-cells = <1>;
  67                 compatible = "lantiq,sram", "simple-bus";
  68                 reg = <0x1f000000 0x800000>;
  69                 ranges = <0x0 0x1f000000 0x7fffff>;
  70
  71                 eiu0: eiu@101000 {
  72                         #interrupt-cells = <1>;
  73                         interrupt-controller;
  74                         compatible = "lantiq,eiu-xway";
  75                         reg = <0x101000 0x1000>;
  76                         interrupt-parent = <&icu0>;
  77                         lantiq,eiu-irqs = <166 135 66 40 41 42>;
  78                 };
  79
  80                 pmu0: pmu@102000 {
  81                         compatible = "lantiq,pmu-xway";
  82                         reg = <0x102000 0x1000>;
  83                 };
  84
  85                 cgu0: cgu@103000 {
  86                         compatible = "lantiq,cgu-xway";
  87                         reg = <0x103000 0x1000>;
  88                 };
  89
  90                 dcdc@106a00 {
  91                         compatible = "lantiq,dcdc-xrx200";
  92                         reg = <0x106a00 0x200>;
  93                 };
  94
  95                 vmmc: vmmc@107000 {
  96                         status = "disabled";
  97                         compatible = "lantiq,vmmc-xway";
  98                         reg = <0x107000 0x300>;
  99                         interrupt-parent = <&icu0>;
 100                         interrupts = <150 151 152 153 154 155>;
 101                 };
 102
 103                 pcie0_phy: phy@106800 {
 104                         compatible = "lantiq,vrx200-pcie-phy";
 105                         reg = <0x106800 0x100>;
 106                         lantiq,rcu = <&rcu0>;
 107                         lantiq,rcu-endian-offset = <0x4c>;
 108                         lantiq,rcu-big-endian-mask = <0x80>; /* bit 7 */
 109                         big-endian;
 110                         resets = <&reset0 12 24>, <&reset0 22 22>;
 111                         reset-names = "phy", "pcie";
 112                         #phy-cells = <1>;
 113                 };
 114
 115                 rcu0: rcu@203000 {
 116                         #address-cells = <1>;
 117                         #size-cells = <1>;
 118                         compatible = "lantiq,xrx200-rcu", "simple-mfd", "syscon";
 119                         reg = <0x203000 0x100>;
 120                         ranges = <0x0 0x203000 0x100>;
 121                         big-endian;
 122
 123                         gphy0: gphy@20 {
 124                                 compatible = "lantiq,xrx200-gphy";
 125                                 reg = <0x20 0x4>;
 126
 127                                 resets = <&reset0 31 30>, <&reset1 7 7>;
 128                                 reset-names = "gphy", "gphy2";
 129                         };
 130
 131                         gphy1: gphy@68 {
 132                                 compatible = "lantiq,xrx200-gphy";
 133                                 reg = <0x68 0x4>;
 134
 135                                 resets = <&reset0 29 28>, <&reset1 6 6>;
 136                                 reset-names = "gphy", "gphy2";
 137                         };
 138
 139                         reset0: reset-controller@10 {
 140                                 compatible = "lantiq,xrx200-reset";
 141                                 reg = <0x10 4>, <0x14 4>;
 142
 143                                 #reset-cells = <2>;
 144                         };
 145
 146                         reset1: reset-controller@48 {
 147                                 compatible = "lantiq,xrx200-reset";
 148                                 reg = <0x48 4>, <0x24 4>;
 149
 150                                 #reset-cells = <2>;
 151                         };
 152
 153                         usb_phy0: usb2-phy@18 {
 154                                 compatible = "lantiq,xrx200-usb2-phy";
 155                                 reg = <0x18 4>, <0x38 4>;
 156                                 status = "disabled";
 157
 158                                 resets = <&reset1 4 4>, <&reset0 4 4>;
 159                                 reset-names = "phy", "ctrl";
 160                                 #phy-cells = <0>;
 161                         };
 162
 163                         usb_phy1: usb2-phy@34 {
 164                                 compatible = "lantiq,xrx200-usb2-phy";
 165                                 reg = <0x34 4>, <0x3c 4>;
 166                                 status = "disabled";
 167
 168                                 resets = <&reset1 5 5>, <&reset0 4 4>;
 169                                 reset-names = "phy", "ctrl";
 170                                 #phy-cells = <0>;
 171                         };
 172                 };
 173         };
 174
 175         fpi@10000000 {
 176                 compatible = "lantiq,xrx200-fpi", "simple-bus";
 177                 ranges = <0x0 0x10000000 0xf000000>;
 178                 reg =   <0x1f400000 0x1000>,
 179                         <0x10000000 0xf000000>;
 180                 regmap = <&rcu0>;
 181                 offset-endianness = <0x4c>;
 182                 #address-cells = <1>;
 183                 #size-cells = <1>;
 184
 185                 localbus: localbus@0 {
 186                         #address-cells = <2>;
 187                         #size-cells = <1>;
 188                         ranges = <0 0 0x0 0x3ffffff /* addrsel0 */
 189                                 1 0 0x4000000 0x4000010>; /* addsel1 */
 190                         compatible = "lantiq,localbus", "simple-bus";
 191                 };
 192
 193                 gptu@e100a00 {
 194                         compatible = "lantiq,gptu-xway";
 195                         reg = <0xe100a00 0x100>;
 196                         interrupt-parent = <&icu0>;
 197                         interrupts = <126 127 128 129 130 131>;
 198                 };
 199
 200                 usif: usif@da00000 {
 201                         compatible = "lantiq,usif";
 202                         reg = <0xda00000 0x1000000>;
 203                         interrupt-parent = <&icu0>;
 204                         interrupts = <29 125 107 108 109 110>;
 205                         status = "disabled";
 206                 };
 207
 208                 spi: spi@e100800 {
 209                         compatible = "lantiq,xrx200-spi", "lantiq,xrx100-spi";
 210                         reg = <0xe100800 0x100>;
 211                         interrupt-parent = <&icu0>;
 212                         interrupts = <22 23 24>;
 213                         interrupt-names = "spi_rx", "spi_tx", "spi_err",
 214                                         "spi_frm";
 215                         #address-cells = <1>;
 216                         #size-cells = <0>;
 217                         pinctrl-names = "default";
 218                         pinctrl-0 = <&spi_pins>, <&spi_cs4_pins>;
 219                         status = "disabled";
 220                 };
 221
 222                 gpio: pinmux@e100b10 {
 223                         compatible = "lantiq,xrx200-pinctrl";
 224                         #gpio-cells = <2>;
 225                         gpio-controller;
 226                         gpio-ranges = <&gpio 0 0 50>;
 227                         reg = <0xe100b10 0xa0>;
 228
 229                         gphy0_led0_pins: gphy0-led0 {
 230                                 mux {
 231                                         lantiq,groups = "gphy0 led0";
 232                                         lantiq,function = "gphy";
 233                                         lantiq,open-drain = <0>;
 234                                         lantiq,pull = <2>;
 235                                         lantiq,output = <1>;
 236                                 };
 237                         };
 238
 239                         gphy0_led1_pins: gphy0-led1 {
 240                                 mux {
 241                                         lantiq,groups = "gphy0 led1";
 242                                         lantiq,function = "gphy";
 243                                         lantiq,open-drain = <0>;
 244                                         lantiq,pull = <2>;
 245                                         lantiq,output = <1>;
 246                                 };
 247                         };
 248
 249                         gphy0_led2_pins: gphy0-led2 {
 250                                 mux {
 251                                         lantiq,groups = "gphy0 led2";
 252                                         lantiq,function = "gphy";
 253                                         lantiq,open-drain = <0>;
 254                                         lantiq,pull = <2>;
 255                                         lantiq,output = <1>;
 256                                 };
 257                         };
 258
 259                         gphy1_led0_pins: gphy1-led0 {
 260                                 mux {
 261                                         lantiq,groups = "gphy1 led0";
 262                                         lantiq,function = "gphy";
 263                                         lantiq,open-drain = <0>;
 264                                         lantiq,pull = <2>;
 265                                         lantiq,output = <1>;
 266                                 };
 267                         };
 268
 269                         gphy1_led1_pins: gphy1-led1 {
 270                                 mux {
 271                                         lantiq,groups = "gphy1 led1";
 272                                         lantiq,function = "gphy";
 273                                         lantiq,open-drain = <0>;
 274                                         lantiq,pull = <2>;
 275                                         lantiq,output = <1>;
 276                                 };
 277                         };
 278
 279                         gphy1_led2_pins: gphy1-led2 {
 280                                 mux {
 281                                         lantiq,groups = "gphy1 led2";
 282                                         lantiq,function = "gphy";
 283                                         lantiq,open-drain = <0>;
 284                                         lantiq,pull = <2>;
 285                                         lantiq,output = <1>;
 286                                 };
 287                         };
 288
 289                         mdio_pins: mdio {
 290                                 mux {
 291                                         lantiq,groups = "mdio";
 292                                         lantiq,function = "mdio";
 293                                 };
 294                         };
 295
 296                         nand_pins: nand {
 297                                 mux-0 {
 298                                         lantiq,groups = "nand cle", "nand ale",
 299                                                         "nand rd";
 300                                         lantiq,function = "ebu";
 301                                         lantiq,output = <1>;
 302                                         lantiq,open-drain = <0>;
 303                                         lantiq,pull = <0>;
 304                                 };
 305                                 mux-1 {
 306                                         lantiq,groups = "nand rdy";
 307                                         lantiq,function = "ebu";
 308                                         lantiq,output = <0>;
 309                                         lantiq,pull = <2>;
 310                                 };
 311                         };
 312
 313                         nand_cs1_pins: nand-cs1 {
 314                                 mux {
 315                                         lantiq,groups = "nand cs1";
 316                                         lantiq,function = "ebu";
 317                                         lantiq,open-drain = <0>;
 318                                         lantiq,pull = <0>;
 319                                 };
 320                         };
 321
 322                         pci_gnt1_pins: pci-gnt1 {
 323                                 mux {
 324                                         lantiq,groups = "gnt1";
 325                                         lantiq,function = "pci";
 326                                         lantiq,output = <1>;
 327                                         lantiq,open-drain = <0>;
 328                                         lantiq,pull = <0>;
 329                                 };
 330                         };
 331
 332                         pci_req1_pins: pci-req1 {
 333                                 mux {
 334                                         lantiq,groups = "req1";
 335                                         lantiq,function = "pci";
 336                                         lantiq,output = <0>;
 337                                         lantiq,open-drain = <1>;
 338                                         lantiq,pull = <2>;
 339                                 };
 340                         };
 341
 342                         spi_pins: spi {
 343                                 mux-0 {
 344                                         lantiq,groups = "spi_di";
 345                                         lantiq,function = "spi";
 346                                 };
 347                                 mux-1 {
 348                                         lantiq,groups = "spi_do", "spi_clk";
 349                                         lantiq,function = "spi";
 350                                         lantiq,output = <1>;
 351                                 };
 352                         };
 353
 354                         spi_cs4_pins: spi-cs4 {
 355                                 mux {
 356                                         lantiq,groups = "spi_cs4";
 357                                         lantiq,function = "spi";
 358                                         lantiq,output = <1>;
 359                                 };
 360                         };
 361
 362                         stp_pins: stp {
 363                                 mux {
 364                                         lantiq,groups = "stp";
 365                                         lantiq,function = "stp";
 366                                         lantiq,pull = <0>;
 367                                         lantiq,open-drain = <0>;
 368                                         lantiq,output = <1>;
 369                                 };
 370                         };
 371                 };
 372
 373                 stp: stp@e100bb0 {
 374                         status = "disabled";
 375                         compatible = "lantiq,gpio-stp-xway";
 376                         reg = <0xe100bb0 0x40>;
 377                         #gpio-cells = <2>;
 378                         gpio-controller;
 379
 380                         pinctrl-0 = <&stp_pins>;
 381                         pinctrl-names = "default";
 382
 383                         lantiq,shadow = <0xffffff>;
 384                         lantiq,groups = <0x7>;
 385                         lantiq,dsl = <0x0>;
 386                         lantiq,phy1 = <0x0>;
 387                         lantiq,phy2 = <0x0>;
 388                 };
 389
 390                 asc1: serial@e100c00 {
 391                         compatible = "lantiq,asc";
 392                         reg = <0xe100c00 0x400>;
 393                         interrupt-parent = <&icu0>;
 394                         interrupts = <112 113 114>;
 395                 };
 396
 397                 deu@e103100 {
 398                         compatible = "lantiq,deu-xrx200";
 399                         reg = <0xe103100 0xf00>;
 400                 };
 401
 402                 dma0: dma@e104100 {
 403                         compatible = "lantiq,dma-xway";
 404                         reg = <0xe104100 0x800>;
 405                 };
 406
 407                 ebu0: ebu@e105300 {
 408                         compatible = "lantiq,ebu-xway";
 409                         reg = <0xe105300 0x100>;
 410                 };
 411
 412                 usb0: usb@e101000 {
 413                         #address-cells = <1>;
 414                         #size-cells = <0>;
 415                         status = "disabled";
 416                         compatible = "lantiq,xrx200-usb";
 417                         reg = <0xe101000 0x1000
 418                                 0xe120000 0x3f000>;
 419                         interrupt-parent = <&icu0>;
 420                         interrupts = <62 91>;
 421                         dr_mode = "host";
 422                         phys = <&usb_phy0>;
 423                         phy-names = "usb2-phy";
 424
 425                         ehci_port1: port@1 {
 426                                 reg = <1>;
 427                                 #trigger-source-cells = <0>;
 428                         };
 429                 };
 430
 431                 usb1: usb@e106000 {
 432                         #address-cells = <1>;
 433                         #size-cells = <0>;
 434                         status = "disabled";
 435                         compatible = "lantiq,xrx200-usb";
 436                         reg = <0xe106000 0x1000>;
 437                         interrupt-parent = <&icu0>;
 438                         interrupts = <91>;
 439                         dr_mode = "host";
 440                         phys = <&usb_phy1>;
 441                         phy-names = "usb2-phy";
 442
 443                         ehci_port2: port@1 {
 444                                 reg = <1>;
 445                                 #trigger-source-cells = <0>;
 446                         };
 447                 };
 448
 449                 eth0: eth@e108000 {
 450                         #address-cells = <1>;
 451                         #size-cells = <0>;
 452                         compatible = "lantiq,xrx200-net";
 453                         reg = < 0xe108000 0x3000 /* switch */
 454                                 0xe10b100 0x70 /* mdio */
 455                                 0xe10b1d8 0x30 /* mii */
 456                                 0xe10b308 0x30 /* pmac */
 457                         >;
 458                         interrupt-parent = <&icu0>;
 459                         interrupts = <75 73 72>;
 460                         resets = <&reset0 21 16>, <&reset0 8 8>;
 461                         reset-names = "switch", "ppe";
 462                         lantiq,phys = <&gphy0>, <&gphy1>;
 463                         pinctrl-0 = <&mdio_pins>;
 464                         pinctrl-names = "default";
 465                 };
 466
 467                 mei@e116000 {
 468                         compatible = "lantiq,mei-xrx200";
 469                         reg = <0xe116000 0x9c>;
 470                         interrupt-parent = <&icu0>;
 471                         interrupts = <63>;
 472                 };
 473
 474                 ppe@e234000 {
 475                         compatible = "lantiq,ppe-xrx200";
 476                         reg = <0xe234000 0x3ffd>;
 477                         interrupt-parent = <&icu0>;
 478                         interrupts = <96>;
 479                         resets = <&reset0 3 3>, <&reset0 11 11>, <&reset0 23 23>;
 480                         reset-names = "dsp", "dfe", "tc";
 481                 };
 482
 483                 pcie0: pcie@d900000 {
 484                         compatible = "lantiq,pcie-xrx200";
 485
 486                         #interrupt-cells = <1>;
 487                         #size-cells = <2>;
 488                         #address-cells = <3>;
 489
 490                         reg = <0xd900000 0x1000>;
 491
 492                         interrupt-parent = <&icu0>;
 493                         interrupts = <161 144>;
 494
 495                         phys = <&pcie0_phy LANTIQ_PCIE_PHY_MODE_36MHZ>;
 496                         phy-names = "pcie";
 497
 498                         resets = <&reset0 22 22>;
 499
 500                         lantiq,rcu = <&rcu0>;
 501
 502                         device_type = "pci";
 503
 504                         gpio-reset = <&gpio 38 GPIO_ACTIVE_HIGH>;
 505                 };
 506
 507                 pci0: pci@e105400 {
 508                         status = "disabled";
 509
 510                         #address-cells = <3>;
 511                         #size-cells = <2>;
 512                         #interrupt-cells = <1>;
 513                         compatible = "lantiq,pci-xway";
 514                         bus-range = <0x0 0x0>;
 515                         ranges = <0x2000000 0 0x8000000 0x8000000 0 0x2000000   /* pci memory */
 516                                 0x1000000 0 0x00000000 0xae00000 0 0x200000>; /* io space */
 517                         reg = <0x7000000 0x8000         /* config space */
 518                                 0xe105400 0x400>;       /* pci bridge */
 519                         lantiq,bus-clock = <33333333>;
 520                         interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 521                         interrupt-map = <0x7000 0 0 1 &icu0 30 1>; /* slot 14, irq 30 */
 522                         req-mask = <0x1>; /* GNT1 */
 523                 };
 524         };
 525
 526         vdsl {
 527                 compatible = "lantiq,vdsl-vrx200";
 528         };
 529 };