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[openwrt/openwrt.git] / target / linux / lantiq / patches-4.1 / 0042-USB-DWC2-big-endian-support.patch
1 --- a/drivers/usb/dwc2/core.c
2 +++ b/drivers/usb/dwc2/core.c
3 @@ -67,10 +67,10 @@ static void dwc2_enable_common_interrupt
4 u32 intmsk;
5
6 /* Clear any pending OTG Interrupts */
7 - writel(0xffffffff, hsotg->regs + GOTGINT);
8 + dwc2_writel(0xffffffff, hsotg->regs + GOTGINT);
9
10 /* Clear any pending interrupts */
11 - writel(0xffffffff, hsotg->regs + GINTSTS);
12 + dwc2_writel(0xffffffff, hsotg->regs + GINTSTS);
13
14 /* Enable the interrupts in the GINTMSK */
15 intmsk = GINTSTS_MODEMIS | GINTSTS_OTGINT;
16 @@ -81,7 +81,7 @@ static void dwc2_enable_common_interrupt
17 intmsk |= GINTSTS_CONIDSTSCHNG | GINTSTS_WKUPINT | GINTSTS_USBSUSP |
18 GINTSTS_SESSREQINT;
19
20 - writel(intmsk, hsotg->regs + GINTMSK);
21 + dwc2_writel(intmsk, hsotg->regs + GINTMSK);
22 }
23
24 /*
25 @@ -104,10 +104,10 @@ static void dwc2_init_fs_ls_pclk_sel(str
26 }
27
28 dev_dbg(hsotg->dev, "Initializing HCFG.FSLSPClkSel to %08x\n", val);
29 - hcfg = readl(hsotg->regs + HCFG);
30 + hcfg = dwc2_readl(hsotg->regs + HCFG);
31 hcfg &= ~HCFG_FSLSPCLKSEL_MASK;
32 hcfg |= val << HCFG_FSLSPCLKSEL_SHIFT;
33 - writel(hcfg, hsotg->regs + HCFG);
34 + dwc2_writel(hcfg, hsotg->regs + HCFG);
35 }
36
37 /*
38 @@ -125,7 +125,7 @@ static int dwc2_core_reset(struct dwc2_h
39 /* Wait for AHB master IDLE state */
40 do {
41 usleep_range(20000, 40000);
42 - greset = readl(hsotg->regs + GRSTCTL);
43 + greset = dwc2_readl(hsotg->regs + GRSTCTL);
44 if (++count > 50) {
45 dev_warn(hsotg->dev,
46 "%s() HANG! AHB Idle GRSTCTL=%0x\n",
47 @@ -137,10 +137,10 @@ static int dwc2_core_reset(struct dwc2_h
48 /* Core Soft Reset */
49 count = 0;
50 greset |= GRSTCTL_CSFTRST;
51 - writel(greset, hsotg->regs + GRSTCTL);
52 + dwc2_writel(greset, hsotg->regs + GRSTCTL);
53 do {
54 usleep_range(20000, 40000);
55 - greset = readl(hsotg->regs + GRSTCTL);
56 + greset = dwc2_readl(hsotg->regs + GRSTCTL);
57 if (++count > 50) {
58 dev_warn(hsotg->dev,
59 "%s() HANG! Soft Reset GRSTCTL=%0x\n",
60 @@ -150,20 +150,20 @@ static int dwc2_core_reset(struct dwc2_h
61 } while (greset & GRSTCTL_CSFTRST);
62
63 if (hsotg->dr_mode == USB_DR_MODE_HOST) {
64 - gusbcfg = readl(hsotg->regs + GUSBCFG);
65 + gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
66 gusbcfg &= ~GUSBCFG_FORCEDEVMODE;
67 gusbcfg |= GUSBCFG_FORCEHOSTMODE;
68 - writel(gusbcfg, hsotg->regs + GUSBCFG);
69 + dwc2_writel(gusbcfg, hsotg->regs + GUSBCFG);
70 } else if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) {
71 - gusbcfg = readl(hsotg->regs + GUSBCFG);
72 + gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
73 gusbcfg &= ~GUSBCFG_FORCEHOSTMODE;
74 gusbcfg |= GUSBCFG_FORCEDEVMODE;
75 - writel(gusbcfg, hsotg->regs + GUSBCFG);
76 + dwc2_writel(gusbcfg, hsotg->regs + GUSBCFG);
77 } else if (hsotg->dr_mode == USB_DR_MODE_OTG) {
78 - gusbcfg = readl(hsotg->regs + GUSBCFG);
79 + gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
80 gusbcfg &= ~GUSBCFG_FORCEHOSTMODE;
81 gusbcfg &= ~GUSBCFG_FORCEDEVMODE;
82 - writel(gusbcfg, hsotg->regs + GUSBCFG);
83 + dwc2_writel(gusbcfg, hsotg->regs + GUSBCFG);
84 }
85
86 /*
87 @@ -186,9 +186,9 @@ static int dwc2_fs_phy_init(struct dwc2_
88 */
89 if (select_phy) {
90 dev_dbg(hsotg->dev, "FS PHY selected\n");
91 - usbcfg = readl(hsotg->regs + GUSBCFG);
92 + usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
93 usbcfg |= GUSBCFG_PHYSEL;
94 - writel(usbcfg, hsotg->regs + GUSBCFG);
95 + dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
96
97 /* Reset after a PHY select */
98 retval = dwc2_core_reset(hsotg);
99 @@ -211,18 +211,18 @@ static int dwc2_fs_phy_init(struct dwc2_
100 dev_dbg(hsotg->dev, "FS PHY enabling I2C\n");
101
102 /* Program GUSBCFG.OtgUtmiFsSel to I2C */
103 - usbcfg = readl(hsotg->regs + GUSBCFG);
104 + usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
105 usbcfg |= GUSBCFG_OTG_UTMI_FS_SEL;
106 - writel(usbcfg, hsotg->regs + GUSBCFG);
107 + dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
108
109 /* Program GI2CCTL.I2CEn */
110 - i2cctl = readl(hsotg->regs + GI2CCTL);
111 + i2cctl = dwc2_readl(hsotg->regs + GI2CCTL);
112 i2cctl &= ~GI2CCTL_I2CDEVADDR_MASK;
113 i2cctl |= 1 << GI2CCTL_I2CDEVADDR_SHIFT;
114 i2cctl &= ~GI2CCTL_I2CEN;
115 - writel(i2cctl, hsotg->regs + GI2CCTL);
116 + dwc2_writel(i2cctl, hsotg->regs + GI2CCTL);
117 i2cctl |= GI2CCTL_I2CEN;
118 - writel(i2cctl, hsotg->regs + GI2CCTL);
119 + dwc2_writel(i2cctl, hsotg->regs + GI2CCTL);
120 }
121
122 return retval;
123 @@ -236,7 +236,7 @@ static int dwc2_hs_phy_init(struct dwc2_
124 if (!select_phy)
125 return 0;
126
127 - usbcfg = readl(hsotg->regs + GUSBCFG);
128 + usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
129
130 /*
131 * HS PHY parameters. These parameters are preserved during soft reset
132 @@ -264,7 +264,7 @@ static int dwc2_hs_phy_init(struct dwc2_
133 break;
134 }
135
136 - writel(usbcfg, hsotg->regs + GUSBCFG);
137 + dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
138
139 /* Reset after setting the PHY parameters */
140 retval = dwc2_core_reset(hsotg);
141 @@ -299,15 +299,15 @@ static int dwc2_phy_init(struct dwc2_hso
142 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED &&
143 hsotg->core_params->ulpi_fs_ls > 0) {
144 dev_dbg(hsotg->dev, "Setting ULPI FSLS\n");
145 - usbcfg = readl(hsotg->regs + GUSBCFG);
146 + usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
147 usbcfg |= GUSBCFG_ULPI_FS_LS;
148 usbcfg |= GUSBCFG_ULPI_CLK_SUSP_M;
149 - writel(usbcfg, hsotg->regs + GUSBCFG);
150 + dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
151 } else {
152 - usbcfg = readl(hsotg->regs + GUSBCFG);
153 + usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
154 usbcfg &= ~GUSBCFG_ULPI_FS_LS;
155 usbcfg &= ~GUSBCFG_ULPI_CLK_SUSP_M;
156 - writel(usbcfg, hsotg->regs + GUSBCFG);
157 + dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
158 }
159
160 return retval;
161 @@ -315,7 +315,7 @@ static int dwc2_phy_init(struct dwc2_hso
162
163 static int dwc2_gahbcfg_init(struct dwc2_hsotg *hsotg)
164 {
165 - u32 ahbcfg = readl(hsotg->regs + GAHBCFG);
166 + u32 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG);
167
168 switch (hsotg->hw_params.arch) {
169 case GHWCFG2_EXT_DMA_ARCH:
170 @@ -354,7 +354,7 @@ static int dwc2_gahbcfg_init(struct dwc2
171 if (hsotg->core_params->dma_enable > 0)
172 ahbcfg |= GAHBCFG_DMA_EN;
173
174 - writel(ahbcfg, hsotg->regs + GAHBCFG);
175 + dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG);
176
177 return 0;
178 }
179 @@ -363,7 +363,7 @@ static void dwc2_gusbcfg_init(struct dwc
180 {
181 u32 usbcfg;
182
183 - usbcfg = readl(hsotg->regs + GUSBCFG);
184 + usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
185 usbcfg &= ~(GUSBCFG_HNPCAP | GUSBCFG_SRPCAP);
186
187 switch (hsotg->hw_params.op_mode) {
188 @@ -391,7 +391,7 @@ static void dwc2_gusbcfg_init(struct dwc
189 break;
190 }
191
192 - writel(usbcfg, hsotg->regs + GUSBCFG);
193 + dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
194 }
195
196 /**
197 @@ -409,7 +409,7 @@ int dwc2_core_init(struct dwc2_hsotg *hs
198
199 dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg);
200
201 - usbcfg = readl(hsotg->regs + GUSBCFG);
202 + usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
203
204 /* Set ULPI External VBUS bit if needed */
205 usbcfg &= ~GUSBCFG_ULPI_EXT_VBUS_DRV;
206 @@ -422,7 +422,7 @@ int dwc2_core_init(struct dwc2_hsotg *hs
207 if (hsotg->core_params->ts_dline > 0)
208 usbcfg |= GUSBCFG_TERMSELDLPULSE;
209
210 - writel(usbcfg, hsotg->regs + GUSBCFG);
211 + dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
212
213 /* Reset the Controller */
214 retval = dwc2_core_reset(hsotg);
215 @@ -448,11 +448,11 @@ int dwc2_core_init(struct dwc2_hsotg *hs
216 dwc2_gusbcfg_init(hsotg);
217
218 /* Program the GOTGCTL register */
219 - otgctl = readl(hsotg->regs + GOTGCTL);
220 + otgctl = dwc2_readl(hsotg->regs + GOTGCTL);
221 otgctl &= ~GOTGCTL_OTGVER;
222 if (hsotg->core_params->otg_ver > 0)
223 otgctl |= GOTGCTL_OTGVER;
224 - writel(otgctl, hsotg->regs + GOTGCTL);
225 + dwc2_writel(otgctl, hsotg->regs + GOTGCTL);
226 dev_dbg(hsotg->dev, "OTG VER PARAM: %d\n", hsotg->core_params->otg_ver);
227
228 /* Clear the SRP success bit for FS-I2c */
229 @@ -488,16 +488,16 @@ void dwc2_enable_host_interrupts(struct
230 dev_dbg(hsotg->dev, "%s()\n", __func__);
231
232 /* Disable all interrupts */
233 - writel(0, hsotg->regs + GINTMSK);
234 - writel(0, hsotg->regs + HAINTMSK);
235 + dwc2_writel(0, hsotg->regs + GINTMSK);
236 + dwc2_writel(0, hsotg->regs + HAINTMSK);
237
238 /* Enable the common interrupts */
239 dwc2_enable_common_interrupts(hsotg);
240
241 /* Enable host mode interrupts without disturbing common interrupts */
242 - intmsk = readl(hsotg->regs + GINTMSK);
243 + intmsk = dwc2_readl(hsotg->regs + GINTMSK);
244 intmsk |= GINTSTS_DISCONNINT | GINTSTS_PRTINT | GINTSTS_HCHINT;
245 - writel(intmsk, hsotg->regs + GINTMSK);
246 + dwc2_writel(intmsk, hsotg->regs + GINTMSK);
247 }
248
249 /**
250 @@ -507,12 +507,12 @@ void dwc2_enable_host_interrupts(struct
251 */
252 void dwc2_disable_host_interrupts(struct dwc2_hsotg *hsotg)
253 {
254 - u32 intmsk = readl(hsotg->regs + GINTMSK);
255 + u32 intmsk = dwc2_readl(hsotg->regs + GINTMSK);
256
257 /* Disable host mode interrupts without disturbing common interrupts */
258 intmsk &= ~(GINTSTS_SOF | GINTSTS_PRTINT | GINTSTS_HCHINT |
259 GINTSTS_PTXFEMP | GINTSTS_NPTXFEMP);
260 - writel(intmsk, hsotg->regs + GINTMSK);
261 + dwc2_writel(intmsk, hsotg->regs + GINTMSK);
262 }
263
264 /*
265 @@ -592,36 +592,36 @@ static void dwc2_config_fifos(struct dwc
266 dwc2_calculate_dynamic_fifo(hsotg);
267
268 /* Rx FIFO */
269 - grxfsiz = readl(hsotg->regs + GRXFSIZ);
270 + grxfsiz = dwc2_readl(hsotg->regs + GRXFSIZ);
271 dev_dbg(hsotg->dev, "initial grxfsiz=%08x\n", grxfsiz);
272 grxfsiz &= ~GRXFSIZ_DEPTH_MASK;
273 grxfsiz |= params->host_rx_fifo_size <<
274 GRXFSIZ_DEPTH_SHIFT & GRXFSIZ_DEPTH_MASK;
275 - writel(grxfsiz, hsotg->regs + GRXFSIZ);
276 - dev_dbg(hsotg->dev, "new grxfsiz=%08x\n", readl(hsotg->regs + GRXFSIZ));
277 + dwc2_writel(grxfsiz, hsotg->regs + GRXFSIZ);
278 + dev_dbg(hsotg->dev, "new grxfsiz=%08x\n", dwc2_readl(hsotg->regs + GRXFSIZ));
279
280 /* Non-periodic Tx FIFO */
281 dev_dbg(hsotg->dev, "initial gnptxfsiz=%08x\n",
282 - readl(hsotg->regs + GNPTXFSIZ));
283 + dwc2_readl(hsotg->regs + GNPTXFSIZ));
284 nptxfsiz = params->host_nperio_tx_fifo_size <<
285 FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK;
286 nptxfsiz |= params->host_rx_fifo_size <<
287 FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK;
288 - writel(nptxfsiz, hsotg->regs + GNPTXFSIZ);
289 + dwc2_writel(nptxfsiz, hsotg->regs + GNPTXFSIZ);
290 dev_dbg(hsotg->dev, "new gnptxfsiz=%08x\n",
291 - readl(hsotg->regs + GNPTXFSIZ));
292 + dwc2_readl(hsotg->regs + GNPTXFSIZ));
293
294 /* Periodic Tx FIFO */
295 dev_dbg(hsotg->dev, "initial hptxfsiz=%08x\n",
296 - readl(hsotg->regs + HPTXFSIZ));
297 + dwc2_readl(hsotg->regs + HPTXFSIZ));
298 hptxfsiz = params->host_perio_tx_fifo_size <<
299 FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK;
300 hptxfsiz |= (params->host_rx_fifo_size +
301 params->host_nperio_tx_fifo_size) <<
302 FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK;
303 - writel(hptxfsiz, hsotg->regs + HPTXFSIZ);
304 + dwc2_writel(hptxfsiz, hsotg->regs + HPTXFSIZ);
305 dev_dbg(hsotg->dev, "new hptxfsiz=%08x\n",
306 - readl(hsotg->regs + HPTXFSIZ));
307 + dwc2_readl(hsotg->regs + HPTXFSIZ));
308
309 if (hsotg->core_params->en_multiple_tx_fifo > 0 &&
310 hsotg->hw_params.snpsid <= DWC2_CORE_REV_2_94a) {
311 @@ -629,14 +629,14 @@ static void dwc2_config_fifos(struct dwc
312 * Global DFIFOCFG calculation for Host mode -
313 * include RxFIFO, NPTXFIFO and HPTXFIFO
314 */
315 - dfifocfg = readl(hsotg->regs + GDFIFOCFG);
316 + dfifocfg = dwc2_readl(hsotg->regs + GDFIFOCFG);
317 dfifocfg &= ~GDFIFOCFG_EPINFOBASE_MASK;
318 dfifocfg |= (params->host_rx_fifo_size +
319 params->host_nperio_tx_fifo_size +
320 params->host_perio_tx_fifo_size) <<
321 GDFIFOCFG_EPINFOBASE_SHIFT &
322 GDFIFOCFG_EPINFOBASE_MASK;
323 - writel(dfifocfg, hsotg->regs + GDFIFOCFG);
324 + dwc2_writel(dfifocfg, hsotg->regs + GDFIFOCFG);
325 }
326 }
327
328 @@ -657,14 +657,14 @@ void dwc2_core_host_init(struct dwc2_hso
329 dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg);
330
331 /* Restart the Phy Clock */
332 - writel(0, hsotg->regs + PCGCTL);
333 + dwc2_writel(0, hsotg->regs + PCGCTL);
334
335 /* Initialize Host Configuration Register */
336 dwc2_init_fs_ls_pclk_sel(hsotg);
337 if (hsotg->core_params->speed == DWC2_SPEED_PARAM_FULL) {
338 - hcfg = readl(hsotg->regs + HCFG);
339 + hcfg = dwc2_readl(hsotg->regs + HCFG);
340 hcfg |= HCFG_FSLSSUPP;
341 - writel(hcfg, hsotg->regs + HCFG);
342 + dwc2_writel(hcfg, hsotg->regs + HCFG);
343 }
344
345 /*
346 @@ -673,9 +673,9 @@ void dwc2_core_host_init(struct dwc2_hso
347 * and its value must not be changed during runtime.
348 */
349 if (hsotg->core_params->reload_ctl > 0) {
350 - hfir = readl(hsotg->regs + HFIR);
351 + hfir = dwc2_readl(hsotg->regs + HFIR);
352 hfir |= HFIR_RLDCTRL;
353 - writel(hfir, hsotg->regs + HFIR);
354 + dwc2_writel(hfir, hsotg->regs + HFIR);
355 }
356
357 if (hsotg->core_params->dma_desc_enable > 0) {
358 @@ -691,9 +691,9 @@ void dwc2_core_host_init(struct dwc2_hso
359 "falling back to buffer DMA mode.\n");
360 hsotg->core_params->dma_desc_enable = 0;
361 } else {
362 - hcfg = readl(hsotg->regs + HCFG);
363 + hcfg = dwc2_readl(hsotg->regs + HCFG);
364 hcfg |= HCFG_DESCDMA;
365 - writel(hcfg, hsotg->regs + HCFG);
366 + dwc2_writel(hcfg, hsotg->regs + HCFG);
367 }
368 }
369
370 @@ -702,18 +702,18 @@ void dwc2_core_host_init(struct dwc2_hso
371
372 /* TODO - check this */
373 /* Clear Host Set HNP Enable in the OTG Control Register */
374 - otgctl = readl(hsotg->regs + GOTGCTL);
375 + otgctl = dwc2_readl(hsotg->regs + GOTGCTL);
376 otgctl &= ~GOTGCTL_HSTSETHNPEN;
377 - writel(otgctl, hsotg->regs + GOTGCTL);
378 + dwc2_writel(otgctl, hsotg->regs + GOTGCTL);
379
380 /* Make sure the FIFOs are flushed */
381 dwc2_flush_tx_fifo(hsotg, 0x10 /* all TX FIFOs */);
382 dwc2_flush_rx_fifo(hsotg);
383
384 /* Clear Host Set HNP Enable in the OTG Control Register */
385 - otgctl = readl(hsotg->regs + GOTGCTL);
386 + otgctl = dwc2_readl(hsotg->regs + GOTGCTL);
387 otgctl &= ~GOTGCTL_HSTSETHNPEN;
388 - writel(otgctl, hsotg->regs + GOTGCTL);
389 + dwc2_writel(otgctl, hsotg->regs + GOTGCTL);
390
391 if (hsotg->core_params->dma_desc_enable <= 0) {
392 int num_channels, i;
393 @@ -722,25 +722,25 @@ void dwc2_core_host_init(struct dwc2_hso
394 /* Flush out any leftover queued requests */
395 num_channels = hsotg->core_params->host_channels;
396 for (i = 0; i < num_channels; i++) {
397 - hcchar = readl(hsotg->regs + HCCHAR(i));
398 + hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
399 hcchar &= ~HCCHAR_CHENA;
400 hcchar |= HCCHAR_CHDIS;
401 hcchar &= ~HCCHAR_EPDIR;
402 - writel(hcchar, hsotg->regs + HCCHAR(i));
403 + dwc2_writel(hcchar, hsotg->regs + HCCHAR(i));
404 }
405
406 /* Halt all channels to put them into a known state */
407 for (i = 0; i < num_channels; i++) {
408 int count = 0;
409
410 - hcchar = readl(hsotg->regs + HCCHAR(i));
411 + hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
412 hcchar |= HCCHAR_CHENA | HCCHAR_CHDIS;
413 hcchar &= ~HCCHAR_EPDIR;
414 - writel(hcchar, hsotg->regs + HCCHAR(i));
415 + dwc2_writel(hcchar, hsotg->regs + HCCHAR(i));
416 dev_dbg(hsotg->dev, "%s: Halt channel %d\n",
417 __func__, i);
418 do {
419 - hcchar = readl(hsotg->regs + HCCHAR(i));
420 + hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
421 if (++count > 1000) {
422 dev_err(hsotg->dev,
423 "Unable to clear enable on channel %d\n",
424 @@ -761,7 +761,7 @@ void dwc2_core_host_init(struct dwc2_hso
425 !!(hprt0 & HPRT0_PWR));
426 if (!(hprt0 & HPRT0_PWR)) {
427 hprt0 |= HPRT0_PWR;
428 - writel(hprt0, hsotg->regs + HPRT0);
429 + dwc2_writel(hprt0, hsotg->regs + HPRT0);
430 }
431 }
432
433 @@ -841,7 +841,7 @@ static void dwc2_hc_enable_slave_ints(st
434 break;
435 }
436
437 - writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num));
438 + dwc2_writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num));
439 if (dbg_hc(chan))
440 dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk);
441 }
442 @@ -878,7 +878,7 @@ static void dwc2_hc_enable_dma_ints(stru
443 }
444 }
445
446 - writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num));
447 + dwc2_writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num));
448 if (dbg_hc(chan))
449 dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk);
450 }
451 @@ -899,16 +899,16 @@ static void dwc2_hc_enable_ints(struct d
452 }
453
454 /* Enable the top level host channel interrupt */
455 - intmsk = readl(hsotg->regs + HAINTMSK);
456 + intmsk = dwc2_readl(hsotg->regs + HAINTMSK);
457 intmsk |= 1 << chan->hc_num;
458 - writel(intmsk, hsotg->regs + HAINTMSK);
459 + dwc2_writel(intmsk, hsotg->regs + HAINTMSK);
460 if (dbg_hc(chan))
461 dev_vdbg(hsotg->dev, "set HAINTMSK to %08x\n", intmsk);
462
463 /* Make sure host channel interrupts are enabled */
464 - intmsk = readl(hsotg->regs + GINTMSK);
465 + intmsk = dwc2_readl(hsotg->regs + GINTMSK);
466 intmsk |= GINTSTS_HCHINT;
467 - writel(intmsk, hsotg->regs + GINTMSK);
468 + dwc2_writel(intmsk, hsotg->regs + GINTMSK);
469 if (dbg_hc(chan))
470 dev_vdbg(hsotg->dev, "set GINTMSK to %08x\n", intmsk);
471 }
472 @@ -937,7 +937,7 @@ void dwc2_hc_init(struct dwc2_hsotg *hso
473 /* Clear old interrupt conditions for this host channel */
474 hcintmsk = 0xffffffff;
475 hcintmsk &= ~HCINTMSK_RESERVED14_31;
476 - writel(hcintmsk, hsotg->regs + HCINT(hc_num));
477 + dwc2_writel(hcintmsk, hsotg->regs + HCINT(hc_num));
478
479 /* Enable channel interrupts required for this transfer */
480 dwc2_hc_enable_ints(hsotg, chan);
481 @@ -954,7 +954,7 @@ void dwc2_hc_init(struct dwc2_hsotg *hso
482 hcchar |= HCCHAR_LSPDDEV;
483 hcchar |= chan->ep_type << HCCHAR_EPTYPE_SHIFT & HCCHAR_EPTYPE_MASK;
484 hcchar |= chan->max_packet << HCCHAR_MPS_SHIFT & HCCHAR_MPS_MASK;
485 - writel(hcchar, hsotg->regs + HCCHAR(hc_num));
486 + dwc2_writel(hcchar, hsotg->regs + HCCHAR(hc_num));
487 if (dbg_hc(chan)) {
488 dev_vdbg(hsotg->dev, "set HCCHAR(%d) to %08x\n",
489 hc_num, hcchar);
490 @@ -1008,7 +1008,7 @@ void dwc2_hc_init(struct dwc2_hsotg *hso
491 }
492 }
493
494 - writel(hcsplt, hsotg->regs + HCSPLT(hc_num));
495 + dwc2_writel(hcsplt, hsotg->regs + HCSPLT(hc_num));
496 }
497
498 /**
499 @@ -1060,14 +1060,14 @@ void dwc2_hc_halt(struct dwc2_hsotg *hso
500 u32 hcintmsk = HCINTMSK_CHHLTD;
501
502 dev_vdbg(hsotg->dev, "dequeue/error\n");
503 - writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num));
504 + dwc2_writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num));
505
506 /*
507 * Make sure no other interrupts besides halt are currently
508 * pending. Handling another interrupt could cause a crash due
509 * to the QTD and QH state.
510 */
511 - writel(~hcintmsk, hsotg->regs + HCINT(chan->hc_num));
512 + dwc2_writel(~hcintmsk, hsotg->regs + HCINT(chan->hc_num));
513
514 /*
515 * Make sure the halt status is set to URB_DEQUEUE or AHB_ERR
516 @@ -1076,7 +1076,7 @@ void dwc2_hc_halt(struct dwc2_hsotg *hso
517 */
518 chan->halt_status = halt_status;
519
520 - hcchar = readl(hsotg->regs + HCCHAR(chan->hc_num));
521 + hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
522 if (!(hcchar & HCCHAR_CHENA)) {
523 /*
524 * The channel is either already halted or it hasn't
525 @@ -1104,7 +1104,7 @@ void dwc2_hc_halt(struct dwc2_hsotg *hso
526 return;
527 }
528
529 - hcchar = readl(hsotg->regs + HCCHAR(chan->hc_num));
530 + hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
531
532 /* No need to set the bit in DDMA for disabling the channel */
533 /* TODO check it everywhere channel is disabled */
534 @@ -1127,7 +1127,7 @@ void dwc2_hc_halt(struct dwc2_hsotg *hso
535 if (chan->ep_type == USB_ENDPOINT_XFER_CONTROL ||
536 chan->ep_type == USB_ENDPOINT_XFER_BULK) {
537 dev_vdbg(hsotg->dev, "control/bulk\n");
538 - nptxsts = readl(hsotg->regs + GNPTXSTS);
539 + nptxsts = dwc2_readl(hsotg->regs + GNPTXSTS);
540 if ((nptxsts & TXSTS_QSPCAVAIL_MASK) == 0) {
541 dev_vdbg(hsotg->dev, "Disabling channel\n");
542 hcchar &= ~HCCHAR_CHENA;
543 @@ -1135,7 +1135,7 @@ void dwc2_hc_halt(struct dwc2_hsotg *hso
544 } else {
545 if (dbg_perio())
546 dev_vdbg(hsotg->dev, "isoc/intr\n");
547 - hptxsts = readl(hsotg->regs + HPTXSTS);
548 + hptxsts = dwc2_readl(hsotg->regs + HPTXSTS);
549 if ((hptxsts & TXSTS_QSPCAVAIL_MASK) == 0 ||
550 hsotg->queuing_high_bandwidth) {
551 if (dbg_perio())
552 @@ -1148,7 +1148,7 @@ void dwc2_hc_halt(struct dwc2_hsotg *hso
553 dev_vdbg(hsotg->dev, "DMA enabled\n");
554 }
555
556 - writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
557 + dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
558 chan->halt_status = halt_status;
559
560 if (hcchar & HCCHAR_CHENA) {
561 @@ -1195,10 +1195,10 @@ void dwc2_hc_cleanup(struct dwc2_hsotg *
562 * Clear channel interrupt enables and any unhandled channel interrupt
563 * conditions
564 */
565 - writel(0, hsotg->regs + HCINTMSK(chan->hc_num));
566 + dwc2_writel(0, hsotg->regs + HCINTMSK(chan->hc_num));
567 hcintmsk = 0xffffffff;
568 hcintmsk &= ~HCINTMSK_RESERVED14_31;
569 - writel(hcintmsk, hsotg->regs + HCINT(chan->hc_num));
570 + dwc2_writel(hcintmsk, hsotg->regs + HCINT(chan->hc_num));
571 }
572
573 /**
574 @@ -1284,13 +1284,13 @@ static void dwc2_hc_write_packet(struct
575 if (((unsigned long)data_buf & 0x3) == 0) {
576 /* xfer_buf is DWORD aligned */
577 for (i = 0; i < dword_count; i++, data_buf++)
578 - writel(*data_buf, data_fifo);
579 + dwc2_writel(*data_buf, data_fifo);
580 } else {
581 /* xfer_buf is not DWORD aligned */
582 for (i = 0; i < dword_count; i++, data_buf++) {
583 u32 data = data_buf[0] | data_buf[1] << 8 |
584 data_buf[2] << 16 | data_buf[3] << 24;
585 - writel(data, data_fifo);
586 + dwc2_writel(data, data_fifo);
587 }
588 }
589
590 @@ -1443,7 +1443,7 @@ void dwc2_hc_start_transfer(struct dwc2_
591 hctsiz |= num_packets << TSIZ_PKTCNT_SHIFT & TSIZ_PKTCNT_MASK;
592 hctsiz |= chan->data_pid_start << TSIZ_SC_MC_PID_SHIFT &
593 TSIZ_SC_MC_PID_MASK;
594 - writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num));
595 + dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num));
596 if (dbg_hc(chan)) {
597 dev_vdbg(hsotg->dev, "Wrote %08x to HCTSIZ(%d)\n",
598 hctsiz, chan->hc_num);
599 @@ -1471,7 +1471,7 @@ void dwc2_hc_start_transfer(struct dwc2_
600 } else {
601 dma_addr = chan->xfer_dma;
602 }
603 - writel((u32)dma_addr, hsotg->regs + HCDMA(chan->hc_num));
604 + dwc2_writel((u32)dma_addr, hsotg->regs + HCDMA(chan->hc_num));
605 if (dbg_hc(chan))
606 dev_vdbg(hsotg->dev, "Wrote %08lx to HCDMA(%d)\n",
607 (unsigned long)dma_addr, chan->hc_num);
608 @@ -1479,13 +1479,13 @@ void dwc2_hc_start_transfer(struct dwc2_
609
610 /* Start the split */
611 if (chan->do_split) {
612 - u32 hcsplt = readl(hsotg->regs + HCSPLT(chan->hc_num));
613 + u32 hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chan->hc_num));
614
615 hcsplt |= HCSPLT_SPLTENA;
616 - writel(hcsplt, hsotg->regs + HCSPLT(chan->hc_num));
617 + dwc2_writel(hcsplt, hsotg->regs + HCSPLT(chan->hc_num));
618 }
619
620 - hcchar = readl(hsotg->regs + HCCHAR(chan->hc_num));
621 + hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
622 hcchar &= ~HCCHAR_MULTICNT_MASK;
623 hcchar |= chan->multi_count << HCCHAR_MULTICNT_SHIFT &
624 HCCHAR_MULTICNT_MASK;
625 @@ -1505,7 +1505,7 @@ void dwc2_hc_start_transfer(struct dwc2_
626 (hcchar & HCCHAR_MULTICNT_MASK) >>
627 HCCHAR_MULTICNT_SHIFT);
628
629 - writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
630 + dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
631 if (dbg_hc(chan))
632 dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar,
633 chan->hc_num);
634 @@ -1564,18 +1564,18 @@ void dwc2_hc_start_transfer_ddma(struct
635 dev_vdbg(hsotg->dev, " NTD: %d\n", chan->ntd - 1);
636 }
637
638 - writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num));
639 + dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num));
640
641 hc_dma = (u32)chan->desc_list_addr & HCDMA_DMA_ADDR_MASK;
642
643 /* Always start from first descriptor */
644 hc_dma &= ~HCDMA_CTD_MASK;
645 - writel(hc_dma, hsotg->regs + HCDMA(chan->hc_num));
646 + dwc2_writel(hc_dma, hsotg->regs + HCDMA(chan->hc_num));
647 if (dbg_hc(chan))
648 dev_vdbg(hsotg->dev, "Wrote %08x to HCDMA(%d)\n",
649 hc_dma, chan->hc_num);
650
651 - hcchar = readl(hsotg->regs + HCCHAR(chan->hc_num));
652 + hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
653 hcchar &= ~HCCHAR_MULTICNT_MASK;
654 hcchar |= chan->multi_count << HCCHAR_MULTICNT_SHIFT &
655 HCCHAR_MULTICNT_MASK;
656 @@ -1594,7 +1594,7 @@ void dwc2_hc_start_transfer_ddma(struct
657 (hcchar & HCCHAR_MULTICNT_MASK) >>
658 HCCHAR_MULTICNT_SHIFT);
659
660 - writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
661 + dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
662 if (dbg_hc(chan))
663 dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar,
664 chan->hc_num);
665 @@ -1651,7 +1651,7 @@ int dwc2_hc_continue_transfer(struct dwc
666 * transfer completes, the extra requests for the channel will
667 * be flushed.
668 */
669 - u32 hcchar = readl(hsotg->regs + HCCHAR(chan->hc_num));
670 + u32 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
671
672 dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar);
673 hcchar |= HCCHAR_CHENA;
674 @@ -1659,7 +1659,7 @@ int dwc2_hc_continue_transfer(struct dwc
675 if (dbg_hc(chan))
676 dev_vdbg(hsotg->dev, " IN xfer: hcchar = 0x%08x\n",
677 hcchar);
678 - writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
679 + dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
680 chan->requests++;
681 return 1;
682 }
683 @@ -1669,7 +1669,7 @@ int dwc2_hc_continue_transfer(struct dwc
684 if (chan->xfer_count < chan->xfer_len) {
685 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
686 chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
687 - u32 hcchar = readl(hsotg->regs +
688 + u32 hcchar = dwc2_readl(hsotg->regs +
689 HCCHAR(chan->hc_num));
690
691 dwc2_hc_set_even_odd_frame(hsotg, chan,
692 @@ -1706,12 +1706,12 @@ void dwc2_hc_do_ping(struct dwc2_hsotg *
693
694 hctsiz = TSIZ_DOPNG;
695 hctsiz |= 1 << TSIZ_PKTCNT_SHIFT;
696 - writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num));
697 + dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num));
698
699 - hcchar = readl(hsotg->regs + HCCHAR(chan->hc_num));
700 + hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
701 hcchar |= HCCHAR_CHENA;
702 hcchar &= ~HCCHAR_CHDIS;
703 - writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
704 + dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
705 }
706
707 /**
708 @@ -1730,8 +1730,8 @@ u32 dwc2_calc_frame_interval(struct dwc2
709 u32 hprt0;
710 int clock = 60; /* default value */
711
712 - usbcfg = readl(hsotg->regs + GUSBCFG);
713 - hprt0 = readl(hsotg->regs + HPRT0);
714 + usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
715 + hprt0 = dwc2_readl(hsotg->regs + HPRT0);
716
717 if (!(usbcfg & GUSBCFG_PHYSEL) && (usbcfg & GUSBCFG_ULPI_UTMI_SEL) &&
718 !(usbcfg & GUSBCFG_PHYIF16))
719 @@ -1787,7 +1787,7 @@ void dwc2_read_packet(struct dwc2_hsotg
720 dev_vdbg(hsotg->dev, "%s(%p,%p,%d)\n", __func__, hsotg, dest, bytes);
721
722 for (i = 0; i < word_count; i++, data_buf++)
723 - *data_buf = readl(fifo);
724 + *data_buf = dwc2_readl(fifo);
725 }
726
727 /**
728 @@ -1807,56 +1807,56 @@ void dwc2_dump_host_registers(struct dwc
729 dev_dbg(hsotg->dev, "Host Global Registers\n");
730 addr = hsotg->regs + HCFG;
731 dev_dbg(hsotg->dev, "HCFG @0x%08lX : 0x%08X\n",
732 - (unsigned long)addr, readl(addr));
733 + (unsigned long)addr, dwc2_readl(addr));
734 addr = hsotg->regs + HFIR;
735 dev_dbg(hsotg->dev, "HFIR @0x%08lX : 0x%08X\n",
736 - (unsigned long)addr, readl(addr));
737 + (unsigned long)addr, dwc2_readl(addr));
738 addr = hsotg->regs + HFNUM;
739 dev_dbg(hsotg->dev, "HFNUM @0x%08lX : 0x%08X\n",
740 - (unsigned long)addr, readl(addr));
741 + (unsigned long)addr, dwc2_readl(addr));
742 addr = hsotg->regs + HPTXSTS;
743 dev_dbg(hsotg->dev, "HPTXSTS @0x%08lX : 0x%08X\n",
744 - (unsigned long)addr, readl(addr));
745 + (unsigned long)addr, dwc2_readl(addr));
746 addr = hsotg->regs + HAINT;
747 dev_dbg(hsotg->dev, "HAINT @0x%08lX : 0x%08X\n",
748 - (unsigned long)addr, readl(addr));
749 + (unsigned long)addr, dwc2_readl(addr));
750 addr = hsotg->regs + HAINTMSK;
751 dev_dbg(hsotg->dev, "HAINTMSK @0x%08lX : 0x%08X\n",
752 - (unsigned long)addr, readl(addr));
753 + (unsigned long)addr, dwc2_readl(addr));
754 if (hsotg->core_params->dma_desc_enable > 0) {
755 addr = hsotg->regs + HFLBADDR;
756 dev_dbg(hsotg->dev, "HFLBADDR @0x%08lX : 0x%08X\n",
757 - (unsigned long)addr, readl(addr));
758 + (unsigned long)addr, dwc2_readl(addr));
759 }
760
761 addr = hsotg->regs + HPRT0;
762 dev_dbg(hsotg->dev, "HPRT0 @0x%08lX : 0x%08X\n",
763 - (unsigned long)addr, readl(addr));
764 + (unsigned long)addr, dwc2_readl(addr));
765
766 for (i = 0; i < hsotg->core_params->host_channels; i++) {
767 dev_dbg(hsotg->dev, "Host Channel %d Specific Registers\n", i);
768 addr = hsotg->regs + HCCHAR(i);
769 dev_dbg(hsotg->dev, "HCCHAR @0x%08lX : 0x%08X\n",
770 - (unsigned long)addr, readl(addr));
771 + (unsigned long)addr, dwc2_readl(addr));
772 addr = hsotg->regs + HCSPLT(i);
773 dev_dbg(hsotg->dev, "HCSPLT @0x%08lX : 0x%08X\n",
774 - (unsigned long)addr, readl(addr));
775 + (unsigned long)addr, dwc2_readl(addr));
776 addr = hsotg->regs + HCINT(i);
777 dev_dbg(hsotg->dev, "HCINT @0x%08lX : 0x%08X\n",
778 - (unsigned long)addr, readl(addr));
779 + (unsigned long)addr, dwc2_readl(addr));
780 addr = hsotg->regs + HCINTMSK(i);
781 dev_dbg(hsotg->dev, "HCINTMSK @0x%08lX : 0x%08X\n",
782 - (unsigned long)addr, readl(addr));
783 + (unsigned long)addr, dwc2_readl(addr));
784 addr = hsotg->regs + HCTSIZ(i);
785 dev_dbg(hsotg->dev, "HCTSIZ @0x%08lX : 0x%08X\n",
786 - (unsigned long)addr, readl(addr));
787 + (unsigned long)addr, dwc2_readl(addr));
788 addr = hsotg->regs + HCDMA(i);
789 dev_dbg(hsotg->dev, "HCDMA @0x%08lX : 0x%08X\n",
790 - (unsigned long)addr, readl(addr));
791 + (unsigned long)addr, dwc2_readl(addr));
792 if (hsotg->core_params->dma_desc_enable > 0) {
793 addr = hsotg->regs + HCDMAB(i);
794 dev_dbg(hsotg->dev, "HCDMAB @0x%08lX : 0x%08X\n",
795 - (unsigned long)addr, readl(addr));
796 + (unsigned long)addr, dwc2_readl(addr));
797 }
798 }
799 #endif
800 @@ -1878,80 +1878,80 @@ void dwc2_dump_global_registers(struct d
801 dev_dbg(hsotg->dev, "Core Global Registers\n");
802 addr = hsotg->regs + GOTGCTL;
803 dev_dbg(hsotg->dev, "GOTGCTL @0x%08lX : 0x%08X\n",
804 - (unsigned long)addr, readl(addr));
805 + (unsigned long)addr, dwc2_readl(addr));
806 addr = hsotg->regs + GOTGINT;
807 dev_dbg(hsotg->dev, "GOTGINT @0x%08lX : 0x%08X\n",
808 - (unsigned long)addr, readl(addr));
809 + (unsigned long)addr, dwc2_readl(addr));
810 addr = hsotg->regs + GAHBCFG;
811 dev_dbg(hsotg->dev, "GAHBCFG @0x%08lX : 0x%08X\n",
812 - (unsigned long)addr, readl(addr));
813 + (unsigned long)addr, dwc2_readl(addr));
814 addr = hsotg->regs + GUSBCFG;
815 dev_dbg(hsotg->dev, "GUSBCFG @0x%08lX : 0x%08X\n",
816 - (unsigned long)addr, readl(addr));
817 + (unsigned long)addr, dwc2_readl(addr));
818 addr = hsotg->regs + GRSTCTL;
819 dev_dbg(hsotg->dev, "GRSTCTL @0x%08lX : 0x%08X\n",
820 - (unsigned long)addr, readl(addr));
821 + (unsigned long)addr, dwc2_readl(addr));
822 addr = hsotg->regs + GINTSTS;
823 dev_dbg(hsotg->dev, "GINTSTS @0x%08lX : 0x%08X\n",
824 - (unsigned long)addr, readl(addr));
825 + (unsigned long)addr, dwc2_readl(addr));
826 addr = hsotg->regs + GINTMSK;
827 dev_dbg(hsotg->dev, "GINTMSK @0x%08lX : 0x%08X\n",
828 - (unsigned long)addr, readl(addr));
829 + (unsigned long)addr, dwc2_readl(addr));
830 addr = hsotg->regs + GRXSTSR;
831 dev_dbg(hsotg->dev, "GRXSTSR @0x%08lX : 0x%08X\n",
832 - (unsigned long)addr, readl(addr));
833 + (unsigned long)addr, dwc2_readl(addr));
834 addr = hsotg->regs + GRXFSIZ;
835 dev_dbg(hsotg->dev, "GRXFSIZ @0x%08lX : 0x%08X\n",
836 - (unsigned long)addr, readl(addr));
837 + (unsigned long)addr, dwc2_readl(addr));
838 addr = hsotg->regs + GNPTXFSIZ;
839 dev_dbg(hsotg->dev, "GNPTXFSIZ @0x%08lX : 0x%08X\n",
840 - (unsigned long)addr, readl(addr));
841 + (unsigned long)addr, dwc2_readl(addr));
842 addr = hsotg->regs + GNPTXSTS;
843 dev_dbg(hsotg->dev, "GNPTXSTS @0x%08lX : 0x%08X\n",
844 - (unsigned long)addr, readl(addr));
845 + (unsigned long)addr, dwc2_readl(addr));
846 addr = hsotg->regs + GI2CCTL;
847 dev_dbg(hsotg->dev, "GI2CCTL @0x%08lX : 0x%08X\n",
848 - (unsigned long)addr, readl(addr));
849 + (unsigned long)addr, dwc2_readl(addr));
850 addr = hsotg->regs + GPVNDCTL;
851 dev_dbg(hsotg->dev, "GPVNDCTL @0x%08lX : 0x%08X\n",
852 - (unsigned long)addr, readl(addr));
853 + (unsigned long)addr, dwc2_readl(addr));
854 addr = hsotg->regs + GGPIO;
855 dev_dbg(hsotg->dev, "GGPIO @0x%08lX : 0x%08X\n",
856 - (unsigned long)addr, readl(addr));
857 + (unsigned long)addr, dwc2_readl(addr));
858 addr = hsotg->regs + GUID;
859 dev_dbg(hsotg->dev, "GUID @0x%08lX : 0x%08X\n",
860 - (unsigned long)addr, readl(addr));
861 + (unsigned long)addr, dwc2_readl(addr));
862 addr = hsotg->regs + GSNPSID;
863 dev_dbg(hsotg->dev, "GSNPSID @0x%08lX : 0x%08X\n",
864 - (unsigned long)addr, readl(addr));
865 + (unsigned long)addr, dwc2_readl(addr));
866 addr = hsotg->regs + GHWCFG1;
867 dev_dbg(hsotg->dev, "GHWCFG1 @0x%08lX : 0x%08X\n",
868 - (unsigned long)addr, readl(addr));
869 + (unsigned long)addr, dwc2_readl(addr));
870 addr = hsotg->regs + GHWCFG2;
871 dev_dbg(hsotg->dev, "GHWCFG2 @0x%08lX : 0x%08X\n",
872 - (unsigned long)addr, readl(addr));
873 + (unsigned long)addr, dwc2_readl(addr));
874 addr = hsotg->regs + GHWCFG3;
875 dev_dbg(hsotg->dev, "GHWCFG3 @0x%08lX : 0x%08X\n",
876 - (unsigned long)addr, readl(addr));
877 + (unsigned long)addr, dwc2_readl(addr));
878 addr = hsotg->regs + GHWCFG4;
879 dev_dbg(hsotg->dev, "GHWCFG4 @0x%08lX : 0x%08X\n",
880 - (unsigned long)addr, readl(addr));
881 + (unsigned long)addr, dwc2_readl(addr));
882 addr = hsotg->regs + GLPMCFG;
883 dev_dbg(hsotg->dev, "GLPMCFG @0x%08lX : 0x%08X\n",
884 - (unsigned long)addr, readl(addr));
885 + (unsigned long)addr, dwc2_readl(addr));
886 addr = hsotg->regs + GPWRDN;
887 dev_dbg(hsotg->dev, "GPWRDN @0x%08lX : 0x%08X\n",
888 - (unsigned long)addr, readl(addr));
889 + (unsigned long)addr, dwc2_readl(addr));
890 addr = hsotg->regs + GDFIFOCFG;
891 dev_dbg(hsotg->dev, "GDFIFOCFG @0x%08lX : 0x%08X\n",
892 - (unsigned long)addr, readl(addr));
893 + (unsigned long)addr, dwc2_readl(addr));
894 addr = hsotg->regs + HPTXFSIZ;
895 dev_dbg(hsotg->dev, "HPTXFSIZ @0x%08lX : 0x%08X\n",
896 - (unsigned long)addr, readl(addr));
897 + (unsigned long)addr, dwc2_readl(addr));
898
899 addr = hsotg->regs + PCGCTL;
900 dev_dbg(hsotg->dev, "PCGCTL @0x%08lX : 0x%08X\n",
901 - (unsigned long)addr, readl(addr));
902 + (unsigned long)addr, dwc2_readl(addr));
903 #endif
904 }
905
906 @@ -1970,15 +1970,15 @@ void dwc2_flush_tx_fifo(struct dwc2_hsot
907
908 greset = GRSTCTL_TXFFLSH;
909 greset |= num << GRSTCTL_TXFNUM_SHIFT & GRSTCTL_TXFNUM_MASK;
910 - writel(greset, hsotg->regs + GRSTCTL);
911 + dwc2_writel(greset, hsotg->regs + GRSTCTL);
912
913 do {
914 - greset = readl(hsotg->regs + GRSTCTL);
915 + greset = dwc2_readl(hsotg->regs + GRSTCTL);
916 if (++count > 10000) {
917 dev_warn(hsotg->dev,
918 "%s() HANG! GRSTCTL=%0x GNPTXSTS=0x%08x\n",
919 __func__, greset,
920 - readl(hsotg->regs + GNPTXSTS));
921 + dwc2_readl(hsotg->regs + GNPTXSTS));
922 break;
923 }
924 udelay(1);
925 @@ -2001,10 +2001,10 @@ void dwc2_flush_rx_fifo(struct dwc2_hsot
926 dev_vdbg(hsotg->dev, "%s()\n", __func__);
927
928 greset = GRSTCTL_RXFFLSH;
929 - writel(greset, hsotg->regs + GRSTCTL);
930 + dwc2_writel(greset, hsotg->regs + GRSTCTL);
931
932 do {
933 - greset = readl(hsotg->regs + GRSTCTL);
934 + greset = dwc2_readl(hsotg->regs + GRSTCTL);
935 if (++count > 10000) {
936 dev_warn(hsotg->dev, "%s() HANG! GRSTCTL=%0x\n",
937 __func__, greset);
938 @@ -2666,7 +2666,7 @@ int dwc2_get_hwparams(struct dwc2_hsotg
939 * 0x45f42xxx or 0x45f43xxx, which corresponds to either "OT2" or "OT3",
940 * as in "OTG version 2.xx" or "OTG version 3.xx".
941 */
942 - hw->snpsid = readl(hsotg->regs + GSNPSID);
943 + hw->snpsid = dwc2_readl(hsotg->regs + GSNPSID);
944 if ((hw->snpsid & 0xfffff000) != 0x4f542000 &&
945 (hw->snpsid & 0xfffff000) != 0x4f543000) {
946 dev_err(hsotg->dev, "Bad value for GSNPSID: 0x%08x\n",
947 @@ -2678,11 +2678,11 @@ int dwc2_get_hwparams(struct dwc2_hsotg
948 hw->snpsid >> 12 & 0xf, hw->snpsid >> 8 & 0xf,
949 hw->snpsid >> 4 & 0xf, hw->snpsid & 0xf, hw->snpsid);
950
951 - hwcfg1 = readl(hsotg->regs + GHWCFG1);
952 - hwcfg2 = readl(hsotg->regs + GHWCFG2);
953 - hwcfg3 = readl(hsotg->regs + GHWCFG3);
954 - hwcfg4 = readl(hsotg->regs + GHWCFG4);
955 - grxfsiz = readl(hsotg->regs + GRXFSIZ);
956 + hwcfg1 = dwc2_readl(hsotg->regs + GHWCFG1);
957 + hwcfg2 = dwc2_readl(hsotg->regs + GHWCFG2);
958 + hwcfg3 = dwc2_readl(hsotg->regs + GHWCFG3);
959 + hwcfg4 = dwc2_readl(hsotg->regs + GHWCFG4);
960 + grxfsiz = dwc2_readl(hsotg->regs + GRXFSIZ);
961
962 dev_dbg(hsotg->dev, "hwcfg1=%08x\n", hwcfg1);
963 dev_dbg(hsotg->dev, "hwcfg2=%08x\n", hwcfg2);
964 @@ -2691,18 +2691,18 @@ int dwc2_get_hwparams(struct dwc2_hsotg
965 dev_dbg(hsotg->dev, "grxfsiz=%08x\n", grxfsiz);
966
967 /* Force host mode to get HPTXFSIZ / GNPTXFSIZ exact power on value */
968 - gusbcfg = readl(hsotg->regs + GUSBCFG);
969 + gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
970 gusbcfg |= GUSBCFG_FORCEHOSTMODE;
971 - writel(gusbcfg, hsotg->regs + GUSBCFG);
972 + dwc2_writel(gusbcfg, hsotg->regs + GUSBCFG);
973 usleep_range(100000, 150000);
974
975 - gnptxfsiz = readl(hsotg->regs + GNPTXFSIZ);
976 - hptxfsiz = readl(hsotg->regs + HPTXFSIZ);
977 + gnptxfsiz = dwc2_readl(hsotg->regs + GNPTXFSIZ);
978 + hptxfsiz = dwc2_readl(hsotg->regs + HPTXFSIZ);
979 dev_dbg(hsotg->dev, "gnptxfsiz=%08x\n", gnptxfsiz);
980 dev_dbg(hsotg->dev, "hptxfsiz=%08x\n", hptxfsiz);
981 - gusbcfg = readl(hsotg->regs + GUSBCFG);
982 + gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
983 gusbcfg &= ~GUSBCFG_FORCEHOSTMODE;
984 - writel(gusbcfg, hsotg->regs + GUSBCFG);
985 + dwc2_writel(gusbcfg, hsotg->regs + GUSBCFG);
986 usleep_range(100000, 150000);
987
988 /* hwcfg2 */
989 @@ -2821,7 +2821,7 @@ u16 dwc2_get_otg_version(struct dwc2_hso
990
991 bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg)
992 {
993 - if (readl(hsotg->regs + GSNPSID) == 0xffffffff)
994 + if (dwc2_readl(hsotg->regs + GSNPSID) == 0xffffffff)
995 return false;
996 else
997 return true;
998 @@ -2835,10 +2835,10 @@ bool dwc2_is_controller_alive(struct dwc
999 */
1000 void dwc2_enable_global_interrupts(struct dwc2_hsotg *hsotg)
1001 {
1002 - u32 ahbcfg = readl(hsotg->regs + GAHBCFG);
1003 + u32 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG);
1004
1005 ahbcfg |= GAHBCFG_GLBL_INTR_EN;
1006 - writel(ahbcfg, hsotg->regs + GAHBCFG);
1007 + dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG);
1008 }
1009
1010 /**
1011 @@ -2849,10 +2849,10 @@ void dwc2_enable_global_interrupts(struc
1012 */
1013 void dwc2_disable_global_interrupts(struct dwc2_hsotg *hsotg)
1014 {
1015 - u32 ahbcfg = readl(hsotg->regs + GAHBCFG);
1016 + u32 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG);
1017
1018 ahbcfg &= ~GAHBCFG_GLBL_INTR_EN;
1019 - writel(ahbcfg, hsotg->regs + GAHBCFG);
1020 + dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG);
1021 }
1022
1023 MODULE_DESCRIPTION("DESIGNWARE HS OTG Core");
1024 --- a/drivers/usb/dwc2/core.h
1025 +++ b/drivers/usb/dwc2/core.h
1026 @@ -44,16 +44,28 @@
1027 #include <linux/usb/phy.h>
1028 #include "hw.h"
1029
1030 -#ifdef DWC2_LOG_WRITES
1031 -static inline void do_write(u32 value, void *addr)
1032 +static inline u32 dwc2_readl(const void __iomem *addr)
1033 {
1034 - writel(value, addr);
1035 - pr_info("INFO:: wrote %08x to %p\n", value, addr);
1036 + u32 value = __raw_readl(addr);
1037 +
1038 + /* In order to preserve endianness __raw_* operation is used. Therefore
1039 + a barrier is needed to ensure IO access is not re-ordered across
1040 + reads or writes */
1041 + mb();
1042 + return value;
1043 }
1044
1045 -#undef writel
1046 -#define writel(v, a) do_write(v, a)
1047 +static inline void dwc2_writel(u32 value, void __iomem *addr)
1048 +{
1049 + __raw_writel(value, addr);
1050 + /* In order to preserve endianness __raw_* operation is used. Therefore
1051 + a barrier is needed to ensure IO access is not re-ordered across
1052 + reads or writes */
1053 + mb();
1054 +#ifdef DWC2_LOG_WRITES
1055 + pr_info("INFO:: wrote %08x to %p\n", value, addr);
1056 #endif
1057 +}
1058
1059 /* Maximum number of Endpoints/HostChannels */
1060 #define MAX_EPS_CHANNELS 16
1061 --- a/drivers/usb/dwc2/core_intr.c
1062 +++ b/drivers/usb/dwc2/core_intr.c
1063 @@ -80,15 +80,15 @@ static const char *dwc2_op_state_str(str
1064 */
1065 static void dwc2_handle_usb_port_intr(struct dwc2_hsotg *hsotg)
1066 {
1067 - u32 hprt0 = readl(hsotg->regs + HPRT0);
1068 + u32 hprt0 = dwc2_readl(hsotg->regs + HPRT0);
1069
1070 if (hprt0 & HPRT0_ENACHG) {
1071 hprt0 &= ~HPRT0_ENA;
1072 - writel(hprt0, hsotg->regs + HPRT0);
1073 + dwc2_writel(hprt0, hsotg->regs + HPRT0);
1074 }
1075
1076 /* Clear interrupt */
1077 - writel(GINTSTS_PRTINT, hsotg->regs + GINTSTS);
1078 + dwc2_writel(GINTSTS_PRTINT, hsotg->regs + GINTSTS);
1079 }
1080
1081 /**
1082 @@ -102,7 +102,7 @@ static void dwc2_handle_mode_mismatch_in
1083 dwc2_is_host_mode(hsotg) ? "Host" : "Device");
1084
1085 /* Clear interrupt */
1086 - writel(GINTSTS_MODEMIS, hsotg->regs + GINTSTS);
1087 + dwc2_writel(GINTSTS_MODEMIS, hsotg->regs + GINTSTS);
1088 }
1089
1090 /**
1091 @@ -117,8 +117,8 @@ static void dwc2_handle_otg_intr(struct
1092 u32 gotgctl;
1093 u32 gintmsk;
1094
1095 - gotgint = readl(hsotg->regs + GOTGINT);
1096 - gotgctl = readl(hsotg->regs + GOTGCTL);
1097 + gotgint = dwc2_readl(hsotg->regs + GOTGINT);
1098 + gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
1099 dev_dbg(hsotg->dev, "++OTG Interrupt gotgint=%0x [%s]\n", gotgint,
1100 dwc2_op_state_str(hsotg));
1101
1102 @@ -126,7 +126,7 @@ static void dwc2_handle_otg_intr(struct
1103 dev_dbg(hsotg->dev,
1104 " ++OTG Interrupt: Session End Detected++ (%s)\n",
1105 dwc2_op_state_str(hsotg));
1106 - gotgctl = readl(hsotg->regs + GOTGCTL);
1107 + gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
1108
1109 if (dwc2_is_device_mode(hsotg))
1110 s3c_hsotg_disconnect(hsotg);
1111 @@ -152,15 +152,15 @@ static void dwc2_handle_otg_intr(struct
1112 hsotg->lx_state = DWC2_L0;
1113 }
1114
1115 - gotgctl = readl(hsotg->regs + GOTGCTL);
1116 + gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
1117 gotgctl &= ~GOTGCTL_DEVHNPEN;
1118 - writel(gotgctl, hsotg->regs + GOTGCTL);
1119 + dwc2_writel(gotgctl, hsotg->regs + GOTGCTL);
1120 }
1121
1122 if (gotgint & GOTGINT_SES_REQ_SUC_STS_CHNG) {
1123 dev_dbg(hsotg->dev,
1124 " ++OTG Interrupt: Session Request Success Status Change++\n");
1125 - gotgctl = readl(hsotg->regs + GOTGCTL);
1126 + gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
1127 if (gotgctl & GOTGCTL_SESREQSCS) {
1128 if (hsotg->core_params->phy_type ==
1129 DWC2_PHY_TYPE_PARAM_FS
1130 @@ -168,9 +168,9 @@ static void dwc2_handle_otg_intr(struct
1131 hsotg->srp_success = 1;
1132 } else {
1133 /* Clear Session Request */
1134 - gotgctl = readl(hsotg->regs + GOTGCTL);
1135 + gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
1136 gotgctl &= ~GOTGCTL_SESREQ;
1137 - writel(gotgctl, hsotg->regs + GOTGCTL);
1138 + dwc2_writel(gotgctl, hsotg->regs + GOTGCTL);
1139 }
1140 }
1141 }
1142 @@ -180,7 +180,7 @@ static void dwc2_handle_otg_intr(struct
1143 * Print statements during the HNP interrupt handling
1144 * can cause it to fail
1145 */
1146 - gotgctl = readl(hsotg->regs + GOTGCTL);
1147 + gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
1148 /*
1149 * WA for 3.00a- HW is not setting cur_mode, even sometimes
1150 * this does not help
1151 @@ -200,9 +200,9 @@ static void dwc2_handle_otg_intr(struct
1152 * interrupt does not get handled and Linux
1153 * complains loudly.
1154 */
1155 - gintmsk = readl(hsotg->regs + GINTMSK);
1156 + gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
1157 gintmsk &= ~GINTSTS_SOF;
1158 - writel(gintmsk, hsotg->regs + GINTMSK);
1159 + dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
1160
1161 /*
1162 * Call callback function with spin lock
1163 @@ -216,9 +216,9 @@ static void dwc2_handle_otg_intr(struct
1164 hsotg->op_state = OTG_STATE_B_HOST;
1165 }
1166 } else {
1167 - gotgctl = readl(hsotg->regs + GOTGCTL);
1168 + gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
1169 gotgctl &= ~(GOTGCTL_HNPREQ | GOTGCTL_DEVHNPEN);
1170 - writel(gotgctl, hsotg->regs + GOTGCTL);
1171 + dwc2_writel(gotgctl, hsotg->regs + GOTGCTL);
1172 dev_dbg(hsotg->dev, "HNP Failed\n");
1173 dev_err(hsotg->dev,
1174 "Device Not Connected/Responding\n");
1175 @@ -244,9 +244,9 @@ static void dwc2_handle_otg_intr(struct
1176 hsotg->op_state = OTG_STATE_A_PERIPHERAL;
1177 } else {
1178 /* Need to disable SOF interrupt immediately */
1179 - gintmsk = readl(hsotg->regs + GINTMSK);
1180 + gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
1181 gintmsk &= ~GINTSTS_SOF;
1182 - writel(gintmsk, hsotg->regs + GINTMSK);
1183 + dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
1184 spin_unlock(&hsotg->lock);
1185 dwc2_hcd_start(hsotg);
1186 spin_lock(&hsotg->lock);
1187 @@ -261,7 +261,7 @@ static void dwc2_handle_otg_intr(struct
1188 dev_dbg(hsotg->dev, " ++OTG Interrupt: Debounce Done++\n");
1189
1190 /* Clear GOTGINT */
1191 - writel(gotgint, hsotg->regs + GOTGINT);
1192 + dwc2_writel(gotgint, hsotg->regs + GOTGINT);
1193 }
1194
1195 /**
1196 @@ -276,11 +276,11 @@ static void dwc2_handle_otg_intr(struct
1197 */
1198 static void dwc2_handle_conn_id_status_change_intr(struct dwc2_hsotg *hsotg)
1199 {
1200 - u32 gintmsk = readl(hsotg->regs + GINTMSK);
1201 + u32 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
1202
1203 /* Need to disable SOF interrupt immediately */
1204 gintmsk &= ~GINTSTS_SOF;
1205 - writel(gintmsk, hsotg->regs + GINTMSK);
1206 + dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
1207
1208 dev_dbg(hsotg->dev, " ++Connector ID Status Change Interrupt++ (%s)\n",
1209 dwc2_is_host_mode(hsotg) ? "Host" : "Device");
1210 @@ -297,7 +297,7 @@ static void dwc2_handle_conn_id_status_c
1211 }
1212
1213 /* Clear interrupt */
1214 - writel(GINTSTS_CONIDSTSCHNG, hsotg->regs + GINTSTS);
1215 + dwc2_writel(GINTSTS_CONIDSTSCHNG, hsotg->regs + GINTSTS);
1216 }
1217
1218 /**
1219 @@ -316,7 +316,7 @@ static void dwc2_handle_session_req_intr
1220 dev_dbg(hsotg->dev, "++Session Request Interrupt++\n");
1221
1222 /* Clear interrupt */
1223 - writel(GINTSTS_SESSREQINT, hsotg->regs + GINTSTS);
1224 + dwc2_writel(GINTSTS_SESSREQINT, hsotg->regs + GINTSTS);
1225
1226 /*
1227 * Report disconnect if there is any previous session established
1228 @@ -338,23 +338,23 @@ static void dwc2_handle_wakeup_detected_
1229 dev_dbg(hsotg->dev, "%s lxstate = %d\n", __func__, hsotg->lx_state);
1230
1231 if (dwc2_is_device_mode(hsotg)) {
1232 - dev_dbg(hsotg->dev, "DSTS=0x%0x\n", readl(hsotg->regs + DSTS));
1233 + dev_dbg(hsotg->dev, "DSTS=0x%0x\n", dwc2_readl(hsotg->regs + DSTS));
1234 if (hsotg->lx_state == DWC2_L2) {
1235 - u32 dctl = readl(hsotg->regs + DCTL);
1236 + u32 dctl = dwc2_readl(hsotg->regs + DCTL);
1237
1238 /* Clear Remote Wakeup Signaling */
1239 dctl &= ~DCTL_RMTWKUPSIG;
1240 - writel(dctl, hsotg->regs + DCTL);
1241 + dwc2_writel(dctl, hsotg->regs + DCTL);
1242 }
1243 /* Change to L0 state */
1244 hsotg->lx_state = DWC2_L0;
1245 } else {
1246 if (hsotg->lx_state != DWC2_L1) {
1247 - u32 pcgcctl = readl(hsotg->regs + PCGCTL);
1248 + u32 pcgcctl = dwc2_readl(hsotg->regs + PCGCTL);
1249
1250 /* Restart the Phy Clock */
1251 pcgcctl &= ~PCGCTL_STOPPCLK;
1252 - writel(pcgcctl, hsotg->regs + PCGCTL);
1253 + dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
1254 mod_timer(&hsotg->wkp_timer,
1255 jiffies + msecs_to_jiffies(71));
1256 } else {
1257 @@ -364,7 +364,7 @@ static void dwc2_handle_wakeup_detected_
1258 }
1259
1260 /* Clear interrupt */
1261 - writel(GINTSTS_WKUPINT, hsotg->regs + GINTSTS);
1262 + dwc2_writel(GINTSTS_WKUPINT, hsotg->regs + GINTSTS);
1263 }
1264
1265 /*
1266 @@ -383,7 +383,7 @@ static void dwc2_handle_disconnect_intr(
1267 /* Change to L3 (OFF) state */
1268 hsotg->lx_state = DWC2_L3;
1269
1270 - writel(GINTSTS_DISCONNINT, hsotg->regs + GINTSTS);
1271 + dwc2_writel(GINTSTS_DISCONNINT, hsotg->regs + GINTSTS);
1272 }
1273
1274 /*
1275 @@ -405,7 +405,7 @@ static void dwc2_handle_usb_suspend_intr
1276 * Check the Device status register to determine if the Suspend
1277 * state is active
1278 */
1279 - dsts = readl(hsotg->regs + DSTS);
1280 + dsts = dwc2_readl(hsotg->regs + DSTS);
1281 dev_dbg(hsotg->dev, "DSTS=0x%0x\n", dsts);
1282 dev_dbg(hsotg->dev,
1283 "DSTS.Suspend Status=%d HWCFG4.Power Optimize=%d\n",
1284 @@ -427,7 +427,7 @@ static void dwc2_handle_usb_suspend_intr
1285 hsotg->lx_state = DWC2_L2;
1286
1287 /* Clear interrupt */
1288 - writel(GINTSTS_USBSUSP, hsotg->regs + GINTSTS);
1289 + dwc2_writel(GINTSTS_USBSUSP, hsotg->regs + GINTSTS);
1290 }
1291
1292 #define GINTMSK_COMMON (GINTSTS_WKUPINT | GINTSTS_SESSREQINT | \
1293 @@ -445,9 +445,9 @@ static u32 dwc2_read_common_intr(struct
1294 u32 gahbcfg;
1295 u32 gintmsk_common = GINTMSK_COMMON;
1296
1297 - gintsts = readl(hsotg->regs + GINTSTS);
1298 - gintmsk = readl(hsotg->regs + GINTMSK);
1299 - gahbcfg = readl(hsotg->regs + GAHBCFG);
1300 + gintsts = dwc2_readl(hsotg->regs + GINTSTS);
1301 + gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
1302 + gahbcfg = dwc2_readl(hsotg->regs + GAHBCFG);
1303
1304 /* If any common interrupts set */
1305 if (gintsts & gintmsk_common)
1306 --- a/drivers/usb/dwc2/gadget.c
1307 +++ b/drivers/usb/dwc2/gadget.c
1308 @@ -58,12 +58,12 @@ static inline struct dwc2_hsotg *to_hsot
1309
1310 static inline void __orr32(void __iomem *ptr, u32 val)
1311 {
1312 - writel(readl(ptr) | val, ptr);
1313 + dwc2_writel(dwc2_readl(ptr) | val, ptr);
1314 }
1315
1316 static inline void __bic32(void __iomem *ptr, u32 val)
1317 {
1318 - writel(readl(ptr) & ~val, ptr);
1319 + dwc2_writel(dwc2_readl(ptr) & ~val, ptr);
1320 }
1321
1322 static inline struct s3c_hsotg_ep *index_to_ep(struct dwc2_hsotg *hsotg,
1323 @@ -109,14 +109,14 @@ static inline bool using_dma(struct dwc2
1324 */
1325 static void s3c_hsotg_en_gsint(struct dwc2_hsotg *hsotg, u32 ints)
1326 {
1327 - u32 gsintmsk = readl(hsotg->regs + GINTMSK);
1328 + u32 gsintmsk = dwc2_readl(hsotg->regs + GINTMSK);
1329 u32 new_gsintmsk;
1330
1331 new_gsintmsk = gsintmsk | ints;
1332
1333 if (new_gsintmsk != gsintmsk) {
1334 dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk);
1335 - writel(new_gsintmsk, hsotg->regs + GINTMSK);
1336 + dwc2_writel(new_gsintmsk, hsotg->regs + GINTMSK);
1337 }
1338 }
1339
1340 @@ -127,13 +127,13 @@ static void s3c_hsotg_en_gsint(struct dw
1341 */
1342 static void s3c_hsotg_disable_gsint(struct dwc2_hsotg *hsotg, u32 ints)
1343 {
1344 - u32 gsintmsk = readl(hsotg->regs + GINTMSK);
1345 + u32 gsintmsk = dwc2_readl(hsotg->regs + GINTMSK);
1346 u32 new_gsintmsk;
1347
1348 new_gsintmsk = gsintmsk & ~ints;
1349
1350 if (new_gsintmsk != gsintmsk)
1351 - writel(new_gsintmsk, hsotg->regs + GINTMSK);
1352 + dwc2_writel(new_gsintmsk, hsotg->regs + GINTMSK);
1353 }
1354
1355 /**
1356 @@ -158,12 +158,12 @@ static void s3c_hsotg_ctrl_epint(struct
1357 bit <<= 16;
1358
1359 local_irq_save(flags);
1360 - daint = readl(hsotg->regs + DAINTMSK);
1361 + daint = dwc2_readl(hsotg->regs + DAINTMSK);
1362 if (en)
1363 daint |= bit;
1364 else
1365 daint &= ~bit;
1366 - writel(daint, hsotg->regs + DAINTMSK);
1367 + dwc2_writel(daint, hsotg->regs + DAINTMSK);
1368 local_irq_restore(flags);
1369 }
1370
1371 @@ -183,8 +183,8 @@ static void s3c_hsotg_init_fifo(struct d
1372 hsotg->fifo_map = 0;
1373
1374 /* set RX/NPTX FIFO sizes */
1375 - writel(hsotg->g_rx_fifo_sz, hsotg->regs + GRXFSIZ);
1376 - writel((hsotg->g_rx_fifo_sz << FIFOSIZE_STARTADDR_SHIFT) |
1377 + dwc2_writel(hsotg->g_rx_fifo_sz, hsotg->regs + GRXFSIZ);
1378 + dwc2_writel((hsotg->g_rx_fifo_sz << FIFOSIZE_STARTADDR_SHIFT) |
1379 (hsotg->g_np_g_tx_fifo_sz << FIFOSIZE_DEPTH_SHIFT),
1380 hsotg->regs + GNPTXFSIZ);
1381
1382 @@ -212,7 +212,7 @@ static void s3c_hsotg_init_fifo(struct d
1383 "insufficient fifo memory");
1384 addr += hsotg->g_tx_fifo_sz[ep];
1385
1386 - writel(val, hsotg->regs + DPTXFSIZN(ep));
1387 + dwc2_writel(val, hsotg->regs + DPTXFSIZN(ep));
1388 }
1389
1390 /*
1391 @@ -220,13 +220,13 @@ static void s3c_hsotg_init_fifo(struct d
1392 * all fifos are flushed before continuing
1393 */
1394
1395 - writel(GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH |
1396 + dwc2_writel(GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH |
1397 GRSTCTL_RXFFLSH, hsotg->regs + GRSTCTL);
1398
1399 /* wait until the fifos are both flushed */
1400 timeout = 100;
1401 while (1) {
1402 - val = readl(hsotg->regs + GRSTCTL);
1403 + val = dwc2_readl(hsotg->regs + GRSTCTL);
1404
1405 if ((val & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH)) == 0)
1406 break;
1407 @@ -319,7 +319,7 @@ static int s3c_hsotg_write_fifo(struct d
1408 struct s3c_hsotg_req *hs_req)
1409 {
1410 bool periodic = is_ep_periodic(hs_ep);
1411 - u32 gnptxsts = readl(hsotg->regs + GNPTXSTS);
1412 + u32 gnptxsts = dwc2_readl(hsotg->regs + GNPTXSTS);
1413 int buf_pos = hs_req->req.actual;
1414 int to_write = hs_ep->size_loaded;
1415 void *data;
1416 @@ -334,7 +334,7 @@ static int s3c_hsotg_write_fifo(struct d
1417 return 0;
1418
1419 if (periodic && !hsotg->dedicated_fifos) {
1420 - u32 epsize = readl(hsotg->regs + DIEPTSIZ(hs_ep->index));
1421 + u32 epsize = dwc2_readl(hsotg->regs + DIEPTSIZ(hs_ep->index));
1422 int size_left;
1423 int size_done;
1424
1425 @@ -375,7 +375,7 @@ static int s3c_hsotg_write_fifo(struct d
1426 return -ENOSPC;
1427 }
1428 } else if (hsotg->dedicated_fifos && hs_ep->index != 0) {
1429 - can_write = readl(hsotg->regs + DTXFSTS(hs_ep->index));
1430 + can_write = dwc2_readl(hsotg->regs + DTXFSTS(hs_ep->index));
1431
1432 can_write &= 0xffff;
1433 can_write *= 4;
1434 @@ -552,11 +552,11 @@ static void s3c_hsotg_start_req(struct d
1435 epsize_reg = dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index);
1436
1437 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n",
1438 - __func__, readl(hsotg->regs + epctrl_reg), index,
1439 + __func__, dwc2_readl(hsotg->regs + epctrl_reg), index,
1440 hs_ep->dir_in ? "in" : "out");
1441
1442 /* If endpoint is stalled, we will restart request later */
1443 - ctrl = readl(hsotg->regs + epctrl_reg);
1444 + ctrl = dwc2_readl(hsotg->regs + epctrl_reg);
1445
1446 if (ctrl & DXEPCTL_STALL) {
1447 dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index);
1448 @@ -620,7 +620,7 @@ static void s3c_hsotg_start_req(struct d
1449 hs_ep->req = hs_req;
1450
1451 /* write size / packets */
1452 - writel(epsize, hsotg->regs + epsize_reg);
1453 + dwc2_writel(epsize, hsotg->regs + epsize_reg);
1454
1455 if (using_dma(hsotg) && !continuing) {
1456 unsigned int dma_reg;
1457 @@ -631,7 +631,7 @@ static void s3c_hsotg_start_req(struct d
1458 */
1459
1460 dma_reg = dir_in ? DIEPDMA(index) : DOEPDMA(index);
1461 - writel(ureq->dma, hsotg->regs + dma_reg);
1462 + dwc2_writel(ureq->dma, hsotg->regs + dma_reg);
1463
1464 dev_dbg(hsotg->dev, "%s: %pad => 0x%08x\n",
1465 __func__, &ureq->dma, dma_reg);
1466 @@ -647,7 +647,7 @@ static void s3c_hsotg_start_req(struct d
1467 ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */
1468
1469 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
1470 - writel(ctrl, hsotg->regs + epctrl_reg);
1471 + dwc2_writel(ctrl, hsotg->regs + epctrl_reg);
1472
1473 /*
1474 * set these, it seems that DMA support increments past the end
1475 @@ -669,7 +669,7 @@ static void s3c_hsotg_start_req(struct d
1476 * to debugging to see what is going on.
1477 */
1478 if (dir_in)
1479 - writel(DIEPMSK_INTKNTXFEMPMSK,
1480 + dwc2_writel(DIEPMSK_INTKNTXFEMPMSK,
1481 hsotg->regs + DIEPINT(index));
1482
1483 /*
1484 @@ -678,13 +678,13 @@ static void s3c_hsotg_start_req(struct d
1485 */
1486
1487 /* check ep is enabled */
1488 - if (!(readl(hsotg->regs + epctrl_reg) & DXEPCTL_EPENA))
1489 + if (!(dwc2_readl(hsotg->regs + epctrl_reg) & DXEPCTL_EPENA))
1490 dev_dbg(hsotg->dev,
1491 "ep%d: failed to become enabled (DXEPCTL=0x%08x)?\n",
1492 - index, readl(hsotg->regs + epctrl_reg));
1493 + index, dwc2_readl(hsotg->regs + epctrl_reg));
1494
1495 dev_dbg(hsotg->dev, "%s: DXEPCTL=0x%08x\n",
1496 - __func__, readl(hsotg->regs + epctrl_reg));
1497 + __func__, dwc2_readl(hsotg->regs + epctrl_reg));
1498
1499 /* enable ep interrupts */
1500 s3c_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 1);
1501 @@ -896,7 +896,7 @@ static struct s3c_hsotg_ep *ep_from_wind
1502 */
1503 static int s3c_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode)
1504 {
1505 - int dctl = readl(hsotg->regs + DCTL);
1506 + int dctl = dwc2_readl(hsotg->regs + DCTL);
1507
1508 dctl &= ~DCTL_TSTCTL_MASK;
1509 switch (testmode) {
1510 @@ -910,7 +910,7 @@ static int s3c_hsotg_set_test_mode(struc
1511 default:
1512 return -EINVAL;
1513 }
1514 - writel(dctl, hsotg->regs + DCTL);
1515 + dwc2_writel(dctl, hsotg->regs + DCTL);
1516 return 0;
1517 }
1518
1519 @@ -1169,14 +1169,14 @@ static void s3c_hsotg_stall_ep0(struct d
1520 * taken effect, so no need to clear later.
1521 */
1522
1523 - ctrl = readl(hsotg->regs + reg);
1524 + ctrl = dwc2_readl(hsotg->regs + reg);
1525 ctrl |= DXEPCTL_STALL;
1526 ctrl |= DXEPCTL_CNAK;
1527 - writel(ctrl, hsotg->regs + reg);
1528 + dwc2_writel(ctrl, hsotg->regs + reg);
1529
1530 dev_dbg(hsotg->dev,
1531 "written DXEPCTL=0x%08x to %08x (DXEPCTL=0x%08x)\n",
1532 - ctrl, reg, readl(hsotg->regs + reg));
1533 + ctrl, reg, dwc2_readl(hsotg->regs + reg));
1534
1535 /*
1536 * complete won't be called, so we enqueue
1537 @@ -1220,11 +1220,11 @@ static void s3c_hsotg_process_control(st
1538 switch (ctrl->bRequest) {
1539 case USB_REQ_SET_ADDRESS:
1540 hsotg->connected = 1;
1541 - dcfg = readl(hsotg->regs + DCFG);
1542 + dcfg = dwc2_readl(hsotg->regs + DCFG);
1543 dcfg &= ~DCFG_DEVADDR_MASK;
1544 dcfg |= (le16_to_cpu(ctrl->wValue) <<
1545 DCFG_DEVADDR_SHIFT) & DCFG_DEVADDR_MASK;
1546 - writel(dcfg, hsotg->regs + DCFG);
1547 + dwc2_writel(dcfg, hsotg->regs + DCFG);
1548
1549 dev_info(hsotg->dev, "new address %d\n", ctrl->wValue);
1550
1551 @@ -1342,15 +1342,15 @@ static void s3c_hsotg_program_zlp(struct
1552 dev_dbg(hsotg->dev, "Receiving zero-length packet on ep%d\n",
1553 index);
1554
1555 - writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
1556 + dwc2_writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
1557 DXEPTSIZ_XFERSIZE(0), hsotg->regs +
1558 epsiz_reg);
1559
1560 - ctrl = readl(hsotg->regs + epctl_reg);
1561 + ctrl = dwc2_readl(hsotg->regs + epctl_reg);
1562 ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */
1563 ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */
1564 ctrl |= DXEPCTL_USBACTEP;
1565 - writel(ctrl, hsotg->regs + epctl_reg);
1566 + dwc2_writel(ctrl, hsotg->regs + epctl_reg);
1567 }
1568
1569 /**
1570 @@ -1444,7 +1444,7 @@ static void s3c_hsotg_rx_data(struct dwc
1571
1572
1573 if (!hs_req) {
1574 - u32 epctl = readl(hsotg->regs + DOEPCTL(ep_idx));
1575 + u32 epctl = dwc2_readl(hsotg->regs + DOEPCTL(ep_idx));
1576 int ptr;
1577
1578 dev_dbg(hsotg->dev,
1579 @@ -1453,7 +1453,7 @@ static void s3c_hsotg_rx_data(struct dwc
1580
1581 /* dump the data from the FIFO, we've nothing we can do */
1582 for (ptr = 0; ptr < size; ptr += 4)
1583 - (void)readl(fifo);
1584 + (void)dwc2_readl(fifo);
1585
1586 return;
1587 }
1588 @@ -1518,7 +1518,7 @@ static void s3c_hsotg_ep0_zlp(struct dwc
1589 */
1590 static void s3c_hsotg_handle_outdone(struct dwc2_hsotg *hsotg, int epnum)
1591 {
1592 - u32 epsize = readl(hsotg->regs + DOEPTSIZ(epnum));
1593 + u32 epsize = dwc2_readl(hsotg->regs + DOEPTSIZ(epnum));
1594 struct s3c_hsotg_ep *hs_ep = hsotg->eps_out[epnum];
1595 struct s3c_hsotg_req *hs_req = hs_ep->req;
1596 struct usb_request *req = &hs_req->req;
1597 @@ -1590,7 +1590,7 @@ static u32 s3c_hsotg_read_frameno(struct
1598 {
1599 u32 dsts;
1600
1601 - dsts = readl(hsotg->regs + DSTS);
1602 + dsts = dwc2_readl(hsotg->regs + DSTS);
1603 dsts &= DSTS_SOFFN_MASK;
1604 dsts >>= DSTS_SOFFN_SHIFT;
1605
1606 @@ -1615,7 +1615,7 @@ static u32 s3c_hsotg_read_frameno(struct
1607 */
1608 static void s3c_hsotg_handle_rx(struct dwc2_hsotg *hsotg)
1609 {
1610 - u32 grxstsr = readl(hsotg->regs + GRXSTSP);
1611 + u32 grxstsr = dwc2_readl(hsotg->regs + GRXSTSP);
1612 u32 epnum, status, size;
1613
1614 WARN_ON(using_dma(hsotg));
1615 @@ -1646,7 +1646,7 @@ static void s3c_hsotg_handle_rx(struct d
1616 dev_dbg(hsotg->dev,
1617 "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1618 s3c_hsotg_read_frameno(hsotg),
1619 - readl(hsotg->regs + DOEPCTL(0)));
1620 + dwc2_readl(hsotg->regs + DOEPCTL(0)));
1621 /*
1622 * Call s3c_hsotg_handle_outdone here if it was not called from
1623 * GRXSTS_PKTSTS_OUTDONE. That is, if the core didn't
1624 @@ -1664,7 +1664,7 @@ static void s3c_hsotg_handle_rx(struct d
1625 dev_dbg(hsotg->dev,
1626 "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1627 s3c_hsotg_read_frameno(hsotg),
1628 - readl(hsotg->regs + DOEPCTL(0)));
1629 + dwc2_readl(hsotg->regs + DOEPCTL(0)));
1630
1631 WARN_ON(hsotg->ep0_state != DWC2_EP0_SETUP);
1632
1633 @@ -1743,15 +1743,15 @@ static void s3c_hsotg_set_ep_maxpacket(s
1634 }
1635
1636 if (dir_in) {
1637 - reg = readl(regs + DIEPCTL(ep));
1638 + reg = dwc2_readl(regs + DIEPCTL(ep));
1639 reg &= ~DXEPCTL_MPS_MASK;
1640 reg |= mpsval;
1641 - writel(reg, regs + DIEPCTL(ep));
1642 + dwc2_writel(reg, regs + DIEPCTL(ep));
1643 } else {
1644 - reg = readl(regs + DOEPCTL(ep));
1645 + reg = dwc2_readl(regs + DOEPCTL(ep));
1646 reg &= ~DXEPCTL_MPS_MASK;
1647 reg |= mpsval;
1648 - writel(reg, regs + DOEPCTL(ep));
1649 + dwc2_writel(reg, regs + DOEPCTL(ep));
1650 }
1651
1652 return;
1653 @@ -1770,14 +1770,14 @@ static void s3c_hsotg_txfifo_flush(struc
1654 int timeout;
1655 int val;
1656
1657 - writel(GRSTCTL_TXFNUM(idx) | GRSTCTL_TXFFLSH,
1658 + dwc2_writel(GRSTCTL_TXFNUM(idx) | GRSTCTL_TXFFLSH,
1659 hsotg->regs + GRSTCTL);
1660
1661 /* wait until the fifo is flushed */
1662 timeout = 100;
1663
1664 while (1) {
1665 - val = readl(hsotg->regs + GRSTCTL);
1666 + val = dwc2_readl(hsotg->regs + GRSTCTL);
1667
1668 if ((val & (GRSTCTL_TXFFLSH)) == 0)
1669 break;
1670 @@ -1838,7 +1838,7 @@ static void s3c_hsotg_complete_in(struct
1671 struct s3c_hsotg_ep *hs_ep)
1672 {
1673 struct s3c_hsotg_req *hs_req = hs_ep->req;
1674 - u32 epsize = readl(hsotg->regs + DIEPTSIZ(hs_ep->index));
1675 + u32 epsize = dwc2_readl(hsotg->regs + DIEPTSIZ(hs_ep->index));
1676 int size_left, size_done;
1677
1678 if (!hs_req) {
1679 @@ -1929,11 +1929,11 @@ static void s3c_hsotg_epint(struct dwc2_
1680 u32 ints;
1681 u32 ctrl;
1682
1683 - ints = readl(hsotg->regs + epint_reg);
1684 - ctrl = readl(hsotg->regs + epctl_reg);
1685 + ints = dwc2_readl(hsotg->regs + epint_reg);
1686 + ctrl = dwc2_readl(hsotg->regs + epctl_reg);
1687
1688 /* Clear endpoint interrupts */
1689 - writel(ints, hsotg->regs + epint_reg);
1690 + dwc2_writel(ints, hsotg->regs + epint_reg);
1691
1692 if (!hs_ep) {
1693 dev_err(hsotg->dev, "%s:Interrupt for unconfigured ep%d(%s)\n",
1694 @@ -1954,13 +1954,13 @@ static void s3c_hsotg_epint(struct dwc2_
1695 ctrl |= DXEPCTL_SETEVENFR;
1696 else
1697 ctrl |= DXEPCTL_SETODDFR;
1698 - writel(ctrl, hsotg->regs + epctl_reg);
1699 + dwc2_writel(ctrl, hsotg->regs + epctl_reg);
1700 }
1701
1702 dev_dbg(hsotg->dev,
1703 "%s: XferCompl: DxEPCTL=0x%08x, DXEPTSIZ=%08x\n",
1704 - __func__, readl(hsotg->regs + epctl_reg),
1705 - readl(hsotg->regs + epsiz_reg));
1706 + __func__, dwc2_readl(hsotg->regs + epctl_reg),
1707 + dwc2_readl(hsotg->regs + epsiz_reg));
1708
1709 /*
1710 * we get OutDone from the FIFO, so we only need to look
1711 @@ -1985,16 +1985,16 @@ static void s3c_hsotg_epint(struct dwc2_
1712 dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__);
1713
1714 if (dir_in) {
1715 - int epctl = readl(hsotg->regs + epctl_reg);
1716 + int epctl = dwc2_readl(hsotg->regs + epctl_reg);
1717
1718 s3c_hsotg_txfifo_flush(hsotg, hs_ep->fifo_index);
1719
1720 if ((epctl & DXEPCTL_STALL) &&
1721 (epctl & DXEPCTL_EPTYPE_BULK)) {
1722 - int dctl = readl(hsotg->regs + DCTL);
1723 + int dctl = dwc2_readl(hsotg->regs + DCTL);
1724
1725 dctl |= DCTL_CGNPINNAK;
1726 - writel(dctl, hsotg->regs + DCTL);
1727 + dwc2_writel(dctl, hsotg->regs + DCTL);
1728 }
1729 }
1730 }
1731 @@ -2056,7 +2056,7 @@ static void s3c_hsotg_epint(struct dwc2_
1732 */
1733 static void s3c_hsotg_irq_enumdone(struct dwc2_hsotg *hsotg)
1734 {
1735 - u32 dsts = readl(hsotg->regs + DSTS);
1736 + u32 dsts = dwc2_readl(hsotg->regs + DSTS);
1737 int ep0_mps = 0, ep_mps = 8;
1738
1739 /*
1740 @@ -2123,8 +2123,8 @@ static void s3c_hsotg_irq_enumdone(struc
1741 s3c_hsotg_enqueue_setup(hsotg);
1742
1743 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
1744 - readl(hsotg->regs + DIEPCTL0),
1745 - readl(hsotg->regs + DOEPCTL0));
1746 + dwc2_readl(hsotg->regs + DIEPCTL0),
1747 + dwc2_readl(hsotg->regs + DOEPCTL0));
1748 }
1749
1750 /**
1751 @@ -2151,7 +2151,7 @@ static void kill_all_requests(struct dwc
1752
1753 if (!hsotg->dedicated_fifos)
1754 return;
1755 - size = (readl(hsotg->regs + DTXFSTS(ep->index)) & 0xffff) * 4;
1756 + size = (dwc2_readl(hsotg->regs + DTXFSTS(ep->index)) & 0xffff) * 4;
1757 if (size < ep->fifo_size)
1758 s3c_hsotg_txfifo_flush(hsotg, ep->fifo_index);
1759 }
1760 @@ -2236,11 +2236,11 @@ static int s3c_hsotg_corereset(struct dw
1761 dev_dbg(hsotg->dev, "resetting core\n");
1762
1763 /* issue soft reset */
1764 - writel(GRSTCTL_CSFTRST, hsotg->regs + GRSTCTL);
1765 + dwc2_writel(GRSTCTL_CSFTRST, hsotg->regs + GRSTCTL);
1766
1767 timeout = 10000;
1768 do {
1769 - grstctl = readl(hsotg->regs + GRSTCTL);
1770 + grstctl = dwc2_readl(hsotg->regs + GRSTCTL);
1771 } while ((grstctl & GRSTCTL_CSFTRST) && timeout-- > 0);
1772
1773 if (grstctl & GRSTCTL_CSFTRST) {
1774 @@ -2251,7 +2251,7 @@ static int s3c_hsotg_corereset(struct dw
1775 timeout = 10000;
1776
1777 while (1) {
1778 - u32 grstctl = readl(hsotg->regs + GRSTCTL);
1779 + u32 grstctl = dwc2_readl(hsotg->regs + GRSTCTL);
1780
1781 if (timeout-- < 0) {
1782 dev_info(hsotg->dev,
1783 @@ -2291,7 +2291,7 @@ void s3c_hsotg_core_init_disconnected(st
1784
1785 /* set the PLL on, remove the HNP/SRP and set the PHY */
1786 val = (hsotg->phyif == GUSBCFG_PHYIF8) ? 9 : 5;
1787 - writel(hsotg->phyif | GUSBCFG_TOUTCAL(7) |
1788 + dwc2_writel(hsotg->phyif | GUSBCFG_TOUTCAL(7) |
1789 (val << GUSBCFG_USBTRDTIM_SHIFT), hsotg->regs + GUSBCFG);
1790
1791 s3c_hsotg_init_fifo(hsotg);
1792 @@ -2299,15 +2299,15 @@ void s3c_hsotg_core_init_disconnected(st
1793 if (!is_usb_reset)
1794 __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON);
1795
1796 - writel(DCFG_EPMISCNT(1) | DCFG_DEVSPD_HS, hsotg->regs + DCFG);
1797 + dwc2_writel(DCFG_EPMISCNT(1) | DCFG_DEVSPD_HS, hsotg->regs + DCFG);
1798
1799 /* Clear any pending OTG interrupts */
1800 - writel(0xffffffff, hsotg->regs + GOTGINT);
1801 + dwc2_writel(0xffffffff, hsotg->regs + GOTGINT);
1802
1803 /* Clear any pending interrupts */
1804 - writel(0xffffffff, hsotg->regs + GINTSTS);
1805 + dwc2_writel(0xffffffff, hsotg->regs + GINTSTS);
1806
1807 - writel(GINTSTS_ERLYSUSP | GINTSTS_SESSREQINT |
1808 + dwc2_writel(GINTSTS_ERLYSUSP | GINTSTS_SESSREQINT |
1809 GINTSTS_GOUTNAKEFF | GINTSTS_GINNAKEFF |
1810 GINTSTS_CONIDSTSCHNG | GINTSTS_USBRST |
1811 GINTSTS_ENUMDONE | GINTSTS_OTGINT |
1812 @@ -2315,11 +2315,11 @@ void s3c_hsotg_core_init_disconnected(st
1813 hsotg->regs + GINTMSK);
1814
1815 if (using_dma(hsotg))
1816 - writel(GAHBCFG_GLBL_INTR_EN | GAHBCFG_DMA_EN |
1817 + dwc2_writel(GAHBCFG_GLBL_INTR_EN | GAHBCFG_DMA_EN |
1818 (GAHBCFG_HBSTLEN_INCR4 << GAHBCFG_HBSTLEN_SHIFT),
1819 hsotg->regs + GAHBCFG);
1820 else
1821 - writel(((hsotg->dedicated_fifos) ? (GAHBCFG_NP_TXF_EMP_LVL |
1822 + dwc2_writel(((hsotg->dedicated_fifos) ? (GAHBCFG_NP_TXF_EMP_LVL |
1823 GAHBCFG_P_TXF_EMP_LVL) : 0) |
1824 GAHBCFG_GLBL_INTR_EN,
1825 hsotg->regs + GAHBCFG);
1826 @@ -2330,7 +2330,7 @@ void s3c_hsotg_core_init_disconnected(st
1827 * interrupts.
1828 */
1829
1830 - writel(((hsotg->dedicated_fifos && !using_dma(hsotg)) ?
1831 + dwc2_writel(((hsotg->dedicated_fifos && !using_dma(hsotg)) ?
1832 DIEPMSK_TXFIFOEMPTY | DIEPMSK_INTKNTXFEMPMSK : 0) |
1833 DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK |
1834 DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK |
1835 @@ -2341,17 +2341,17 @@ void s3c_hsotg_core_init_disconnected(st
1836 * don't need XferCompl, we get that from RXFIFO in slave mode. In
1837 * DMA mode we may need this.
1838 */
1839 - writel((using_dma(hsotg) ? (DIEPMSK_XFERCOMPLMSK |
1840 + dwc2_writel((using_dma(hsotg) ? (DIEPMSK_XFERCOMPLMSK |
1841 DIEPMSK_TIMEOUTMSK) : 0) |
1842 DOEPMSK_EPDISBLDMSK | DOEPMSK_AHBERRMSK |
1843 DOEPMSK_SETUPMSK,
1844 hsotg->regs + DOEPMSK);
1845
1846 - writel(0, hsotg->regs + DAINTMSK);
1847 + dwc2_writel(0, hsotg->regs + DAINTMSK);
1848
1849 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
1850 - readl(hsotg->regs + DIEPCTL0),
1851 - readl(hsotg->regs + DOEPCTL0));
1852 + dwc2_readl(hsotg->regs + DIEPCTL0),
1853 + dwc2_readl(hsotg->regs + DOEPCTL0));
1854
1855 /* enable in and out endpoint interrupts */
1856 s3c_hsotg_en_gsint(hsotg, GINTSTS_OEPINT | GINTSTS_IEPINT);
1857 @@ -2374,7 +2374,7 @@ void s3c_hsotg_core_init_disconnected(st
1858 __bic32(hsotg->regs + DCTL, DCTL_PWRONPRGDONE);
1859 }
1860
1861 - dev_dbg(hsotg->dev, "DCTL=0x%08x\n", readl(hsotg->regs + DCTL));
1862 + dev_dbg(hsotg->dev, "DCTL=0x%08x\n", dwc2_readl(hsotg->regs + DCTL));
1863
1864 /*
1865 * DxEPCTL_USBActEp says RO in manual, but seems to be set by
1866 @@ -2382,23 +2382,23 @@ void s3c_hsotg_core_init_disconnected(st
1867 */
1868
1869 /* set to read 1 8byte packet */
1870 - writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
1871 + dwc2_writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
1872 DXEPTSIZ_XFERSIZE(8), hsotg->regs + DOEPTSIZ0);
1873
1874 - writel(s3c_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) |
1875 + dwc2_writel(s3c_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) |
1876 DXEPCTL_CNAK | DXEPCTL_EPENA |
1877 DXEPCTL_USBACTEP,
1878 hsotg->regs + DOEPCTL0);
1879
1880 /* enable, but don't activate EP0in */
1881 - writel(s3c_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) |
1882 + dwc2_writel(s3c_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) |
1883 DXEPCTL_USBACTEP, hsotg->regs + DIEPCTL0);
1884
1885 s3c_hsotg_enqueue_setup(hsotg);
1886
1887 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
1888 - readl(hsotg->regs + DIEPCTL0),
1889 - readl(hsotg->regs + DOEPCTL0));
1890 + dwc2_readl(hsotg->regs + DIEPCTL0),
1891 + dwc2_readl(hsotg->regs + DOEPCTL0));
1892
1893 /* clear global NAKs */
1894 val = DCTL_CGOUTNAK | DCTL_CGNPINNAK;
1895 @@ -2438,8 +2438,8 @@ static irqreturn_t s3c_hsotg_irq(int irq
1896
1897 spin_lock(&hsotg->lock);
1898 irq_retry:
1899 - gintsts = readl(hsotg->regs + GINTSTS);
1900 - gintmsk = readl(hsotg->regs + GINTMSK);
1901 + gintsts = dwc2_readl(hsotg->regs + GINTSTS);
1902 + gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
1903
1904 dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n",
1905 __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count);
1906 @@ -2447,14 +2447,14 @@ irq_retry:
1907 gintsts &= gintmsk;
1908
1909 if (gintsts & GINTSTS_ENUMDONE) {
1910 - writel(GINTSTS_ENUMDONE, hsotg->regs + GINTSTS);
1911 + dwc2_writel(GINTSTS_ENUMDONE, hsotg->regs + GINTSTS);
1912
1913 s3c_hsotg_irq_enumdone(hsotg);
1914 }
1915
1916 if (gintsts & (GINTSTS_OEPINT | GINTSTS_IEPINT)) {
1917 - u32 daint = readl(hsotg->regs + DAINT);
1918 - u32 daintmsk = readl(hsotg->regs + DAINTMSK);
1919 + u32 daint = dwc2_readl(hsotg->regs + DAINT);
1920 + u32 daintmsk = dwc2_readl(hsotg->regs + DAINTMSK);
1921 u32 daint_out, daint_in;
1922 int ep;
1923
1924 @@ -2479,13 +2479,13 @@ irq_retry:
1925
1926 if (gintsts & GINTSTS_USBRST) {
1927
1928 - u32 usb_status = readl(hsotg->regs + GOTGCTL);
1929 + u32 usb_status = dwc2_readl(hsotg->regs + GOTGCTL);
1930
1931 dev_dbg(hsotg->dev, "%s: USBRst\n", __func__);
1932 dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n",
1933 - readl(hsotg->regs + GNPTXSTS));
1934 + dwc2_readl(hsotg->regs + GNPTXSTS));
1935
1936 - writel(GINTSTS_USBRST, hsotg->regs + GINTSTS);
1937 + dwc2_writel(GINTSTS_USBRST, hsotg->regs + GINTSTS);
1938
1939 /* Report disconnection if it is not already done. */
1940 s3c_hsotg_disconnect(hsotg);
1941 @@ -2538,7 +2538,7 @@ irq_retry:
1942
1943 if (gintsts & GINTSTS_ERLYSUSP) {
1944 dev_dbg(hsotg->dev, "GINTSTS_ErlySusp\n");
1945 - writel(GINTSTS_ERLYSUSP, hsotg->regs + GINTSTS);
1946 + dwc2_writel(GINTSTS_ERLYSUSP, hsotg->regs + GINTSTS);
1947 }
1948
1949 /*
1950 @@ -2550,7 +2550,7 @@ irq_retry:
1951 if (gintsts & GINTSTS_GOUTNAKEFF) {
1952 dev_info(hsotg->dev, "GOUTNakEff triggered\n");
1953
1954 - writel(DCTL_CGOUTNAK, hsotg->regs + DCTL);
1955 + dwc2_writel(DCTL_CGOUTNAK, hsotg->regs + DCTL);
1956
1957 s3c_hsotg_dump(hsotg);
1958 }
1959 @@ -2558,7 +2558,7 @@ irq_retry:
1960 if (gintsts & GINTSTS_GINNAKEFF) {
1961 dev_info(hsotg->dev, "GINNakEff triggered\n");
1962
1963 - writel(DCTL_CGNPINNAK, hsotg->regs + DCTL);
1964 + dwc2_writel(DCTL_CGNPINNAK, hsotg->regs + DCTL);
1965
1966 s3c_hsotg_dump(hsotg);
1967 }
1968 @@ -2616,7 +2616,7 @@ static int s3c_hsotg_ep_enable(struct us
1969 /* note, we handle this here instead of s3c_hsotg_set_ep_maxpacket */
1970
1971 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
1972 - epctrl = readl(hsotg->regs + epctrl_reg);
1973 + epctrl = dwc2_readl(hsotg->regs + epctrl_reg);
1974
1975 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n",
1976 __func__, epctrl, epctrl_reg);
1977 @@ -2700,7 +2700,7 @@ static int s3c_hsotg_ep_enable(struct us
1978 for (i = 1; i < hsotg->num_of_eps; ++i) {
1979 if (hsotg->fifo_map & (1<<i))
1980 continue;
1981 - val = readl(hsotg->regs + DPTXFSIZN(i));
1982 + val = dwc2_readl(hsotg->regs + DPTXFSIZN(i));
1983 val = (val >> FIFOSIZE_DEPTH_SHIFT)*4;
1984 if (val < size)
1985 continue;
1986 @@ -2729,9 +2729,9 @@ static int s3c_hsotg_ep_enable(struct us
1987 dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n",
1988 __func__, epctrl);
1989
1990 - writel(epctrl, hsotg->regs + epctrl_reg);
1991 + dwc2_writel(epctrl, hsotg->regs + epctrl_reg);
1992 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x\n",
1993 - __func__, readl(hsotg->regs + epctrl_reg));
1994 + __func__, dwc2_readl(hsotg->regs + epctrl_reg));
1995
1996 /* enable the endpoint interrupt */
1997 s3c_hsotg_ctrl_epint(hsotg, index, dir_in, 1);
1998 @@ -2770,13 +2770,13 @@ static int s3c_hsotg_ep_disable_force(st
1999 hs_ep->fifo_index = 0;
2000 hs_ep->fifo_size = 0;
2001
2002 - ctrl = readl(hsotg->regs + epctrl_reg);
2003 + ctrl = dwc2_readl(hsotg->regs + epctrl_reg);
2004 ctrl &= ~DXEPCTL_EPENA;
2005 ctrl &= ~DXEPCTL_USBACTEP;
2006 ctrl |= DXEPCTL_SNAK;
2007
2008 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
2009 - writel(ctrl, hsotg->regs + epctrl_reg);
2010 + dwc2_writel(ctrl, hsotg->regs + epctrl_reg);
2011
2012 /* disable endpoint interrupts */
2013 s3c_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 0);
2014 @@ -2863,7 +2863,7 @@ static int s3c_hsotg_ep_sethalt(struct u
2015
2016 if (hs_ep->dir_in) {
2017 epreg = DIEPCTL(index);
2018 - epctl = readl(hs->regs + epreg);
2019 + epctl = dwc2_readl(hs->regs + epreg);
2020
2021 if (value) {
2022 epctl |= DXEPCTL_STALL + DXEPCTL_SNAK;
2023 @@ -2876,11 +2876,11 @@ static int s3c_hsotg_ep_sethalt(struct u
2024 xfertype == DXEPCTL_EPTYPE_INTERRUPT)
2025 epctl |= DXEPCTL_SETD0PID;
2026 }
2027 - writel(epctl, hs->regs + epreg);
2028 + dwc2_writel(epctl, hs->regs + epreg);
2029 } else {
2030
2031 epreg = DOEPCTL(index);
2032 - epctl = readl(hs->regs + epreg);
2033 + epctl = dwc2_readl(hs->regs + epreg);
2034
2035 if (value)
2036 epctl |= DXEPCTL_STALL;
2037 @@ -2891,7 +2891,7 @@ static int s3c_hsotg_ep_sethalt(struct u
2038 xfertype == DXEPCTL_EPTYPE_INTERRUPT)
2039 epctl |= DXEPCTL_SETD0PID;
2040 }
2041 - writel(epctl, hs->regs + epreg);
2042 + dwc2_writel(epctl, hs->regs + epreg);
2043 }
2044
2045 hs_ep->halted = value;
2046 @@ -2982,15 +2982,15 @@ static void s3c_hsotg_init(struct dwc2_h
2047 u32 trdtim;
2048 /* unmask subset of endpoint interrupts */
2049
2050 - writel(DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK |
2051 + dwc2_writel(DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK |
2052 DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK,
2053 hsotg->regs + DIEPMSK);
2054
2055 - writel(DOEPMSK_SETUPMSK | DOEPMSK_AHBERRMSK |
2056 + dwc2_writel(DOEPMSK_SETUPMSK | DOEPMSK_AHBERRMSK |
2057 DOEPMSK_EPDISBLDMSK | DOEPMSK_XFERCOMPLMSK,
2058 hsotg->regs + DOEPMSK);
2059
2060 - writel(0, hsotg->regs + DAINTMSK);
2061 + dwc2_writel(0, hsotg->regs + DAINTMSK);
2062
2063 /* Be in disconnected state until gadget is registered */
2064 __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON);
2065 @@ -2998,14 +2998,14 @@ static void s3c_hsotg_init(struct dwc2_h
2066 /* setup fifos */
2067
2068 dev_dbg(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
2069 - readl(hsotg->regs + GRXFSIZ),
2070 - readl(hsotg->regs + GNPTXFSIZ));
2071 + dwc2_readl(hsotg->regs + GRXFSIZ),
2072 + dwc2_readl(hsotg->regs + GNPTXFSIZ));
2073
2074 s3c_hsotg_init_fifo(hsotg);
2075
2076 /* set the PLL on, remove the HNP/SRP and set the PHY */
2077 trdtim = (hsotg->phyif == GUSBCFG_PHYIF8) ? 9 : 5;
2078 - writel(hsotg->phyif | GUSBCFG_TOUTCAL(7) |
2079 + dwc2_writel(hsotg->phyif | GUSBCFG_TOUTCAL(7) |
2080 (trdtim << GUSBCFG_USBTRDTIM_SHIFT),
2081 hsotg->regs + GUSBCFG);
2082
2083 @@ -3275,9 +3275,9 @@ static void s3c_hsotg_initep(struct dwc2
2084 if (using_dma(hsotg)) {
2085 u32 next = DXEPCTL_NEXTEP((epnum + 1) % 15);
2086 if (dir_in)
2087 - writel(next, hsotg->regs + DIEPCTL(epnum));
2088 + dwc2_writel(next, hsotg->regs + DIEPCTL(epnum));
2089 else
2090 - writel(next, hsotg->regs + DOEPCTL(epnum));
2091 + dwc2_writel(next, hsotg->regs + DOEPCTL(epnum));
2092 }
2093 }
2094
2095 @@ -3295,7 +3295,7 @@ static int s3c_hsotg_hw_cfg(struct dwc2_
2096
2097 /* check hardware configuration */
2098
2099 - cfg = readl(hsotg->regs + GHWCFG2);
2100 + cfg = dwc2_readl(hsotg->regs + GHWCFG2);
2101 hsotg->num_of_eps = (cfg >> GHWCFG2_NUM_DEV_EP_SHIFT) & 0xF;
2102 /* Add ep0 */
2103 hsotg->num_of_eps++;
2104 @@ -3307,7 +3307,7 @@ static int s3c_hsotg_hw_cfg(struct dwc2_
2105 /* Same s3c_hsotg_ep is used in both directions for ep0 */
2106 hsotg->eps_out[0] = hsotg->eps_in[0];
2107
2108 - cfg = readl(hsotg->regs + GHWCFG1);
2109 + cfg = dwc2_readl(hsotg->regs + GHWCFG1);
2110 for (i = 1, cfg >>= 2; i < hsotg->num_of_eps; i++, cfg >>= 2) {
2111 ep_type = cfg & 3;
2112 /* Direction in or both */
2113 @@ -3326,10 +3326,10 @@ static int s3c_hsotg_hw_cfg(struct dwc2_
2114 }
2115 }
2116
2117 - cfg = readl(hsotg->regs + GHWCFG3);
2118 + cfg = dwc2_readl(hsotg->regs + GHWCFG3);
2119 hsotg->fifo_mem = (cfg >> GHWCFG3_DFIFO_DEPTH_SHIFT);
2120
2121 - cfg = readl(hsotg->regs + GHWCFG4);
2122 + cfg = dwc2_readl(hsotg->regs + GHWCFG4);
2123 hsotg->dedicated_fifos = (cfg >> GHWCFG4_DED_FIFO_SHIFT) & 1;
2124
2125 dev_info(hsotg->dev, "EPs: %d, %s fifos, %d entries in SPRAM\n",
2126 @@ -3352,19 +3352,19 @@ static void s3c_hsotg_dump(struct dwc2_h
2127 int idx;
2128
2129 dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n",
2130 - readl(regs + DCFG), readl(regs + DCTL),
2131 - readl(regs + DIEPMSK));
2132 + dwc2_readl(regs + DCFG), dwc2_readl(regs + DCTL),
2133 + dwc2_readl(regs + DIEPMSK));
2134
2135 dev_info(dev, "GAHBCFG=0x%08x, GHWCFG1=0x%08x\n",
2136 - readl(regs + GAHBCFG), readl(regs + GHWCFG1));
2137 + dwc2_readl(regs + GAHBCFG), dwc2_readl(regs + GHWCFG1));
2138
2139 dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
2140 - readl(regs + GRXFSIZ), readl(regs + GNPTXFSIZ));
2141 + dwc2_readl(regs + GRXFSIZ), dwc2_readl(regs + GNPTXFSIZ));
2142
2143 /* show periodic fifo settings */
2144
2145 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
2146 - val = readl(regs + DPTXFSIZN(idx));
2147 + val = dwc2_readl(regs + DPTXFSIZN(idx));
2148 dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx,
2149 val >> FIFOSIZE_DEPTH_SHIFT,
2150 val & FIFOSIZE_STARTADDR_MASK);
2151 @@ -3373,21 +3373,21 @@ static void s3c_hsotg_dump(struct dwc2_h
2152 for (idx = 0; idx < hsotg->num_of_eps; idx++) {
2153 dev_info(dev,
2154 "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx,
2155 - readl(regs + DIEPCTL(idx)),
2156 - readl(regs + DIEPTSIZ(idx)),
2157 - readl(regs + DIEPDMA(idx)));
2158 + dwc2_readl(regs + DIEPCTL(idx)),
2159 + dwc2_readl(regs + DIEPTSIZ(idx)),
2160 + dwc2_readl(regs + DIEPDMA(idx)));
2161
2162 - val = readl(regs + DOEPCTL(idx));
2163 + val = dwc2_readl(regs + DOEPCTL(idx));
2164 dev_info(dev,
2165 "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n",
2166 - idx, readl(regs + DOEPCTL(idx)),
2167 - readl(regs + DOEPTSIZ(idx)),
2168 - readl(regs + DOEPDMA(idx)));
2169 + idx, dwc2_readl(regs + DOEPCTL(idx)),
2170 + dwc2_readl(regs + DOEPTSIZ(idx)),
2171 + dwc2_readl(regs + DOEPDMA(idx)));
2172
2173 }
2174
2175 dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n",
2176 - readl(regs + DVBUSDIS), readl(regs + DVBUSPULSE));
2177 + dwc2_readl(regs + DVBUSDIS), dwc2_readl(regs + DVBUSPULSE));
2178 #endif
2179 }
2180
2181 @@ -3443,7 +3443,7 @@ static int testmode_show(struct seq_file
2182 int dctl;
2183
2184 spin_lock_irqsave(&hsotg->lock, flags);
2185 - dctl = readl(hsotg->regs + DCTL);
2186 + dctl = dwc2_readl(hsotg->regs + DCTL);
2187 dctl &= DCTL_TSTCTL_MASK;
2188 dctl >>= DCTL_TSTCTL_SHIFT;
2189 spin_unlock_irqrestore(&hsotg->lock, flags);
2190 @@ -3504,38 +3504,38 @@ static int state_show(struct seq_file *s
2191 int idx;
2192
2193 seq_printf(seq, "DCFG=0x%08x, DCTL=0x%08x, DSTS=0x%08x\n",
2194 - readl(regs + DCFG),
2195 - readl(regs + DCTL),
2196 - readl(regs + DSTS));
2197 + dwc2_readl(regs + DCFG),
2198 + dwc2_readl(regs + DCTL),
2199 + dwc2_readl(regs + DSTS));
2200
2201 seq_printf(seq, "DIEPMSK=0x%08x, DOEPMASK=0x%08x\n",
2202 - readl(regs + DIEPMSK), readl(regs + DOEPMSK));
2203 + dwc2_readl(regs + DIEPMSK), dwc2_readl(regs + DOEPMSK));
2204
2205 seq_printf(seq, "GINTMSK=0x%08x, GINTSTS=0x%08x\n",
2206 - readl(regs + GINTMSK),
2207 - readl(regs + GINTSTS));
2208 + dwc2_readl(regs + GINTMSK),
2209 + dwc2_readl(regs + GINTSTS));
2210
2211 seq_printf(seq, "DAINTMSK=0x%08x, DAINT=0x%08x\n",
2212 - readl(regs + DAINTMSK),
2213 - readl(regs + DAINT));
2214 + dwc2_readl(regs + DAINTMSK),
2215 + dwc2_readl(regs + DAINT));
2216
2217 seq_printf(seq, "GNPTXSTS=0x%08x, GRXSTSR=%08x\n",
2218 - readl(regs + GNPTXSTS),
2219 - readl(regs + GRXSTSR));
2220 + dwc2_readl(regs + GNPTXSTS),
2221 + dwc2_readl(regs + GRXSTSR));
2222
2223 seq_puts(seq, "\nEndpoint status:\n");
2224
2225 for (idx = 0; idx < hsotg->num_of_eps; idx++) {
2226 u32 in, out;
2227
2228 - in = readl(regs + DIEPCTL(idx));
2229 - out = readl(regs + DOEPCTL(idx));
2230 + in = dwc2_readl(regs + DIEPCTL(idx));
2231 + out = dwc2_readl(regs + DOEPCTL(idx));
2232
2233 seq_printf(seq, "ep%d: DIEPCTL=0x%08x, DOEPCTL=0x%08x",
2234 idx, in, out);
2235
2236 - in = readl(regs + DIEPTSIZ(idx));
2237 - out = readl(regs + DOEPTSIZ(idx));
2238 + in = dwc2_readl(regs + DIEPTSIZ(idx));
2239 + out = dwc2_readl(regs + DOEPTSIZ(idx));
2240
2241 seq_printf(seq, ", DIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x",
2242 in, out);
2243 @@ -3575,9 +3575,9 @@ static int fifo_show(struct seq_file *se
2244 int idx;
2245
2246 seq_puts(seq, "Non-periodic FIFOs:\n");
2247 - seq_printf(seq, "RXFIFO: Size %d\n", readl(regs + GRXFSIZ));
2248 + seq_printf(seq, "RXFIFO: Size %d\n", dwc2_readl(regs + GRXFSIZ));
2249
2250 - val = readl(regs + GNPTXFSIZ);
2251 + val = dwc2_readl(regs + GNPTXFSIZ);
2252 seq_printf(seq, "NPTXFIFO: Size %d, Start 0x%08x\n",
2253 val >> FIFOSIZE_DEPTH_SHIFT,
2254 val & FIFOSIZE_DEPTH_MASK);
2255 @@ -3585,7 +3585,7 @@ static int fifo_show(struct seq_file *se
2256 seq_puts(seq, "\nPeriodic TXFIFOs:\n");
2257
2258 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
2259 - val = readl(regs + DPTXFSIZN(idx));
2260 + val = dwc2_readl(regs + DPTXFSIZN(idx));
2261
2262 seq_printf(seq, "\tDPTXFIFO%2d: Size %d, Start 0x%08x\n", idx,
2263 val >> FIFOSIZE_DEPTH_SHIFT,
2264 @@ -3638,20 +3638,20 @@ static int ep_show(struct seq_file *seq,
2265 /* first show the register state */
2266
2267 seq_printf(seq, "\tDIEPCTL=0x%08x, DOEPCTL=0x%08x\n",
2268 - readl(regs + DIEPCTL(index)),
2269 - readl(regs + DOEPCTL(index)));
2270 + dwc2_readl(regs + DIEPCTL(index)),
2271 + dwc2_readl(regs + DOEPCTL(index)));
2272
2273 seq_printf(seq, "\tDIEPDMA=0x%08x, DOEPDMA=0x%08x\n",
2274 - readl(regs + DIEPDMA(index)),
2275 - readl(regs + DOEPDMA(index)));
2276 + dwc2_readl(regs + DIEPDMA(index)),
2277 + dwc2_readl(regs + DOEPDMA(index)));
2278
2279 seq_printf(seq, "\tDIEPINT=0x%08x, DOEPINT=0x%08x\n",
2280 - readl(regs + DIEPINT(index)),
2281 - readl(regs + DOEPINT(index)));
2282 + dwc2_readl(regs + DIEPINT(index)),
2283 + dwc2_readl(regs + DOEPINT(index)));
2284
2285 seq_printf(seq, "\tDIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x\n",
2286 - readl(regs + DIEPTSIZ(index)),
2287 - readl(regs + DOEPTSIZ(index)));
2288 + dwc2_readl(regs + DIEPTSIZ(index)),
2289 + dwc2_readl(regs + DOEPTSIZ(index)));
2290
2291 seq_puts(seq, "\n");
2292 seq_printf(seq, "mps %d\n", ep->ep.maxpacket);
2293 --- a/drivers/usb/dwc2/hcd.c
2294 +++ b/drivers/usb/dwc2/hcd.c
2295 @@ -80,10 +80,10 @@ static void dwc2_dump_channel_info(struc
2296 if (chan == NULL)
2297 return;
2298
2299 - hcchar = readl(hsotg->regs + HCCHAR(chan->hc_num));
2300 - hcsplt = readl(hsotg->regs + HCSPLT(chan->hc_num));
2301 - hctsiz = readl(hsotg->regs + HCTSIZ(chan->hc_num));
2302 - hc_dma = readl(hsotg->regs + HCDMA(chan->hc_num));
2303 + hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
2304 + hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chan->hc_num));
2305 + hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chan->hc_num));
2306 + hc_dma = dwc2_readl(hsotg->regs + HCDMA(chan->hc_num));
2307
2308 dev_dbg(hsotg->dev, " Assigned to channel %p:\n", chan);
2309 dev_dbg(hsotg->dev, " hcchar 0x%08x, hcsplt 0x%08x\n",
2310 @@ -207,7 +207,7 @@ void dwc2_hcd_start(struct dwc2_hsotg *h
2311 */
2312 hprt0 = dwc2_read_hprt0(hsotg);
2313 hprt0 |= HPRT0_RST;
2314 - writel(hprt0, hsotg->regs + HPRT0);
2315 + dwc2_writel(hprt0, hsotg->regs + HPRT0);
2316 }
2317
2318 queue_delayed_work(hsotg->wq_otg, &hsotg->start_work,
2319 @@ -228,11 +228,11 @@ static void dwc2_hcd_cleanup_channels(st
2320 channel = hsotg->hc_ptr_array[i];
2321 if (!list_empty(&channel->hc_list_entry))
2322 continue;
2323 - hcchar = readl(hsotg->regs + HCCHAR(i));
2324 + hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
2325 if (hcchar & HCCHAR_CHENA) {
2326 hcchar &= ~(HCCHAR_CHENA | HCCHAR_EPDIR);
2327 hcchar |= HCCHAR_CHDIS;
2328 - writel(hcchar, hsotg->regs + HCCHAR(i));
2329 + dwc2_writel(hcchar, hsotg->regs + HCCHAR(i));
2330 }
2331 }
2332 }
2333 @@ -241,11 +241,11 @@ static void dwc2_hcd_cleanup_channels(st
2334 channel = hsotg->hc_ptr_array[i];
2335 if (!list_empty(&channel->hc_list_entry))
2336 continue;
2337 - hcchar = readl(hsotg->regs + HCCHAR(i));
2338 + hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
2339 if (hcchar & HCCHAR_CHENA) {
2340 /* Halt the channel */
2341 hcchar |= HCCHAR_CHDIS;
2342 - writel(hcchar, hsotg->regs + HCCHAR(i));
2343 + dwc2_writel(hcchar, hsotg->regs + HCCHAR(i));
2344 }
2345
2346 dwc2_hc_cleanup(hsotg, channel);
2347 @@ -287,11 +287,11 @@ void dwc2_hcd_disconnect(struct dwc2_hso
2348 * interrupt mask and status bits and disabling subsequent host
2349 * channel interrupts.
2350 */
2351 - intr = readl(hsotg->regs + GINTMSK);
2352 + intr = dwc2_readl(hsotg->regs + GINTMSK);
2353 intr &= ~(GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT);
2354 - writel(intr, hsotg->regs + GINTMSK);
2355 + dwc2_writel(intr, hsotg->regs + GINTMSK);
2356 intr = GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT;
2357 - writel(intr, hsotg->regs + GINTSTS);
2358 + dwc2_writel(intr, hsotg->regs + GINTSTS);
2359
2360 /*
2361 * Turn off the vbus power only if the core has transitioned to device
2362 @@ -301,7 +301,7 @@ void dwc2_hcd_disconnect(struct dwc2_hso
2363 if (dwc2_is_device_mode(hsotg)) {
2364 if (hsotg->op_state != OTG_STATE_A_SUSPEND) {
2365 dev_dbg(hsotg->dev, "Disconnect: PortPower off\n");
2366 - writel(0, hsotg->regs + HPRT0);
2367 + dwc2_writel(0, hsotg->regs + HPRT0);
2368 }
2369
2370 dwc2_disable_host_interrupts(hsotg);
2371 @@ -354,7 +354,7 @@ void dwc2_hcd_stop(struct dwc2_hsotg *hs
2372
2373 /* Turn off the vbus power */
2374 dev_dbg(hsotg->dev, "PortPower off\n");
2375 - writel(0, hsotg->regs + HPRT0);
2376 + dwc2_writel(0, hsotg->regs + HPRT0);
2377 }
2378
2379 static int dwc2_hcd_urb_enqueue(struct dwc2_hsotg *hsotg,
2380 @@ -379,7 +379,7 @@ static int dwc2_hcd_urb_enqueue(struct d
2381 if ((dev_speed == USB_SPEED_LOW) &&
2382 (hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) &&
2383 (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI)) {
2384 - u32 hprt0 = readl(hsotg->regs + HPRT0);
2385 + u32 hprt0 = dwc2_readl(hsotg->regs + HPRT0);
2386 u32 prtspd = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
2387
2388 if (prtspd == HPRT0_SPD_FULL_SPEED)
2389 @@ -401,7 +401,7 @@ static int dwc2_hcd_urb_enqueue(struct d
2390 return retval;
2391 }
2392
2393 - intr_mask = readl(hsotg->regs + GINTMSK);
2394 + intr_mask = dwc2_readl(hsotg->regs + GINTMSK);
2395 if (!(intr_mask & GINTSTS_SOF)) {
2396 enum dwc2_transaction_type tr_type;
2397
2398 @@ -1069,7 +1069,7 @@ static void dwc2_process_periodic_channe
2399 if (dbg_perio())
2400 dev_vdbg(hsotg->dev, "Queue periodic transactions\n");
2401
2402 - tx_status = readl(hsotg->regs + HPTXSTS);
2403 + tx_status = dwc2_readl(hsotg->regs + HPTXSTS);
2404 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
2405 TXSTS_QSPCAVAIL_SHIFT;
2406 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
2407 @@ -1084,7 +1084,7 @@ static void dwc2_process_periodic_channe
2408
2409 qh_ptr = hsotg->periodic_sched_assigned.next;
2410 while (qh_ptr != &hsotg->periodic_sched_assigned) {
2411 - tx_status = readl(hsotg->regs + HPTXSTS);
2412 + tx_status = dwc2_readl(hsotg->regs + HPTXSTS);
2413 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
2414 TXSTS_QSPCAVAIL_SHIFT;
2415 if (qspcavail == 0) {
2416 @@ -1144,7 +1144,7 @@ static void dwc2_process_periodic_channe
2417 }
2418
2419 if (hsotg->core_params->dma_enable <= 0) {
2420 - tx_status = readl(hsotg->regs + HPTXSTS);
2421 + tx_status = dwc2_readl(hsotg->regs + HPTXSTS);
2422 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
2423 TXSTS_QSPCAVAIL_SHIFT;
2424 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
2425 @@ -1167,9 +1167,9 @@ static void dwc2_process_periodic_channe
2426 * level to ensure that new requests are loaded as
2427 * soon as possible.)
2428 */
2429 - gintmsk = readl(hsotg->regs + GINTMSK);
2430 + gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
2431 gintmsk |= GINTSTS_PTXFEMP;
2432 - writel(gintmsk, hsotg->regs + GINTMSK);
2433 + dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
2434 } else {
2435 /*
2436 * Disable the Tx FIFO empty interrupt since there are
2437 @@ -1178,9 +1178,9 @@ static void dwc2_process_periodic_channe
2438 * handlers to queue more transactions as transfer
2439 * states change.
2440 */
2441 - gintmsk = readl(hsotg->regs + GINTMSK);
2442 + gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
2443 gintmsk &= ~GINTSTS_PTXFEMP;
2444 - writel(gintmsk, hsotg->regs + GINTMSK);
2445 + dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
2446 }
2447 }
2448 }
2449 @@ -1209,7 +1209,7 @@ static void dwc2_process_non_periodic_ch
2450
2451 dev_vdbg(hsotg->dev, "Queue non-periodic transactions\n");
2452
2453 - tx_status = readl(hsotg->regs + GNPTXSTS);
2454 + tx_status = dwc2_readl(hsotg->regs + GNPTXSTS);
2455 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
2456 TXSTS_QSPCAVAIL_SHIFT;
2457 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
2458 @@ -1232,7 +1232,7 @@ static void dwc2_process_non_periodic_ch
2459 * available in the request queue or the Tx FIFO
2460 */
2461 do {
2462 - tx_status = readl(hsotg->regs + GNPTXSTS);
2463 + tx_status = dwc2_readl(hsotg->regs + GNPTXSTS);
2464 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
2465 TXSTS_QSPCAVAIL_SHIFT;
2466 if (hsotg->core_params->dma_enable <= 0 && qspcavail == 0) {
2467 @@ -1269,7 +1269,7 @@ next:
2468 } while (hsotg->non_periodic_qh_ptr != orig_qh_ptr);
2469
2470 if (hsotg->core_params->dma_enable <= 0) {
2471 - tx_status = readl(hsotg->regs + GNPTXSTS);
2472 + tx_status = dwc2_readl(hsotg->regs + GNPTXSTS);
2473 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
2474 TXSTS_QSPCAVAIL_SHIFT;
2475 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
2476 @@ -1289,9 +1289,9 @@ next:
2477 * level to ensure that new requests are loaded as
2478 * soon as possible.)
2479 */
2480 - gintmsk = readl(hsotg->regs + GINTMSK);
2481 + gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
2482 gintmsk |= GINTSTS_NPTXFEMP;
2483 - writel(gintmsk, hsotg->regs + GINTMSK);
2484 + dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
2485 } else {
2486 /*
2487 * Disable the Tx FIFO empty interrupt since there are
2488 @@ -1300,9 +1300,9 @@ next:
2489 * handlers to queue more transactions as transfer
2490 * states change.
2491 */
2492 - gintmsk = readl(hsotg->regs + GINTMSK);
2493 + gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
2494 gintmsk &= ~GINTSTS_NPTXFEMP;
2495 - writel(gintmsk, hsotg->regs + GINTMSK);
2496 + dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
2497 }
2498 }
2499 }
2500 @@ -1340,10 +1340,10 @@ void dwc2_hcd_queue_transactions(struct
2501 * Ensure NP Tx FIFO empty interrupt is disabled when
2502 * there are no non-periodic transfers to process
2503 */
2504 - u32 gintmsk = readl(hsotg->regs + GINTMSK);
2505 + u32 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
2506
2507 gintmsk &= ~GINTSTS_NPTXFEMP;
2508 - writel(gintmsk, hsotg->regs + GINTMSK);
2509 + dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
2510 }
2511 }
2512 }
2513 @@ -1357,7 +1357,7 @@ static void dwc2_conn_id_status_change(s
2514
2515 dev_dbg(hsotg->dev, "%s()\n", __func__);
2516
2517 - gotgctl = readl(hsotg->regs + GOTGCTL);
2518 + gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
2519 dev_dbg(hsotg->dev, "gotgctl=%0x\n", gotgctl);
2520 dev_dbg(hsotg->dev, "gotgctl.b.conidsts=%d\n",
2521 !!(gotgctl & GOTGCTL_CONID_B));
2522 @@ -1420,9 +1420,9 @@ static void dwc2_wakeup_detected(unsigne
2523 hprt0 = dwc2_read_hprt0(hsotg);
2524 dev_dbg(hsotg->dev, "Resume: HPRT0=%0x\n", hprt0);
2525 hprt0 &= ~HPRT0_RES;
2526 - writel(hprt0, hsotg->regs + HPRT0);
2527 + dwc2_writel(hprt0, hsotg->regs + HPRT0);
2528 dev_dbg(hsotg->dev, "Clear Resume: HPRT0=%0x\n",
2529 - readl(hsotg->regs + HPRT0));
2530 + dwc2_readl(hsotg->regs + HPRT0));
2531
2532 dwc2_hcd_rem_wakeup(hsotg);
2533
2534 @@ -1450,30 +1450,30 @@ static void dwc2_port_suspend(struct dwc
2535 spin_lock_irqsave(&hsotg->lock, flags);
2536
2537 if (windex == hsotg->otg_port && dwc2_host_is_b_hnp_enabled(hsotg)) {
2538 - gotgctl = readl(hsotg->regs + GOTGCTL);
2539 + gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
2540 gotgctl |= GOTGCTL_HSTSETHNPEN;
2541 - writel(gotgctl, hsotg->regs + GOTGCTL);
2542 + dwc2_writel(gotgctl, hsotg->regs + GOTGCTL);
2543 hsotg->op_state = OTG_STATE_A_SUSPEND;
2544 }
2545
2546 hprt0 = dwc2_read_hprt0(hsotg);
2547 hprt0 |= HPRT0_SUSP;
2548 - writel(hprt0, hsotg->regs + HPRT0);
2549 + dwc2_writel(hprt0, hsotg->regs + HPRT0);
2550
2551 /* Update lx_state */
2552 hsotg->lx_state = DWC2_L2;
2553
2554 /* Suspend the Phy Clock */
2555 - pcgctl = readl(hsotg->regs + PCGCTL);
2556 + pcgctl = dwc2_readl(hsotg->regs + PCGCTL);
2557 pcgctl |= PCGCTL_STOPPCLK;
2558 - writel(pcgctl, hsotg->regs + PCGCTL);
2559 + dwc2_writel(pcgctl, hsotg->regs + PCGCTL);
2560 udelay(10);
2561
2562 /* For HNP the bus must be suspended for at least 200ms */
2563 if (dwc2_host_is_b_hnp_enabled(hsotg)) {
2564 - pcgctl = readl(hsotg->regs + PCGCTL);
2565 + pcgctl = dwc2_readl(hsotg->regs + PCGCTL);
2566 pcgctl &= ~PCGCTL_STOPPCLK;
2567 - writel(pcgctl, hsotg->regs + PCGCTL);
2568 + dwc2_writel(pcgctl, hsotg->regs + PCGCTL);
2569
2570 spin_unlock_irqrestore(&hsotg->lock, flags);
2571
2572 @@ -1522,23 +1522,23 @@ static int dwc2_hcd_hub_control(struct d
2573 "ClearPortFeature USB_PORT_FEAT_ENABLE\n");
2574 hprt0 = dwc2_read_hprt0(hsotg);
2575 hprt0 |= HPRT0_ENA;
2576 - writel(hprt0, hsotg->regs + HPRT0);
2577 + dwc2_writel(hprt0, hsotg->regs + HPRT0);
2578 break;
2579
2580 case USB_PORT_FEAT_SUSPEND:
2581 dev_dbg(hsotg->dev,
2582 "ClearPortFeature USB_PORT_FEAT_SUSPEND\n");
2583 - writel(0, hsotg->regs + PCGCTL);
2584 + dwc2_writel(0, hsotg->regs + PCGCTL);
2585 usleep_range(20000, 40000);
2586
2587 hprt0 = dwc2_read_hprt0(hsotg);
2588 hprt0 |= HPRT0_RES;
2589 - writel(hprt0, hsotg->regs + HPRT0);
2590 + dwc2_writel(hprt0, hsotg->regs + HPRT0);
2591 hprt0 &= ~HPRT0_SUSP;
2592 msleep(USB_RESUME_TIMEOUT);
2593
2594 hprt0 &= ~HPRT0_RES;
2595 - writel(hprt0, hsotg->regs + HPRT0);
2596 + dwc2_writel(hprt0, hsotg->regs + HPRT0);
2597 break;
2598
2599 case USB_PORT_FEAT_POWER:
2600 @@ -1546,7 +1546,7 @@ static int dwc2_hcd_hub_control(struct d
2601 "ClearPortFeature USB_PORT_FEAT_POWER\n");
2602 hprt0 = dwc2_read_hprt0(hsotg);
2603 hprt0 &= ~HPRT0_PWR;
2604 - writel(hprt0, hsotg->regs + HPRT0);
2605 + dwc2_writel(hprt0, hsotg->regs + HPRT0);
2606 break;
2607
2608 case USB_PORT_FEAT_INDICATOR:
2609 @@ -1667,7 +1667,7 @@ static int dwc2_hcd_hub_control(struct d
2610 break;
2611 }
2612
2613 - hprt0 = readl(hsotg->regs + HPRT0);
2614 + hprt0 = dwc2_readl(hsotg->regs + HPRT0);
2615 dev_vdbg(hsotg->dev, " HPRT0: 0x%08x\n", hprt0);
2616
2617 if (hprt0 & HPRT0_CONNSTS)
2618 @@ -1732,18 +1732,18 @@ static int dwc2_hcd_hub_control(struct d
2619 "SetPortFeature - USB_PORT_FEAT_POWER\n");
2620 hprt0 = dwc2_read_hprt0(hsotg);
2621 hprt0 |= HPRT0_PWR;
2622 - writel(hprt0, hsotg->regs + HPRT0);
2623 + dwc2_writel(hprt0, hsotg->regs + HPRT0);
2624 break;
2625
2626 case USB_PORT_FEAT_RESET:
2627 hprt0 = dwc2_read_hprt0(hsotg);
2628 dev_dbg(hsotg->dev,
2629 "SetPortFeature - USB_PORT_FEAT_RESET\n");
2630 - pcgctl = readl(hsotg->regs + PCGCTL);
2631 + pcgctl = dwc2_readl(hsotg->regs + PCGCTL);
2632 pcgctl &= ~(PCGCTL_ENBL_SLEEP_GATING | PCGCTL_STOPPCLK);
2633 - writel(pcgctl, hsotg->regs + PCGCTL);
2634 + dwc2_writel(pcgctl, hsotg->regs + PCGCTL);
2635 /* ??? Original driver does this */
2636 - writel(0, hsotg->regs + PCGCTL);
2637 + dwc2_writel(0, hsotg->regs + PCGCTL);
2638
2639 hprt0 = dwc2_read_hprt0(hsotg);
2640 /* Clear suspend bit if resetting from suspend state */
2641 @@ -1758,13 +1758,13 @@ static int dwc2_hcd_hub_control(struct d
2642 hprt0 |= HPRT0_PWR | HPRT0_RST;
2643 dev_dbg(hsotg->dev,
2644 "In host mode, hprt0=%08x\n", hprt0);
2645 - writel(hprt0, hsotg->regs + HPRT0);
2646 + dwc2_writel(hprt0, hsotg->regs + HPRT0);
2647 }
2648
2649 /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */
2650 usleep_range(50000, 70000);
2651 hprt0 &= ~HPRT0_RST;
2652 - writel(hprt0, hsotg->regs + HPRT0);
2653 + dwc2_writel(hprt0, hsotg->regs + HPRT0);
2654 hsotg->lx_state = DWC2_L0; /* Now back to On state */
2655 break;
2656
2657 @@ -1828,7 +1828,7 @@ static int dwc2_hcd_is_status_changed(st
2658
2659 int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg)
2660 {
2661 - u32 hfnum = readl(hsotg->regs + HFNUM);
2662 + u32 hfnum = dwc2_readl(hsotg->regs + HFNUM);
2663
2664 #ifdef DWC2_DEBUG_SOF
2665 dev_vdbg(hsotg->dev, "DWC OTG HCD GET FRAME NUMBER %d\n",
2666 @@ -1931,11 +1931,11 @@ void dwc2_hcd_dump_state(struct dwc2_hso
2667 if (chan->xfer_started) {
2668 u32 hfnum, hcchar, hctsiz, hcint, hcintmsk;
2669
2670 - hfnum = readl(hsotg->regs + HFNUM);
2671 - hcchar = readl(hsotg->regs + HCCHAR(i));
2672 - hctsiz = readl(hsotg->regs + HCTSIZ(i));
2673 - hcint = readl(hsotg->regs + HCINT(i));
2674 - hcintmsk = readl(hsotg->regs + HCINTMSK(i));
2675 + hfnum = dwc2_readl(hsotg->regs + HFNUM);
2676 + hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
2677 + hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(i));
2678 + hcint = dwc2_readl(hsotg->regs + HCINT(i));
2679 + hcintmsk = dwc2_readl(hsotg->regs + HCINTMSK(i));
2680 dev_dbg(hsotg->dev, " hfnum: 0x%08x\n", hfnum);
2681 dev_dbg(hsotg->dev, " hcchar: 0x%08x\n", hcchar);
2682 dev_dbg(hsotg->dev, " hctsiz: 0x%08x\n", hctsiz);
2683 @@ -1983,12 +1983,12 @@ void dwc2_hcd_dump_state(struct dwc2_hso
2684 dev_dbg(hsotg->dev, " periodic_channels: %d\n",
2685 hsotg->periodic_channels);
2686 dev_dbg(hsotg->dev, " periodic_usecs: %d\n", hsotg->periodic_usecs);
2687 - np_tx_status = readl(hsotg->regs + GNPTXSTS);
2688 + np_tx_status = dwc2_readl(hsotg->regs + GNPTXSTS);
2689 dev_dbg(hsotg->dev, " NP Tx Req Queue Space Avail: %d\n",
2690 (np_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT);
2691 dev_dbg(hsotg->dev, " NP Tx FIFO Space Avail: %d\n",
2692 (np_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT);
2693 - p_tx_status = readl(hsotg->regs + HPTXSTS);
2694 + p_tx_status = dwc2_readl(hsotg->regs + HPTXSTS);
2695 dev_dbg(hsotg->dev, " P Tx Req Queue Space Avail: %d\n",
2696 (p_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT);
2697 dev_dbg(hsotg->dev, " P Tx FIFO Space Avail: %d\n",
2698 @@ -2252,7 +2252,7 @@ static void dwc2_hcd_reset_func(struct w
2699 dev_dbg(hsotg->dev, "USB RESET function called\n");
2700 hprt0 = dwc2_read_hprt0(hsotg);
2701 hprt0 &= ~HPRT0_RST;
2702 - writel(hprt0, hsotg->regs + HPRT0);
2703 + dwc2_writel(hprt0, hsotg->regs + HPRT0);
2704 hsotg->flags.b.port_reset_change = 1;
2705 }
2706
2707 @@ -2729,17 +2729,17 @@ static void dwc2_hcd_free(struct dwc2_hs
2708 hsotg->status_buf = NULL;
2709 }
2710
2711 - ahbcfg = readl(hsotg->regs + GAHBCFG);
2712 + ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG);
2713
2714 /* Disable all interrupts */
2715 ahbcfg &= ~GAHBCFG_GLBL_INTR_EN;
2716 - writel(ahbcfg, hsotg->regs + GAHBCFG);
2717 - writel(0, hsotg->regs + GINTMSK);
2718 + dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG);
2719 + dwc2_writel(0, hsotg->regs + GINTMSK);
2720
2721 if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a) {
2722 - dctl = readl(hsotg->regs + DCTL);
2723 + dctl = dwc2_readl(hsotg->regs + DCTL);
2724 dctl |= DCTL_SFTDISCON;
2725 - writel(dctl, hsotg->regs + DCTL);
2726 + dwc2_writel(dctl, hsotg->regs + DCTL);
2727 }
2728
2729 if (hsotg->wq_otg) {
2730 @@ -2805,7 +2805,7 @@ int dwc2_hcd_init(struct dwc2_hsotg *hso
2731
2732 retval = -ENOMEM;
2733
2734 - hcfg = readl(hsotg->regs + HCFG);
2735 + hcfg = dwc2_readl(hsotg->regs + HCFG);
2736 dev_dbg(hsotg->dev, "hcfg=%08x\n", hcfg);
2737
2738 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
2739 --- a/drivers/usb/dwc2/hcd_ddma.c
2740 +++ b/drivers/usb/dwc2/hcd_ddma.c
2741 @@ -169,19 +169,19 @@ static void dwc2_per_sched_enable(struct
2742
2743 spin_lock_irqsave(&hsotg->lock, flags);
2744
2745 - hcfg = readl(hsotg->regs + HCFG);
2746 + hcfg = dwc2_readl(hsotg->regs + HCFG);
2747 if (hcfg & HCFG_PERSCHEDENA) {
2748 /* already enabled */
2749 spin_unlock_irqrestore(&hsotg->lock, flags);
2750 return;
2751 }
2752
2753 - writel(hsotg->frame_list_dma, hsotg->regs + HFLBADDR);
2754 + dwc2_writel(hsotg->frame_list_dma, hsotg->regs + HFLBADDR);
2755
2756 hcfg &= ~HCFG_FRLISTEN_MASK;
2757 hcfg |= fr_list_en | HCFG_PERSCHEDENA;
2758 dev_vdbg(hsotg->dev, "Enabling Periodic schedule\n");
2759 - writel(hcfg, hsotg->regs + HCFG);
2760 + dwc2_writel(hcfg, hsotg->regs + HCFG);
2761
2762 spin_unlock_irqrestore(&hsotg->lock, flags);
2763 }
2764 @@ -193,7 +193,7 @@ static void dwc2_per_sched_disable(struc
2765
2766 spin_lock_irqsave(&hsotg->lock, flags);
2767
2768 - hcfg = readl(hsotg->regs + HCFG);
2769 + hcfg = dwc2_readl(hsotg->regs + HCFG);
2770 if (!(hcfg & HCFG_PERSCHEDENA)) {
2771 /* already disabled */
2772 spin_unlock_irqrestore(&hsotg->lock, flags);
2773 @@ -202,7 +202,7 @@ static void dwc2_per_sched_disable(struc
2774
2775 hcfg &= ~HCFG_PERSCHEDENA;
2776 dev_vdbg(hsotg->dev, "Disabling Periodic schedule\n");
2777 - writel(hcfg, hsotg->regs + HCFG);
2778 + dwc2_writel(hcfg, hsotg->regs + HCFG);
2779
2780 spin_unlock_irqrestore(&hsotg->lock, flags);
2781 }
2782 --- a/drivers/usb/dwc2/hcd.h
2783 +++ b/drivers/usb/dwc2/hcd.h
2784 @@ -371,10 +371,10 @@ static inline struct usb_hcd *dwc2_hsotg
2785 */
2786 static inline void disable_hc_int(struct dwc2_hsotg *hsotg, int chnum, u32 intr)
2787 {
2788 - u32 mask = readl(hsotg->regs + HCINTMSK(chnum));
2789 + u32 mask = dwc2_readl(hsotg->regs + HCINTMSK(chnum));
2790
2791 mask &= ~intr;
2792 - writel(mask, hsotg->regs + HCINTMSK(chnum));
2793 + dwc2_writel(mask, hsotg->regs + HCINTMSK(chnum));
2794 }
2795
2796 /*
2797 @@ -382,11 +382,11 @@ static inline void disable_hc_int(struct
2798 */
2799 static inline int dwc2_is_host_mode(struct dwc2_hsotg *hsotg)
2800 {
2801 - return (readl(hsotg->regs + GINTSTS) & GINTSTS_CURMODE_HOST) != 0;
2802 + return (dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_CURMODE_HOST) != 0;
2803 }
2804 static inline int dwc2_is_device_mode(struct dwc2_hsotg *hsotg)
2805 {
2806 - return (readl(hsotg->regs + GINTSTS) & GINTSTS_CURMODE_HOST) == 0;
2807 + return (dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_CURMODE_HOST) == 0;
2808 }
2809
2810 /*
2811 @@ -395,7 +395,7 @@ static inline int dwc2_is_device_mode(st
2812 */
2813 static inline u32 dwc2_read_hprt0(struct dwc2_hsotg *hsotg)
2814 {
2815 - u32 hprt0 = readl(hsotg->regs + HPRT0);
2816 + u32 hprt0 = dwc2_readl(hsotg->regs + HPRT0);
2817
2818 hprt0 &= ~(HPRT0_ENA | HPRT0_CONNDET | HPRT0_ENACHG | HPRT0_OVRCURRCHG);
2819 return hprt0;
2820 @@ -582,7 +582,7 @@ static inline u16 dwc2_micro_frame_num(u
2821 */
2822 static inline u32 dwc2_read_core_intr(struct dwc2_hsotg *hsotg)
2823 {
2824 - return readl(hsotg->regs + GINTSTS) & readl(hsotg->regs + GINTMSK);
2825 + return dwc2_readl(hsotg->regs + GINTSTS) & dwc2_readl(hsotg->regs + GINTMSK);
2826 }
2827
2828 static inline u32 dwc2_hcd_urb_get_status(struct dwc2_hcd_urb *dwc2_urb)
2829 @@ -734,7 +734,7 @@ do { \
2830 qtd_list_entry); \
2831 if (usb_pipeint(_qtd_->urb->pipe) && \
2832 (_qh_)->start_split_frame != 0 && !_qtd_->complete_split) { \
2833 - _hfnum_.d32 = readl((_hcd_)->regs + HFNUM); \
2834 + _hfnum_.d32 = dwc2_readl((_hcd_)->regs + HFNUM); \
2835 switch (_hfnum_.b.frnum & 0x7) { \
2836 case 7: \
2837 (_hcd_)->hfnum_7_samples_##_letter_++; \
2838 --- a/drivers/usb/dwc2/hcd_intr.c
2839 +++ b/drivers/usb/dwc2/hcd_intr.c
2840 @@ -148,7 +148,7 @@ static void dwc2_sof_intr(struct dwc2_hs
2841 dwc2_hcd_queue_transactions(hsotg, tr_type);
2842
2843 /* Clear interrupt */
2844 - writel(GINTSTS_SOF, hsotg->regs + GINTSTS);
2845 + dwc2_writel(GINTSTS_SOF, hsotg->regs + GINTSTS);
2846 }
2847
2848 /*
2849 @@ -164,7 +164,7 @@ static void dwc2_rx_fifo_level_intr(stru
2850 if (dbg_perio())
2851 dev_vdbg(hsotg->dev, "--RxFIFO Level Interrupt--\n");
2852
2853 - grxsts = readl(hsotg->regs + GRXSTSP);
2854 + grxsts = dwc2_readl(hsotg->regs + GRXSTSP);
2855 chnum = (grxsts & GRXSTS_HCHNUM_MASK) >> GRXSTS_HCHNUM_SHIFT;
2856 chan = hsotg->hc_ptr_array[chnum];
2857 if (!chan) {
2858 @@ -247,11 +247,11 @@ static void dwc2_hprt0_enable(struct dwc
2859 dev_vdbg(hsotg->dev, "%s(%p)\n", __func__, hsotg);
2860
2861 /* Every time when port enables calculate HFIR.FrInterval */
2862 - hfir = readl(hsotg->regs + HFIR);
2863 + hfir = dwc2_readl(hsotg->regs + HFIR);
2864 hfir &= ~HFIR_FRINT_MASK;
2865 hfir |= dwc2_calc_frame_interval(hsotg) << HFIR_FRINT_SHIFT &
2866 HFIR_FRINT_MASK;
2867 - writel(hfir, hsotg->regs + HFIR);
2868 + dwc2_writel(hfir, hsotg->regs + HFIR);
2869
2870 /* Check if we need to adjust the PHY clock speed for low power */
2871 if (!params->host_support_fs_ls_low_power) {
2872 @@ -260,7 +260,7 @@ static void dwc2_hprt0_enable(struct dwc
2873 return;
2874 }
2875
2876 - usbcfg = readl(hsotg->regs + GUSBCFG);
2877 + usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
2878 prtspd = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
2879
2880 if (prtspd == HPRT0_SPD_LOW_SPEED || prtspd == HPRT0_SPD_FULL_SPEED) {
2881 @@ -268,11 +268,11 @@ static void dwc2_hprt0_enable(struct dwc
2882 if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL)) {
2883 /* Set PHY low power clock select for FS/LS devices */
2884 usbcfg |= GUSBCFG_PHY_LP_CLK_SEL;
2885 - writel(usbcfg, hsotg->regs + GUSBCFG);
2886 + dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
2887 do_reset = 1;
2888 }
2889
2890 - hcfg = readl(hsotg->regs + HCFG);
2891 + hcfg = dwc2_readl(hsotg->regs + HCFG);
2892 fslspclksel = (hcfg & HCFG_FSLSPCLKSEL_MASK) >>
2893 HCFG_FSLSPCLKSEL_SHIFT;
2894
2895 @@ -286,7 +286,7 @@ static void dwc2_hprt0_enable(struct dwc
2896 fslspclksel = HCFG_FSLSPCLKSEL_6_MHZ;
2897 hcfg &= ~HCFG_FSLSPCLKSEL_MASK;
2898 hcfg |= fslspclksel << HCFG_FSLSPCLKSEL_SHIFT;
2899 - writel(hcfg, hsotg->regs + HCFG);
2900 + dwc2_writel(hcfg, hsotg->regs + HCFG);
2901 do_reset = 1;
2902 }
2903 } else {
2904 @@ -297,7 +297,7 @@ static void dwc2_hprt0_enable(struct dwc
2905 fslspclksel = HCFG_FSLSPCLKSEL_48_MHZ;
2906 hcfg &= ~HCFG_FSLSPCLKSEL_MASK;
2907 hcfg |= fslspclksel << HCFG_FSLSPCLKSEL_SHIFT;
2908 - writel(hcfg, hsotg->regs + HCFG);
2909 + dwc2_writel(hcfg, hsotg->regs + HCFG);
2910 do_reset = 1;
2911 }
2912 }
2913 @@ -305,7 +305,7 @@ static void dwc2_hprt0_enable(struct dwc
2914 /* Not low power */
2915 if (usbcfg & GUSBCFG_PHY_LP_CLK_SEL) {
2916 usbcfg &= ~GUSBCFG_PHY_LP_CLK_SEL;
2917 - writel(usbcfg, hsotg->regs + GUSBCFG);
2918 + dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
2919 do_reset = 1;
2920 }
2921 }
2922 @@ -332,7 +332,7 @@ static void dwc2_port_intr(struct dwc2_h
2923
2924 dev_vdbg(hsotg->dev, "--Port Interrupt--\n");
2925
2926 - hprt0 = readl(hsotg->regs + HPRT0);
2927 + hprt0 = dwc2_readl(hsotg->regs + HPRT0);
2928 hprt0_modify = hprt0;
2929
2930 /*
2931 @@ -385,7 +385,7 @@ static void dwc2_port_intr(struct dwc2_h
2932 }
2933
2934 /* Clear Port Interrupts */
2935 - writel(hprt0_modify, hsotg->regs + HPRT0);
2936 + dwc2_writel(hprt0_modify, hsotg->regs + HPRT0);
2937 }
2938
2939 /*
2940 @@ -405,7 +405,7 @@ static u32 dwc2_get_actual_xfer_length(s
2941 {
2942 u32 hctsiz, count, length;
2943
2944 - hctsiz = readl(hsotg->regs + HCTSIZ(chnum));
2945 + hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum));
2946
2947 if (halt_status == DWC2_HC_XFER_COMPLETE) {
2948 if (chan->ep_is_in) {
2949 @@ -483,7 +483,7 @@ static int dwc2_update_urb_state(struct
2950 urb->status = 0;
2951 }
2952
2953 - hctsiz = readl(hsotg->regs + HCTSIZ(chnum));
2954 + hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum));
2955 dev_vdbg(hsotg->dev, "DWC_otg: %s: %s, channel %d\n",
2956 __func__, (chan->ep_is_in ? "IN" : "OUT"), chnum);
2957 dev_vdbg(hsotg->dev, " chan->xfer_len %d\n", chan->xfer_len);
2958 @@ -506,7 +506,7 @@ void dwc2_hcd_save_data_toggle(struct dw
2959 struct dwc2_host_chan *chan, int chnum,
2960 struct dwc2_qtd *qtd)
2961 {
2962 - u32 hctsiz = readl(hsotg->regs + HCTSIZ(chnum));
2963 + u32 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum));
2964 u32 pid = (hctsiz & TSIZ_SC_MC_PID_MASK) >> TSIZ_SC_MC_PID_SHIFT;
2965
2966 if (chan->ep_type != USB_ENDPOINT_XFER_CONTROL) {
2967 @@ -753,9 +753,9 @@ cleanup:
2968 }
2969 }
2970
2971 - haintmsk = readl(hsotg->regs + HAINTMSK);
2972 + haintmsk = dwc2_readl(hsotg->regs + HAINTMSK);
2973 haintmsk &= ~(1 << chan->hc_num);
2974 - writel(haintmsk, hsotg->regs + HAINTMSK);
2975 + dwc2_writel(haintmsk, hsotg->regs + HAINTMSK);
2976
2977 /* Try to queue more transfers now that there's a free channel */
2978 tr_type = dwc2_hcd_select_transactions(hsotg);
2979 @@ -802,9 +802,9 @@ static void dwc2_halt_channel(struct dwc
2980 * is enabled so that the non-periodic schedule will
2981 * be processed
2982 */
2983 - gintmsk = readl(hsotg->regs + GINTMSK);
2984 + gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
2985 gintmsk |= GINTSTS_NPTXFEMP;
2986 - writel(gintmsk, hsotg->regs + GINTMSK);
2987 + dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
2988 } else {
2989 dev_vdbg(hsotg->dev, "isoc/intr\n");
2990 /*
2991 @@ -821,9 +821,9 @@ static void dwc2_halt_channel(struct dwc
2992 * enabled so that the periodic schedule will be
2993 * processed
2994 */
2995 - gintmsk = readl(hsotg->regs + GINTMSK);
2996 + gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
2997 gintmsk |= GINTSTS_PTXFEMP;
2998 - writel(gintmsk, hsotg->regs + GINTMSK);
2999 + dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
3000 }
3001 }
3002 }
3003 @@ -888,7 +888,7 @@ static void dwc2_complete_periodic_xfer(
3004 struct dwc2_qtd *qtd,
3005 enum dwc2_halt_status halt_status)
3006 {
3007 - u32 hctsiz = readl(hsotg->regs + HCTSIZ(chnum));
3008 + u32 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum));
3009
3010 qtd->error_count = 0;
3011
3012 @@ -1158,7 +1158,7 @@ static void dwc2_update_urb_state_abn(st
3013
3014 urb->actual_length += xfer_length;
3015
3016 - hctsiz = readl(hsotg->regs + HCTSIZ(chnum));
3017 + hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum));
3018 dev_vdbg(hsotg->dev, "DWC_otg: %s: %s, channel %d\n",
3019 __func__, (chan->ep_is_in ? "IN" : "OUT"), chnum);
3020 dev_vdbg(hsotg->dev, " chan->start_pkt_count %d\n",
3021 @@ -1469,10 +1469,10 @@ static void dwc2_hc_ahberr_intr(struct d
3022
3023 dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
3024
3025 - hcchar = readl(hsotg->regs + HCCHAR(chnum));
3026 - hcsplt = readl(hsotg->regs + HCSPLT(chnum));
3027 - hctsiz = readl(hsotg->regs + HCTSIZ(chnum));
3028 - hc_dma = readl(hsotg->regs + HCDMA(chnum));
3029 + hcchar = dwc2_readl(hsotg->regs + HCCHAR(chnum));
3030 + hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chnum));
3031 + hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum));
3032 + hc_dma = dwc2_readl(hsotg->regs + HCDMA(chnum));
3033
3034 dev_err(hsotg->dev, "AHB ERROR, Channel %d\n", chnum);
3035 dev_err(hsotg->dev, " hcchar 0x%08x, hcsplt 0x%08x\n", hcchar, hcsplt);
3036 @@ -1685,10 +1685,10 @@ static bool dwc2_halt_status_ok(struct d
3037 * This code is here only as a check. This condition should
3038 * never happen. Ignore the halt if it does occur.
3039 */
3040 - hcchar = readl(hsotg->regs + HCCHAR(chnum));
3041 - hctsiz = readl(hsotg->regs + HCTSIZ(chnum));
3042 - hcintmsk = readl(hsotg->regs + HCINTMSK(chnum));
3043 - hcsplt = readl(hsotg->regs + HCSPLT(chnum));
3044 + hcchar = dwc2_readl(hsotg->regs + HCCHAR(chnum));
3045 + hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum));
3046 + hcintmsk = dwc2_readl(hsotg->regs + HCINTMSK(chnum));
3047 + hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chnum));
3048 dev_dbg(hsotg->dev,
3049 "%s: chan->halt_status DWC2_HC_XFER_NO_HALT_STATUS,\n",
3050 __func__);
3051 @@ -1712,7 +1712,7 @@ static bool dwc2_halt_status_ok(struct d
3052 * when the halt interrupt occurs. Halt the channel again if it does
3053 * occur.
3054 */
3055 - hcchar = readl(hsotg->regs + HCCHAR(chnum));
3056 + hcchar = dwc2_readl(hsotg->regs + HCCHAR(chnum));
3057 if (hcchar & HCCHAR_CHDIS) {
3058 dev_warn(hsotg->dev,
3059 "%s: hcchar.chdis set unexpectedly, hcchar 0x%08x, trying to halt again\n",
3060 @@ -1772,7 +1772,7 @@ static void dwc2_hc_chhltd_intr_dma(stru
3061 return;
3062 }
3063
3064 - hcintmsk = readl(hsotg->regs + HCINTMSK(chnum));
3065 + hcintmsk = dwc2_readl(hsotg->regs + HCINTMSK(chnum));
3066
3067 if (chan->hcint & HCINTMSK_XFERCOMPL) {
3068 /*
3069 @@ -1867,7 +1867,7 @@ static void dwc2_hc_chhltd_intr_dma(stru
3070 dev_err(hsotg->dev,
3071 "hcint 0x%08x, intsts 0x%08x\n",
3072 chan->hcint,
3073 - readl(hsotg->regs + GINTSTS));
3074 + dwc2_readl(hsotg->regs + GINTSTS));
3075 goto error;
3076 }
3077 }
3078 @@ -1922,11 +1922,11 @@ static void dwc2_hc_n_intr(struct dwc2_h
3079
3080 chan = hsotg->hc_ptr_array[chnum];
3081
3082 - hcint = readl(hsotg->regs + HCINT(chnum));
3083 - hcintmsk = readl(hsotg->regs + HCINTMSK(chnum));
3084 + hcint = dwc2_readl(hsotg->regs + HCINT(chnum));
3085 + hcintmsk = dwc2_readl(hsotg->regs + HCINTMSK(chnum));
3086 if (!chan) {
3087 dev_err(hsotg->dev, "## hc_ptr_array for channel is NULL ##\n");
3088 - writel(hcint, hsotg->regs + HCINT(chnum));
3089 + dwc2_writel(hcint, hsotg->regs + HCINT(chnum));
3090 return;
3091 }
3092
3093 @@ -1938,7 +1938,7 @@ static void dwc2_hc_n_intr(struct dwc2_h
3094 hcint, hcintmsk, hcint & hcintmsk);
3095 }
3096
3097 - writel(hcint, hsotg->regs + HCINT(chnum));
3098 + dwc2_writel(hcint, hsotg->regs + HCINT(chnum));
3099 chan->hcint = hcint;
3100 hcint &= hcintmsk;
3101
3102 @@ -2030,7 +2030,7 @@ static void dwc2_hc_intr(struct dwc2_hso
3103 u32 haint;
3104 int i;
3105
3106 - haint = readl(hsotg->regs + HAINT);
3107 + haint = dwc2_readl(hsotg->regs + HAINT);
3108 if (dbg_perio()) {
3109 dev_vdbg(hsotg->dev, "%s()\n", __func__);
3110
3111 @@ -2098,8 +2098,8 @@ irqreturn_t dwc2_handle_hcd_intr(struct
3112 "DWC OTG HCD Finished Servicing Interrupts\n");
3113 dev_vdbg(hsotg->dev,
3114 "DWC OTG HCD gintsts=0x%08x gintmsk=0x%08x\n",
3115 - readl(hsotg->regs + GINTSTS),
3116 - readl(hsotg->regs + GINTMSK));
3117 + dwc2_readl(hsotg->regs + GINTSTS),
3118 + dwc2_readl(hsotg->regs + GINTMSK));
3119 }
3120 }
3121
3122 --- a/drivers/usb/dwc2/hcd_queue.c
3123 +++ b/drivers/usb/dwc2/hcd_queue.c
3124 @@ -115,7 +115,7 @@ static void dwc2_qh_init(struct dwc2_hso
3125 if (qh->ep_type == USB_ENDPOINT_XFER_INT)
3126 qh->interval = 8;
3127 #endif
3128 - hprt = readl(hsotg->regs + HPRT0);
3129 + hprt = dwc2_readl(hsotg->regs + HPRT0);
3130 prtspd = (hprt & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
3131 if (prtspd == HPRT0_SPD_HIGH_SPEED &&
3132 (dev_speed == USB_SPEED_LOW ||
3133 @@ -593,9 +593,9 @@ int dwc2_hcd_qh_add(struct dwc2_hsotg *h
3134 if (status)
3135 return status;
3136 if (!hsotg->periodic_qh_count) {
3137 - intr_mask = readl(hsotg->regs + GINTMSK);
3138 + intr_mask = dwc2_readl(hsotg->regs + GINTMSK);
3139 intr_mask |= GINTSTS_SOF;
3140 - writel(intr_mask, hsotg->regs + GINTMSK);
3141 + dwc2_writel(intr_mask, hsotg->regs + GINTMSK);
3142 }
3143 hsotg->periodic_qh_count++;
3144
3145 @@ -630,9 +630,9 @@ void dwc2_hcd_qh_unlink(struct dwc2_hsot
3146 dwc2_deschedule_periodic(hsotg, qh);
3147 hsotg->periodic_qh_count--;
3148 if (!hsotg->periodic_qh_count) {
3149 - intr_mask = readl(hsotg->regs + GINTMSK);
3150 + intr_mask = dwc2_readl(hsotg->regs + GINTMSK);
3151 intr_mask &= ~GINTSTS_SOF;
3152 - writel(intr_mask, hsotg->regs + GINTMSK);
3153 + dwc2_writel(intr_mask, hsotg->regs + GINTMSK);
3154 }
3155 }
3156
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