target/linux/lantiq/patches-5.10/0113-MIPS-lantiq-dma-make-a-burst-length-configurable-in-.patch

   1 From 6615eeb39f7a110a196f20acbfb3a017da4d75d2 Mon Sep 17 00:00:00 2001
   2 From: Aleksander Jan Bajkowski <olek2@wp.pl>
   3 Date: Fri, 14 May 2021 21:25:08 +0200
   4 Subject: [PATCH 4/5] MIPS: lantiq: dma: make a burst length configurable in
   5  drivers
   6
   7 Make a burst length configurable in drivers.
   8
   9 Signed-off-by: Aleksander Jan Bajkowski <olek2@wp.pl>
  10 ---
  11  .../include/asm/mach-lantiq/xway/xway_dma.h   |  2 +-
  12  arch/mips/lantiq/xway/dma.c                   | 38 ++++++++++++++++---
  13  2 files changed, 34 insertions(+), 6 deletions(-)
  14
  15 --- a/arch/mips/include/asm/mach-lantiq/xway/xway_dma.h
  16 +++ b/arch/mips/include/asm/mach-lantiq/xway/xway_dma.h
  17 @@ -45,6 +45,6 @@ extern void ltq_dma_close(struct ltq_dma
  18  extern void ltq_dma_alloc_tx(struct ltq_dma_channel *ch);
  19  extern void ltq_dma_alloc_rx(struct ltq_dma_channel *ch);
  20  extern void ltq_dma_free(struct ltq_dma_channel *ch);
  21 -extern void ltq_dma_init_port(int p);
  22 +extern void ltq_dma_init_port(int p, int tx_burst, int rx_burst);
  23
  24  #endif
  25 --- a/arch/mips/lantiq/xway/dma.c
  26 +++ b/arch/mips/lantiq/xway/dma.c
  27 @@ -181,7 +181,7 @@ ltq_dma_free(struct ltq_dma_channel *ch)
  28  EXPORT_SYMBOL_GPL(ltq_dma_free);
  29
  30  void
  31 -ltq_dma_init_port(int p)
  32 +ltq_dma_init_port(int p, int tx_burst, int rx_burst)
  33  {
  34         ltq_dma_w32(p, LTQ_DMA_PS);
  35         switch (p) {
  36 @@ -190,16 +190,44 @@ ltq_dma_init_port(int p)
  37                  * Tell the DMA engine to swap the endianness of data frames and
  38                  * drop packets if the channel arbitration fails.
  39                  */
  40 -               ltq_dma_w32_mask(0, DMA_ETOP_ENDIANNESS | DMA_PDEN,
  41 +               ltq_dma_w32_mask(0, (DMA_ETOP_ENDIANNESS | DMA_PDEN),
  42                         LTQ_DMA_PCTRL);
  43                 break;
  44
  45 -       case DMA_PORT_DEU:
  46 -               ltq_dma_w32((DMA_PCTRL_2W_BURST << DMA_TX_BURST_SHIFT) |
  47 -                       (DMA_PCTRL_2W_BURST << DMA_RX_BURST_SHIFT),
  48 +       default:
  49 +               break;
  50 +       }
  51 +
  52 +       switch (rx_burst) {
  53 +       case 8:
  54 +               ltq_dma_w32_mask(0x0c, (DMA_PCTRL_8W_BURST << DMA_RX_BURST_SHIFT),
  55                         LTQ_DMA_PCTRL);
  56                 break;
  57 +       case 4:
  58 +               ltq_dma_w32_mask(0x0c, (DMA_PCTRL_4W_BURST << DMA_RX_BURST_SHIFT),
  59 +                       LTQ_DMA_PCTRL);
  60 +               break;
  61 +       case 2:
  62 +               ltq_dma_w32_mask(0x0c, (DMA_PCTRL_2W_BURST << DMA_RX_BURST_SHIFT),
  63 +                       LTQ_DMA_PCTRL);
  64 +               break;
  65 +       default:
  66 +               break;
  67 +       }
  68
  69 +       switch (tx_burst) {
  70 +       case 8:
  71 +               ltq_dma_w32_mask(0x30, (DMA_PCTRL_8W_BURST << DMA_TX_BURST_SHIFT),
  72 +                       LTQ_DMA_PCTRL);
  73 +               break;
  74 +       case 4:
  75 +               ltq_dma_w32_mask(0x30, (DMA_PCTRL_4W_BURST << DMA_TX_BURST_SHIFT),
  76 +                       LTQ_DMA_PCTRL);
  77 +               break;
  78 +       case 2:
  79 +               ltq_dma_w32_mask(0x30, (DMA_PCTRL_2W_BURST << DMA_TX_BURST_SHIFT),
  80 +                       LTQ_DMA_PCTRL);
  81 +               break;
  82         default:
  83                 break;
  84         }