target/linux/layerscape/patches-5.4/701-net-0251-net-mscc-ocelot-split-assignment-of-the-cpu-port-int.patch

   1 From c6f39379529e74eccbe317e70bb11d18110c63d4 Mon Sep 17 00:00:00 2001
   2 From: Vladimir Oltean <vladimir.oltean@nxp.com>
   3 Date: Sat, 9 Nov 2019 15:03:00 +0200
   4 Subject: [PATCH] net: mscc: ocelot: split assignment of the cpu port into a
   5  separate function
   6
   7 Now that the places that configure routing destinations for the CPU port
   8 have been marked as such, allow callers to specify their own CPU port
   9 that is different than ocelot->num_phys_ports. A user will be the Felix
  10 DSA driver, where the CPU port is one of the physical ports (NPI mode).
  11
  12 Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
  13 Signed-off-by: David S. Miller <davem@davemloft.net>
  14 ---
  15  drivers/net/ethernet/mscc/ocelot.c       | 65 +++++++++++++++++++++-----------
  16  drivers/net/ethernet/mscc/ocelot.h       | 12 ++++++
  17  drivers/net/ethernet/mscc/ocelot_board.c |  2 +
  18  3 files changed, 57 insertions(+), 22 deletions(-)
  19
  20 --- a/drivers/net/ethernet/mscc/ocelot.c
  21 +++ b/drivers/net/ethernet/mscc/ocelot.c
  22 @@ -380,12 +380,6 @@ static void ocelot_vlan_init(struct ocel
  23         ocelot->vlan_mask[0] = GENMASK(ocelot->num_phys_ports - 1, 0);
  24         ocelot_vlant_set_mask(ocelot, 0, ocelot->vlan_mask[0]);
  25
  26 -       /* Configure the CPU port to be VLAN aware */
  27 -       ocelot_write_gix(ocelot, ANA_PORT_VLAN_CFG_VLAN_VID(0) |
  28 -                                ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA |
  29 -                                ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1),
  30 -                        ANA_PORT_VLAN_CFG, ocelot->num_phys_ports);
  31 -
  32         /* Set vlan ingress filter mask to all ports but the CPU port by
  33          * default.
  34          */
  35 @@ -2226,11 +2220,52 @@ int ocelot_probe_port(struct ocelot *oce
  36  }
  37  EXPORT_SYMBOL(ocelot_probe_port);
  38
  39 +void ocelot_set_cpu_port(struct ocelot *ocelot, int cpu,
  40 +                        enum ocelot_tag_prefix injection,
  41 +                        enum ocelot_tag_prefix extraction)
  42 +{
  43 +       /* Configure and enable the CPU port. */
  44 +       ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, cpu);
  45 +       ocelot_write_rix(ocelot, BIT(cpu), ANA_PGID_PGID, PGID_CPU);
  46 +       ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_RECV_ENA |
  47 +                        ANA_PORT_PORT_CFG_PORTID_VAL(cpu),
  48 +                        ANA_PORT_PORT_CFG, cpu);
  49 +
  50 +       /* If the CPU port is a physical port, set up the port in Node
  51 +        * Processor Interface (NPI) mode. This is the mode through which
  52 +        * frames can be injected from and extracted to an external CPU.
  53 +        * Only one port can be an NPI at the same time.
  54 +        */
  55 +       if (cpu < ocelot->num_phys_ports) {
  56 +               ocelot_write(ocelot, QSYS_EXT_CPU_CFG_EXT_CPUQ_MSK_M |
  57 +                            QSYS_EXT_CPU_CFG_EXT_CPU_PORT(cpu),
  58 +                            QSYS_EXT_CPU_CFG);
  59 +       }
  60 +
  61 +       /* CPU port Injection/Extraction configuration */
  62 +       ocelot_write_rix(ocelot, QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE |
  63 +                        QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG(1) |
  64 +                        QSYS_SWITCH_PORT_MODE_PORT_ENA,
  65 +                        QSYS_SWITCH_PORT_MODE, cpu);
  66 +       ocelot_write_rix(ocelot, SYS_PORT_MODE_INCL_XTR_HDR(extraction) |
  67 +                        SYS_PORT_MODE_INCL_INJ_HDR(injection),
  68 +                        SYS_PORT_MODE, cpu);
  69 +
  70 +       /* Configure the CPU port to be VLAN aware */
  71 +       ocelot_write_gix(ocelot, ANA_PORT_VLAN_CFG_VLAN_VID(0) |
  72 +                                ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA |
  73 +                                ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1),
  74 +                        ANA_PORT_VLAN_CFG, cpu);
  75 +
  76 +       ocelot->cpu = cpu;
  77 +}
  78 +EXPORT_SYMBOL(ocelot_set_cpu_port);
  79 +
  80  int ocelot_init(struct ocelot *ocelot)
  81  {
  82 -       u32 port;
  83 -       int i, ret, cpu = ocelot->num_phys_ports;
  84         char queue_name[32];
  85 +       int i, ret;
  86 +       u32 port;
  87
  88         ocelot->lags = devm_kcalloc(ocelot->dev, ocelot->num_phys_ports,
  89                                     sizeof(u32), GFP_KERNEL);
  90 @@ -2310,13 +2345,6 @@ int ocelot_init(struct ocelot *ocelot)
  91                 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_SRC + port);
  92         }
  93
  94 -       /* Configure and enable the CPU port. */
  95 -       ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, cpu);
  96 -       ocelot_write_rix(ocelot, BIT(cpu), ANA_PGID_PGID, PGID_CPU);
  97 -       ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_RECV_ENA |
  98 -                        ANA_PORT_PORT_CFG_PORTID_VAL(cpu),
  99 -                        ANA_PORT_PORT_CFG, cpu);
 100 -
 101         /* Allow broadcast MAC frames. */
 102         for (i = ocelot->num_phys_ports + 1; i < PGID_CPU; i++) {
 103                 u32 val = ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports - 1, 0));
 104 @@ -2329,13 +2357,6 @@ int ocelot_init(struct ocelot *ocelot)
 105         ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV4);
 106         ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV6);
 107
 108 -       /* CPU port Injection/Extraction configuration */
 109 -       ocelot_write_rix(ocelot, QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE |
 110 -                        QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG(1) |
 111 -                        QSYS_SWITCH_PORT_MODE_PORT_ENA,
 112 -                        QSYS_SWITCH_PORT_MODE, cpu);
 113 -       ocelot_write_rix(ocelot, SYS_PORT_MODE_INCL_XTR_HDR(1) |
 114 -                        SYS_PORT_MODE_INCL_INJ_HDR(1), SYS_PORT_MODE, cpu);
 115         /* Allow manual injection via DEVCPU_QS registers, and byte swap these
 116          * registers endianness.
 117          */
 118 --- a/drivers/net/ethernet/mscc/ocelot.h
 119 +++ b/drivers/net/ethernet/mscc/ocelot.h
 120 @@ -427,6 +427,13 @@ struct ocelot_multicast {
 121         u16 ports;
 122  };
 123
 124 +enum ocelot_tag_prefix {
 125 +       OCELOT_TAG_PREFIX_DISABLED      = 0,
 126 +       OCELOT_TAG_PREFIX_NONE,
 127 +       OCELOT_TAG_PREFIX_SHORT,
 128 +       OCELOT_TAG_PREFIX_LONG,
 129 +};
 130 +
 131  struct ocelot_port;
 132
 133  struct ocelot_stat_layout {
 134 @@ -455,6 +462,7 @@ struct ocelot {
 135
 136         u8 num_phys_ports;
 137         u8 num_cpu_ports;
 138 +       u8 cpu;
 139         struct ocelot_port **ports;
 140
 141         u32 *lags;
 142 @@ -552,6 +560,10 @@ int ocelot_probe_port(struct ocelot *oce
 143                       void __iomem *regs,
 144                       struct phy_device *phy);
 145
 146 +void ocelot_set_cpu_port(struct ocelot *ocelot, int cpu,
 147 +                        enum ocelot_tag_prefix injection,
 148 +                        enum ocelot_tag_prefix extraction);
 149 +
 150  extern struct notifier_block ocelot_netdevice_nb;
 151  extern struct notifier_block ocelot_switchdev_nb;
 152  extern struct notifier_block ocelot_switchdev_blocking_nb;
 153 --- a/drivers/net/ethernet/mscc/ocelot_board.c
 154 +++ b/drivers/net/ethernet/mscc/ocelot_board.c
 155 @@ -373,6 +373,8 @@ static int mscc_ocelot_probe(struct plat
 156                                      sizeof(struct ocelot_port *), GFP_KERNEL);
 157
 158         ocelot_init(ocelot);
 159 +       ocelot_set_cpu_port(ocelot, ocelot->num_phys_ports,
 160 +                           OCELOT_TAG_PREFIX_NONE, OCELOT_TAG_PREFIX_NONE);
 161
 162         for_each_available_child_of_node(ports, portnp) {
 163                 struct ocelot_port_private *priv;