target/linux/layerscape/patches-5.4/804-crypto-0018-MLKU-114-3-crypto-caam-OP-TEE-firmware-support.patch

   1 From 8a0bf079f870379a1e392819ac1116d74500ec01 Mon Sep 17 00:00:00 2001
   2 From: =?UTF-8?q?Horia=20Geant=C4=83?= <horia.geanta@nxp.com>
   3 Date: Fri, 4 Oct 2019 15:07:41 +0300
   4 Subject: [PATCH] MLKU-114-3 crypto: caam - OP-TEE firmware support
   5 MIME-Version: 1.0
   6 Content-Type: text/plain; charset=UTF-8
   7 Content-Transfer-Encoding: 8bit
   8
   9 caam driver needs to be aware of OP-TEE f/w presence, since some things
  10 are done differently:
  11
  12 1. there is no access to controller's register page (note however that
  13 some registers are aliased in job rings' register pages)
  14
  15 It's worth mentioning that due to this, MCFGR[PS] cannot be read
  16 and driver assumes MCFGR[PS] = b'0 - engine using 32-bit address pointers.
  17
  18 This is in sync with the fact that:
  19 -all i.MX SoCs currently use MCFGR[PS] = b'0
  20 -only i.MX OP-TEE use cases don't allow access to controller register page
  21
  22 Note: When DN OP-TEE will start enforcing the same policy,
  23 this solution will stop working and information about caam configuration
  24 will have to deduced in some other way.
  25
  26 2. as a consequence of "1.", part of the initialization is moved in
  27 other f/w (TF-A etc.), e.g. RNG initialization
  28
  29 Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
  30 ---
  31  drivers/crypto/caam/ctrl.c   | 22 ++++++++++++++++++----
  32  drivers/crypto/caam/intern.h |  1 +
  33  2 files changed, 19 insertions(+), 4 deletions(-)
  34
  35 --- a/drivers/crypto/caam/ctrl.c
  36 +++ b/drivers/crypto/caam/ctrl.c
  37 @@ -583,6 +583,7 @@ static int caam_probe(struct platform_de
  38         u8 rng_vid;
  39         int pg_size;
  40         int BLOCK_OFFSET = 0;
  41 +       bool reg_access = true;
  42
  43         ctrlpriv = devm_kzalloc(&pdev->dev, sizeof(*ctrlpriv), GFP_KERNEL);
  44         if (!ctrlpriv)
  45 @@ -600,6 +601,8 @@ static int caam_probe(struct platform_de
  46                 ctrlpriv->scu_en = !!np;
  47                 of_node_put(np);
  48
  49 +               reg_access = !ctrlpriv->scu_en;
  50 +
  51                 /*
  52                  * CAAM clocks cannot be controlled from kernel.
  53                  * They are automatically turned on by SCU f/w.
  54 @@ -607,6 +610,17 @@ static int caam_probe(struct platform_de
  55                 if (ctrlpriv->scu_en)
  56                         goto iomap_ctrl;
  57
  58 +               /*
  59 +                * Until Layerscape and i.MX OP-TEE get in sync,
  60 +                * only i.MX OP-TEE use cases disallow access to
  61 +                * caam page 0 (controller) registers.
  62 +                */
  63 +               np = of_find_compatible_node(NULL, NULL, "linaro,optee-tz");
  64 +               ctrlpriv->optee_en = !!np;
  65 +               of_node_put(np);
  66 +
  67 +               reg_access = reg_access && !ctrlpriv->optee_en;
  68 +
  69                 if (!imx_soc_match->data) {
  70                         dev_err(dev, "No clock data provided for i.MX SoC");
  71                         return -EINVAL;
  72 @@ -657,7 +671,7 @@ iomap_ctrl:
  73         caam_little_end = !(bool)(rd_reg32(&perfmon->status) &
  74                                   (CSTA_PLEND | CSTA_ALT_PLEND));
  75         comp_params = rd_reg32(&perfmon->comp_parms_ms);
  76 -       if (!ctrlpriv->scu_en && comp_params & CTPR_MS_PS &&
  77 +       if (reg_access && comp_params & CTPR_MS_PS &&
  78             rd_reg32(&ctrl->mcr) & MCFGR_LONG_PTR)
  79                 caam_ptr_sz = sizeof(u64);
  80         else
  81 @@ -708,7 +722,7 @@ iomap_ctrl:
  82         /* Get the IRQ of the controller (for security violations only) */
  83         ctrlpriv->secvio_irq = irq_of_parse_and_map(nprop, 0);
  84
  85 -       if (ctrlpriv->scu_en)
  86 +       if (!reg_access)
  87                 goto set_dma_mask;
  88
  89         /*
  90 @@ -801,7 +815,7 @@ set_dma_mask:
  91                 return -ENOMEM;
  92         }
  93
  94 -       if (ctrlpriv->scu_en)
  95 +       if (!reg_access)
  96                 goto report_live;
  97
  98         if (ctrlpriv->era < 10) {
  99 @@ -928,7 +942,7 @@ report_live:
 100                             ctrlpriv->ctl, &perfmon->status,
 101                             &caam_fops_u32_ro);
 102
 103 -       if (ctrlpriv->scu_en)
 104 +       if (!reg_access)
 105                 goto probe_jrs;
 106
 107         /* Internal covering keys (useful in non-secure mode only) */
 108 --- a/drivers/crypto/caam/intern.h
 109 +++ b/drivers/crypto/caam/intern.h
 110 @@ -83,6 +83,7 @@ struct caam_drv_private {
 111         u8 qi_present;          /* Nonzero if QI present in device */
 112         u8 mc_en;               /* Nonzero if MC f/w is active */
 113         u8 scu_en;              /* Nonzero if SCU f/w is active */
 114 ++      u8 optee_en;            /* Nonzero if OP-TEE f/w is active */
 115         int secvio_irq;         /* Security violation interrupt number */
 116         int virt_en;            /* Virtualization enabled in CAAM */
 117         int era;                /* CAAM Era (internal HW revision) */