target/linux/layerscape/patches-5.4/805-display-0011-drm-imx-add-imx8mq-hdmi-support.patch

   1 From 7095b3b3b28031708ab74a65c32e84e231bc9d27 Mon Sep 17 00:00:00 2001
   2 From: Sandor Yu <Sandor.yu@nxp.com>
   3 Date: Wed, 11 Sep 2019 17:18:29 +0800
   4 Subject: [PATCH] drm: imx: add imx8mq hdmi support
   5
   6 add struct imx_mhdp_device for imx specific.
   7 add imx8mq hdmi support.
   8 move imx8qm specific functions to plat_data
   9 uniform variable name.
  10
  11 Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
  12 ---
  13  drivers/gpu/drm/imx/Makefile            |   2 +-
  14  drivers/gpu/drm/imx/cdn-mhdp-dp-phy.c   |   8 +-
  15  drivers/gpu/drm/imx/cdn-mhdp-hdmi-phy.c |   7 +-
  16  drivers/gpu/drm/imx/cdn-mhdp-imx8mq.c   | 163 ------------
  17  drivers/gpu/drm/imx/cdn-mhdp-imx8qm.c   | 437 ++++++++++----------------------
  18  drivers/gpu/drm/imx/cdn-mhdp-imxdrv.c   | 202 +++++++++++++++
  19  drivers/gpu/drm/imx/cdn-mhdp-phy.h      |  12 +-
  20  drivers/gpu/drm/imx/cdns-mhdp-imx.h     |  80 ++++++
  21  8 files changed, 421 insertions(+), 490 deletions(-)
  22  delete mode 100644 drivers/gpu/drm/imx/cdn-mhdp-imx8mq.c
  23  create mode 100644 drivers/gpu/drm/imx/cdn-mhdp-imxdrv.c
  24  create mode 100644 drivers/gpu/drm/imx/cdns-mhdp-imx.h
  25
  26 --- a/drivers/gpu/drm/imx/Makefile
  27 +++ b/drivers/gpu/drm/imx/Makefile
  28 @@ -9,4 +9,4 @@ obj-$(CONFIG_DRM_IMX_TVE) += imx-tve.o
  29  obj-$(CONFIG_DRM_IMX_LDB) += imx-ldb.o
  30
  31  obj-$(CONFIG_DRM_IMX_HDMI) += dw_hdmi-imx.o
  32 -obj-$(CONFIG_DRM_IMX_CDNS_MHDP) += cdn-mhdp-imx8qm.o cdn-mhdp-imx8mq.o cdn-mhdp-dp-phy.o cdn-mhdp-hdmi-phy.o
  33 +obj-$(CONFIG_DRM_IMX_CDNS_MHDP) += cdn-mhdp-imxdrv.o cdn-mhdp-dp-phy.o cdn-mhdp-hdmi-phy.o cdn-mhdp-imx8qm.o
  34 --- a/drivers/gpu/drm/imx/cdn-mhdp-dp-phy.c
  35 +++ b/drivers/gpu/drm/imx/cdn-mhdp-dp-phy.c
  36 @@ -12,7 +12,6 @@
  37  #include <linux/clk.h>
  38  #include <linux/kernel.h>
  39  #include <drm/drm_dp_helper.h>
  40 -
  41  #include <drm/bridge/cdns-mhdp-common.h>
  42  #include "cdn-mhdp-phy.h"
  43
  44 @@ -477,9 +476,8 @@ static int dp_phy_power_up(struct cdns_m
  45         return 0;
  46  }
  47
  48 -int cdns_dp_phy_init_imx8mq(struct imx_mhdp_device *hdp)
  49 +int cdns_dp_phy_set_imx8mq(struct cdns_mhdp_device *mhdp)
  50  {
  51 -       struct cdns_mhdp_device *mhdp = &hdp->mhdp;
  52         int ret;
  53
  54         /* Disable phy clock if PHY in power up state */
  55 @@ -504,10 +502,8 @@ int cdns_dp_phy_init_imx8mq(struct imx_m
  56         return ret;
  57  }
  58
  59 -
  60 -int cdns_dp_phy_init_imx8qm(struct imx_mhdp_device *hdp)
  61 +int cdns_dp_phy_set_imx8qm(struct cdns_mhdp_device *mhdp)
  62  {
  63 -       struct cdns_mhdp_device *mhdp = &hdp->mhdp;
  64         int ret;
  65
  66         /* Disable phy clock if PHY in power up state */
  67 --- a/drivers/gpu/drm/imx/cdn-mhdp-hdmi-phy.c
  68 +++ b/drivers/gpu/drm/imx/cdn-mhdp-hdmi-phy.c
  69 @@ -624,9 +624,8 @@ static int hdmi_phy_power_up(struct cdns
  70         return 0;
  71  }
  72
  73 -int cdns_hdmi_phy_set_imx8mq(struct imx_mhdp_device *hdp)
  74 +int cdns_hdmi_phy_set_imx8mq(struct cdns_mhdp_device *mhdp)
  75  {
  76 -       struct cdns_mhdp_device *mhdp = &hdp->mhdp;
  77         struct drm_display_mode *mode = &mhdp->mode;
  78         int ret;
  79
  80 @@ -653,9 +652,8 @@ int cdns_hdmi_phy_set_imx8mq(struct imx_
  81         return true;
  82  }
  83
  84 -int cdns_hdmi_phy_set_imx8qm(struct imx_mhdp_device *hdp)
  85 +int cdns_hdmi_phy_set_imx8qm(struct cdns_mhdp_device *mhdp)
  86  {
  87 -       struct cdns_mhdp_device *mhdp = &hdp->mhdp;
  88         struct drm_display_mode *mode = &mhdp->mode;
  89         int ret;
  90
  91 @@ -681,4 +679,3 @@ int cdns_hdmi_phy_set_imx8qm(struct imx_
  92
  93         return true;
  94  }
  95 -
  96 --- a/drivers/gpu/drm/imx/cdn-mhdp-imx8mq.c
  97 +++ /dev/null
  98 @@ -1,163 +0,0 @@
  99 -/*
 100 - * Copyright (C) 2019 NXP Semiconductor, Inc.
 101 - *
 102 - * This program is free software; you can redistribute it and/or modify
 103 - * it under the terms of the GNU General Public License version 2 as
 104 - * published by the Free Software Foundation.
 105 - */
 106 -#include <linux/module.h>
 107 -#include <linux/platform_device.h>
 108 -#include <linux/component.h>
 109 -#include <linux/mfd/syscon.h>
 110 -#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
 111 -#include <drm/drm_of.h>
 112 -#include <drm/drmP.h>
 113 -#include <drm/drm_crtc_helper.h>
 114 -#include <drm/drm_edid.h>
 115 -#include <drm/drm_encoder_slave.h>
 116 -
 117 -#include <drm/bridge/cdns-mhdp-imx.h>
 118 -#include "cdn-mhdp-phy.h"
 119 -#include "imx-drm.h"
 120 -
 121 -struct imx_hdmi {
 122 -       struct device *dev;
 123 -       struct drm_encoder encoder;
 124 -};
 125 -
 126 -static void cdns_hdmi_imx_encoder_disable(struct drm_encoder *encoder)
 127 -{
 128 -}
 129 -
 130 -static void cdns_hdmi_imx_encoder_enable(struct drm_encoder *encoder)
 131 -{
 132 -}
 133 -
 134 -static int cdns_hdmi_imx_atomic_check(struct drm_encoder *encoder,
 135 -                                   struct drm_crtc_state *crtc_state,
 136 -                                   struct drm_connector_state *conn_state)
 137 -{
 138 -       return 0;
 139 -}
 140 -
 141 -static const struct drm_encoder_helper_funcs cdns_hdmi_imx_encoder_helper_funcs = {
 142 -       .enable     = cdns_hdmi_imx_encoder_enable,
 143 -       .disable    = cdns_hdmi_imx_encoder_disable,
 144 -       .atomic_check = cdns_hdmi_imx_atomic_check,
 145 -};
 146 -
 147 -static const struct drm_encoder_funcs cdns_hdmi_imx_encoder_funcs = {
 148 -       .destroy = drm_encoder_cleanup,
 149 -};
 150 -
 151 -static struct cdn_plat_data imx8mq_hdmi_drv_data = {
 152 -       .bind   = cdns_hdmi_bind,
 153 -       .unbind = cdns_hdmi_unbind,
 154 -       .phy_init = cdns_hdmi_phy_set_imx8mq,
 155 -};
 156 -
 157 -static struct cdn_plat_data imx8mq_dp_drv_data = {
 158 -       .bind   = cdns_dp_bind,
 159 -       .unbind = cdns_dp_unbind,
 160 -       .phy_init = cdns_dp_phy_init_imx8mq,
 161 -};
 162 -
 163 -static const struct of_device_id cdns_hdmi_imx_dt_ids[] = {
 164 -       { .compatible = "cdn,imx8mq-hdmi",
 165 -         .data = &imx8mq_hdmi_drv_data
 166 -       },
 167 -       { .compatible = "cdn,imx8mq-dp",
 168 -         .data = &imx8mq_dp_drv_data
 169 -       },
 170 -       {},
 171 -};
 172 -MODULE_DEVICE_TABLE(of, cdns_hdmi_imx_dt_ids);
 173 -
 174 -static int cdns_hdmi_imx_bind(struct device *dev, struct device *master,
 175 -                           void *data)
 176 -{
 177 -       struct platform_device *pdev = to_platform_device(dev);
 178 -       const struct cdn_plat_data *plat_data;
 179 -       const struct of_device_id *match;
 180 -       struct drm_device *drm = data;
 181 -       struct drm_encoder *encoder;
 182 -       struct imx_hdmi *hdmi;
 183 -       int ret;
 184 -
 185 -       if (!pdev->dev.of_node)
 186 -               return -ENODEV;
 187 -
 188 -       hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL);
 189 -       if (!hdmi)
 190 -               return -ENOMEM;
 191 -
 192 -       match = of_match_node(cdns_hdmi_imx_dt_ids, pdev->dev.of_node);
 193 -       plat_data = match->data;
 194 -       hdmi->dev = &pdev->dev;
 195 -       encoder = &hdmi->encoder;
 196 -
 197 -       encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node);
 198 -       /*
 199 -        * If we failed to find the CRTC(s) which this encoder is
 200 -        * supposed to be connected to, it's because the CRTC has
 201 -        * not been registered yet.  Defer probing, and hope that
 202 -        * the required CRTC is added later.
 203 -        */
 204 -       if (encoder->possible_crtcs == 0)
 205 -               return -EPROBE_DEFER;
 206 -
 207 -       drm_encoder_helper_add(encoder, &cdns_hdmi_imx_encoder_helper_funcs);
 208 -       drm_encoder_init(drm, encoder, &cdns_hdmi_imx_encoder_funcs,
 209 -                        DRM_MODE_ENCODER_TMDS, NULL);
 210 -
 211 -       ret = plat_data->bind(pdev, encoder, plat_data);
 212 -
 213 -       /*
 214 -        * If cdns_hdmi_bind() fails we'll never call cdns_hdmi_unbind(),
 215 -        * which would have called the encoder cleanup.  Do it manually.
 216 -        */
 217 -       if (ret)
 218 -               drm_encoder_cleanup(encoder);
 219 -
 220 -       return ret;
 221 -}
 222 -
 223 -static void cdns_hdmi_imx_unbind(struct device *dev, struct device *master,
 224 -                              void *data)
 225 -{
 226 -       struct imx_mhdp_device *hdp = dev_get_drvdata(dev);
 227 -
 228 -       hdp->plat_data->unbind(dev);
 229 -}
 230 -
 231 -static const struct component_ops cdns_hdmi_imx_ops = {
 232 -       .bind   = cdns_hdmi_imx_bind,
 233 -       .unbind = cdns_hdmi_imx_unbind,
 234 -};
 235 -
 236 -static int cdns_hdmi_imx_probe(struct platform_device *pdev)
 237 -{
 238 -       return component_add(&pdev->dev, &cdns_hdmi_imx_ops);
 239 -}
 240 -
 241 -static int cdns_hdmi_imx_remove(struct platform_device *pdev)
 242 -{
 243 -       component_del(&pdev->dev, &cdns_hdmi_imx_ops);
 244 -
 245 -       return 0;
 246 -}
 247 -
 248 -static struct platform_driver cdns_hdmi_imx_platform_driver = {
 249 -       .probe  = cdns_hdmi_imx_probe,
 250 -       .remove = cdns_hdmi_imx_remove,
 251 -       .driver = {
 252 -               .name = "cdn-hdp-imx8mq",
 253 -               .of_match_table = cdns_hdmi_imx_dt_ids,
 254 -       },
 255 -};
 256 -
 257 -module_platform_driver(cdns_hdmi_imx_platform_driver);
 258 -
 259 -MODULE_AUTHOR("Sandor YU <sandor.yu@nxp.com>");
 260 -MODULE_LICENSE("GPL");
 261 -MODULE_ALIAS("platform:cdnhdmi-imx");
 262 --- a/drivers/gpu/drm/imx/cdn-mhdp-imx8qm.c
 263 +++ b/drivers/gpu/drm/imx/cdn-mhdp-imx8qm.c
 264 @@ -1,54 +1,40 @@
 265  /*
 266 - * Copyright (C) 2019 NXP Semiconductor, Inc.
 267 + * copyright (c) 2019 nxp semiconductor, inc.
 268   *
 269 - * This program is free software; you can redistribute it and/or modify
 270 - * it under the terms of the GNU General Public License version 2 as
 271 - * published by the Free Software Foundation.
 272 + * this program is free software; you can redistribute it and/or modify
 273 + * it under the terms of the gnu general public license version 2 as
 274 + * published by the free software foundation.
 275   */
 276  #include <dt-bindings/firmware/imx/rsrc.h>
 277 -#include <linux/clk.h>
 278 -#include <linux/module.h>
 279 -#include <linux/platform_device.h>
 280 -#include <linux/component.h>
 281 -#include <drm/drm_of.h>
 282 -#include <drm/drmP.h>
 283 -#include <drm/drm_crtc_helper.h>
 284 -#include <drm/drm_encoder_slave.h>
 285  #include <linux/firmware/imx/sci.h>
 286 -#include <linux/regmap.h>
 287  #include <linux/pm_domain.h>
 288 +#include <linux/clk.h>
 289 +#include <drm/drmP.h>
 290
 291 -#include <drm/bridge/cdns-mhdp-imx.h>
 292 -#include "cdn-mhdp-phy.h"
 293 -#include "imx-drm.h"
 294 +#include "cdns-mhdp-imx.h"
 295
 296  #define CSR_PIXEL_LINK_MUX_CTL         0x00
 297 -#define PL_MUX_CTL_VCP_OFFSET          5
 298 -#define PL_MUX_CTL_HCP_OFFSET          4
 299 +#define CSR_PIXEL_LINK_MUX_VCP_OFFSET          5
 300 +#define CSR_PIXEL_LINK_MUX_HCP_OFFSET          4
 301
 302  #define PLL_800MHZ (800000000)
 303
 304 -struct imx_hdmi {
 305 -       struct device *dev;
 306 -       struct drm_encoder encoder;
 307 -};
 308 -
 309 -static void imx8qm_pixel_link_mux(struct imx_mhdp_device *hdp)
 310 +static void imx8qm_pixel_link_mux(struct imx_mhdp_device *imx_mhdp)
 311  {
 312 -       struct drm_display_mode *mode = &hdp->mhdp.mode;
 313 +       struct drm_display_mode *mode = &imx_mhdp->mhdp.mode;
 314         u32 val;
 315
 316         val = 0x4;      /* RGB */
 317 -       if (hdp->dual_mode)
 318 +       if (imx_mhdp->dual_mode)
 319                 val |= 0x2;     /* pixel link 0 and 1 are active */
 320         if (mode->flags & DRM_MODE_FLAG_PVSYNC)
 321 -               val |= 1 << PL_MUX_CTL_VCP_OFFSET;
 322 +               val |= 1 << CSR_PIXEL_LINK_MUX_VCP_OFFSET;
 323         if (mode->flags & DRM_MODE_FLAG_PHSYNC)
 324 -               val |= 1 << PL_MUX_CTL_HCP_OFFSET;
 325 +               val |= 1 << CSR_PIXEL_LINK_MUX_HCP_OFFSET;
 326         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 327                 val |= 0x2;
 328
 329 -       regmap_write(hdp->regmap_csr, hdp->csr_pxl_mux_reg, val);
 330 +       writel(val, imx_mhdp->mhdp.regs_sec);
 331  }
 332
 333  static void imx8qm_pixel_link_valid(u32 dual_mode)
 334 @@ -120,10 +106,10 @@ static void imx8qm_clk_mux(u8 is_dp)
 335                 imx_sc_misc_set_control(handle, IMX_SC_R_HDMI, IMX_SC_C_MODE, 0);
 336  }
 337
 338 -int imx8qm_clocks_init(struct imx_mhdp_device *hdp)
 339 +int imx8qm_clocks_init(struct imx_mhdp_device *imx_mhdp)
 340  {
 341 -       struct device *dev = hdp->mhdp.dev;
 342 -       struct imx_hdp_clks *clks = &hdp->clks;
 343 +       struct device *dev = imx_mhdp->mhdp.dev;
 344 +       struct imx_hdp_clks *clks = &imx_mhdp->clks;
 345
 346         clks->dig_pll = devm_clk_get(dev, "dig_pll");
 347         if (IS_ERR(clks->dig_pll)) {
 348 @@ -229,10 +215,10 @@ int imx8qm_clocks_init(struct imx_mhdp_d
 349         return true;
 350  }
 351
 352 -static int imx8qm_pixel_clk_enable(struct imx_mhdp_device *hdp)
 353 +static int imx8qm_pixel_clk_enable(struct imx_mhdp_device *imx_mhdp)
 354  {
 355 -       struct imx_hdp_clks *clks = &hdp->clks;
 356 -       struct device *dev = hdp->mhdp.dev;
 357 +       struct imx_hdp_clks *clks = &imx_mhdp->clks;
 358 +       struct device *dev = imx_mhdp->mhdp.dev;
 359         int ret;
 360
 361         ret = clk_prepare_enable(clks->av_pll);
 362 @@ -273,12 +259,11 @@ static int imx8qm_pixel_clk_enable(struc
 363                 return ret;
 364         }
 365         return ret;
 366 -
 367  }
 368
 369 -static void imx8qm_pixel_clk_disable(struct imx_mhdp_device *hdp)
 370 +static void imx8qm_pixel_clk_disable(struct imx_mhdp_device *imx_mhdp)
 371  {
 372 -       struct imx_hdp_clks *clks = &hdp->clks;
 373 +       struct imx_hdp_clks *clks = &imx_mhdp->clks;
 374
 375         clk_disable_unprepare(clks->lpcg_pxl);
 376         clk_disable_unprepare(clks->lpcg_hdp);
 377 @@ -289,14 +274,14 @@ static void imx8qm_pixel_clk_disable(str
 378         clk_disable_unprepare(clks->av_pll);
 379  }
 380
 381 -static void imx8qm_pixel_clk_set_rate(struct imx_mhdp_device *hdp, u32 pclock)
 382 +static void imx8qm_pixel_clk_set_rate(struct imx_mhdp_device *imx_mhdp, u32 pclock)
 383  {
 384 -       struct imx_hdp_clks *clks = &hdp->clks;
 385 +       struct imx_hdp_clks *clks = &imx_mhdp->clks;
 386
 387         /* pixel clock for HDMI */
 388         clk_set_rate(clks->av_pll, pclock);
 389
 390 -       if (hdp->dual_mode == true) {
 391 +       if (imx_mhdp->dual_mode == true) {
 392                 clk_set_rate(clks->clk_pxl, pclock/2);
 393                 clk_set_rate(clks->clk_pxl_link, pclock/2);
 394         } else {
 395 @@ -306,24 +291,11 @@ static void imx8qm_pixel_clk_set_rate(st
 396         clk_set_rate(clks->clk_pxl_mux, pclock);
 397  }
 398
 399 -static void imx8qm_pixel_clk_rate_change(struct imx_mhdp_device *hdp)
 400 -{
 401 -       /* set pixel clock before video mode setup */
 402 -       imx8qm_pixel_clk_disable(hdp);
 403 -
 404 -       imx8qm_pixel_clk_set_rate(hdp, hdp->mhdp.mode.clock * 1000);
 405 -
 406 -       imx8qm_pixel_clk_enable(hdp);
 407 -
 408 -       /* Config pixel link mux */
 409 -       imx8qm_pixel_link_mux(hdp);
 410 -}
 411 -
 412 -static int imx8qm_ipg_clk_enable(struct imx_mhdp_device *hdp)
 413 +static int imx8qm_ipg_clk_enable(struct imx_mhdp_device *imx_mhdp)
 414  {
 415         int ret;
 416 -       struct imx_hdp_clks *clks = &hdp->clks;
 417 -       struct device *dev = hdp->mhdp.dev;
 418 +       struct imx_hdp_clks *clks = &imx_mhdp->clks;
 419 +       struct device *dev = imx_mhdp->mhdp.dev;
 420
 421         ret = clk_prepare_enable(clks->dig_pll);
 422         if (ret < 0) {
 423 @@ -381,25 +353,9 @@ static int imx8qm_ipg_clk_enable(struct
 424         return ret;
 425  }
 426
 427 -static void imx8qm_ipg_clk_disable(struct imx_mhdp_device *hdp)
 428 -{
 429 -       struct imx_hdp_clks *clks = &hdp->clks;
 430 -
 431 -       clk_disable_unprepare(clks->clk_i2s_bypass);
 432 -       clk_disable_unprepare(clks->lpcg_i2s);
 433 -       clk_disable_unprepare(clks->lpcg_apb_ctrl);
 434 -       clk_disable_unprepare(clks->lpcg_apb_csr);
 435 -       clk_disable_unprepare(clks->lpcg_msi);
 436 -       clk_disable_unprepare(clks->lpcg_lis);
 437 -       clk_disable_unprepare(clks->lpcg_apb);
 438 -       clk_disable_unprepare(clks->clk_core);
 439 -       clk_disable_unprepare(clks->clk_ipg);
 440 -       clk_disable_unprepare(clks->dig_pll);
 441 -}
 442 -
 443 -static void imx8qm_ipg_clk_set_rate(struct imx_mhdp_device *hdp)
 444 +static void imx8qm_ipg_clk_set_rate(struct imx_mhdp_device *imx_mhdp)
 445  {
 446 -       struct imx_hdp_clks *clks = &hdp->clks;
 447 +       struct imx_hdp_clks *clks = &imx_mhdp->clks;
 448
 449         /* ipg/core clock */
 450         clk_set_rate(clks->dig_pll,  PLL_800MHZ);
 451 @@ -407,308 +363,171 @@ static void imx8qm_ipg_clk_set_rate(stru
 452         clk_set_rate(clks->clk_ipg,  PLL_800MHZ/8);
 453  }
 454
 455 -static void imx8qm_detach_pm_domains(struct imx_mhdp_device *hdp)
 456 +static void imx8qm_detach_pm_domains(struct imx_mhdp_device *imx_mhdp)
 457  {
 458 -       if (hdp->pd_pll1_link && !IS_ERR(hdp->pd_pll1_link))
 459 -               device_link_del(hdp->pd_pll1_link);
 460 -       if (hdp->pd_pll1_dev && !IS_ERR(hdp->pd_pll1_dev))
 461 -               dev_pm_domain_detach(hdp->pd_pll1_dev, true);
 462 -
 463 -       if (hdp->pd_pll0_link && !IS_ERR(hdp->pd_pll0_link))
 464 -               device_link_del(hdp->pd_pll0_link);
 465 -       if (hdp->pd_pll0_dev && !IS_ERR(hdp->pd_pll0_dev))
 466 -               dev_pm_domain_detach(hdp->pd_pll0_dev, true);
 467 -
 468 -       if (hdp->pd_mhdp_link && !IS_ERR(hdp->pd_mhdp_link))
 469 -               device_link_del(hdp->pd_mhdp_link);
 470 -       if (hdp->pd_mhdp_dev && !IS_ERR(hdp->pd_mhdp_dev))
 471 -               dev_pm_domain_detach(hdp->pd_mhdp_dev, true);
 472 -
 473 -       hdp->pd_mhdp_dev = NULL;
 474 -       hdp->pd_mhdp_link = NULL;
 475 -       hdp->pd_pll0_dev = NULL;
 476 -       hdp->pd_pll0_link = NULL;
 477 -       hdp->pd_pll1_dev = NULL;
 478 -       hdp->pd_pll1_link = NULL;
 479 +       if (imx_mhdp->pd_pll1_link && !IS_ERR(imx_mhdp->pd_pll1_link))
 480 +               device_link_del(imx_mhdp->pd_pll1_link);
 481 +       if (imx_mhdp->pd_pll1_dev && !IS_ERR(imx_mhdp->pd_pll1_dev))
 482 +               dev_pm_domain_detach(imx_mhdp->pd_pll1_dev, true);
 483 +
 484 +       if (imx_mhdp->pd_pll0_link && !IS_ERR(imx_mhdp->pd_pll0_link))
 485 +               device_link_del(imx_mhdp->pd_pll0_link);
 486 +       if (imx_mhdp->pd_pll0_dev && !IS_ERR(imx_mhdp->pd_pll0_dev))
 487 +               dev_pm_domain_detach(imx_mhdp->pd_pll0_dev, true);
 488 +
 489 +       if (imx_mhdp->pd_mhdp_link && !IS_ERR(imx_mhdp->pd_mhdp_link))
 490 +               device_link_del(imx_mhdp->pd_mhdp_link);
 491 +       if (imx_mhdp->pd_mhdp_dev && !IS_ERR(imx_mhdp->pd_mhdp_dev))
 492 +               dev_pm_domain_detach(imx_mhdp->pd_mhdp_dev, true);
 493 +
 494 +       imx_mhdp->pd_mhdp_dev = NULL;
 495 +       imx_mhdp->pd_mhdp_link = NULL;
 496 +       imx_mhdp->pd_pll0_dev = NULL;
 497 +       imx_mhdp->pd_pll0_link = NULL;
 498 +       imx_mhdp->pd_pll1_dev = NULL;
 499 +       imx_mhdp->pd_pll1_link = NULL;
 500  }
 501
 502 -static int imx8qm_attach_pm_domains(struct imx_mhdp_device *hdp)
 503 +static int imx8qm_attach_pm_domains(struct imx_mhdp_device *imx_mhdp)
 504  {
 505 -       struct device *dev = hdp->mhdp.dev;
 506 +       struct device *dev = imx_mhdp->mhdp.dev;
 507         u32 flags = DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME | DL_FLAG_RPM_ACTIVE;
 508         int ret = 0;
 509
 510 -       hdp->pd_mhdp_dev = dev_pm_domain_attach_by_name(dev, "hdmi");
 511 -       if (IS_ERR(hdp->pd_mhdp_dev)) {
 512 -               ret = PTR_ERR(hdp->pd_mhdp_dev);
 513 +       imx_mhdp->pd_mhdp_dev = dev_pm_domain_attach_by_name(dev, "hdmi");
 514 +       if (IS_ERR(imx_mhdp->pd_mhdp_dev)) {
 515 +               ret = PTR_ERR(imx_mhdp->pd_mhdp_dev);
 516                 dev_err(dev, "Failed to attach dc pd dev: %d\n", ret);
 517                 goto fail;
 518         }
 519 -       hdp->pd_mhdp_link = device_link_add(dev, hdp->pd_mhdp_dev, flags);
 520 -       if (IS_ERR(hdp->pd_mhdp_link)) {
 521 -               ret = PTR_ERR(hdp->pd_mhdp_link);
 522 +       imx_mhdp->pd_mhdp_link = device_link_add(dev, imx_mhdp->pd_mhdp_dev, flags);
 523 +       if (IS_ERR(imx_mhdp->pd_mhdp_link)) {
 524 +               ret = PTR_ERR(imx_mhdp->pd_mhdp_link);
 525                 dev_err(dev, "Failed to add device link to dc pd dev: %d\n",
 526                         ret);
 527                 goto fail;
 528         }
 529
 530 -       hdp->pd_pll0_dev = dev_pm_domain_attach_by_name(dev, "pll0");
 531 -       if (IS_ERR(hdp->pd_pll0_dev)) {
 532 -               ret = PTR_ERR(hdp->pd_pll0_dev);
 533 +       imx_mhdp->pd_pll0_dev = dev_pm_domain_attach_by_name(dev, "pll0");
 534 +       if (IS_ERR(imx_mhdp->pd_pll0_dev)) {
 535 +               ret = PTR_ERR(imx_mhdp->pd_pll0_dev);
 536                 dev_err(dev, "Failed to attach pll0 pd dev: %d\n", ret);
 537                 goto fail;
 538         }
 539 -       hdp->pd_pll0_link = device_link_add(dev, hdp->pd_pll0_dev, flags);
 540 -       if (IS_ERR(hdp->pd_pll0_link)) {
 541 -               ret = PTR_ERR(hdp->pd_pll0_link);
 542 +       imx_mhdp->pd_pll0_link = device_link_add(dev, imx_mhdp->pd_pll0_dev, flags);
 543 +       if (IS_ERR(imx_mhdp->pd_pll0_link)) {
 544 +               ret = PTR_ERR(imx_mhdp->pd_pll0_link);
 545                 dev_err(dev, "Failed to add device link to pll0 pd dev: %d\n",
 546                         ret);
 547                 goto fail;
 548         }
 549
 550 -       hdp->pd_pll1_dev = dev_pm_domain_attach_by_name(dev, "pll1");
 551 -       if (IS_ERR(hdp->pd_pll1_dev)) {
 552 -               ret = PTR_ERR(hdp->pd_pll1_dev);
 553 +       imx_mhdp->pd_pll1_dev = dev_pm_domain_attach_by_name(dev, "pll1");
 554 +       if (IS_ERR(imx_mhdp->pd_pll1_dev)) {
 555 +               ret = PTR_ERR(imx_mhdp->pd_pll1_dev);
 556                 dev_err(dev, "Failed to attach pll0 pd dev: %d\n", ret);
 557                 goto fail;
 558         }
 559 -       hdp->pd_pll1_link = device_link_add(dev, hdp->pd_pll1_dev, flags);
 560 -       if (IS_ERR(hdp->pd_pll1_link)) {
 561 -               ret = PTR_ERR(hdp->pd_pll1_link);
 562 +       imx_mhdp->pd_pll1_link = device_link_add(dev, imx_mhdp->pd_pll1_dev, flags);
 563 +       if (IS_ERR(imx_mhdp->pd_pll1_link)) {
 564 +               ret = PTR_ERR(imx_mhdp->pd_pll1_link);
 565                 dev_err(dev, "Failed to add device link to pll1 pd dev: %d\n",
 566                         ret);
 567                 goto fail;
 568         }
 569  fail:
 570 -       imx8qm_detach_pm_domains(hdp);
 571 +       imx8qm_detach_pm_domains(imx_mhdp);
 572         return ret;
 573  }
 574
 575 -static int imx8qm_firmware_init(struct imx_mhdp_device *hdp)
 576 +static void imx8qm_mhdp_power_on(struct cdns_mhdp_device *mhdp)
 577  {
 578 -       u32 rate;
 579 -       int ret;
 580 -
 581 +       struct imx_mhdp_device *imx_mhdp =
 582 +                               container_of(mhdp, struct imx_mhdp_device, mhdp);
 583         /* Power on PM Domains */
 584 -       imx8qm_attach_pm_domains(hdp);
 585 +
 586 +       imx8qm_attach_pm_domains(imx_mhdp);
 587
 588         /* clock init and  rate set */
 589 -       imx8qm_clocks_init(hdp);
 590 +       imx8qm_clocks_init(imx_mhdp);
 591
 592 -       imx8qm_ipg_clk_set_rate(hdp);
 593 +       imx8qm_ipg_clk_set_rate(imx_mhdp);
 594
 595         /* Init pixel clock with 148.5MHz before FW init */
 596 -       imx8qm_pixel_clk_set_rate(hdp, 148500000);
 597 +       imx8qm_pixel_clk_set_rate(imx_mhdp, 148500000);
 598
 599 -       imx8qm_ipg_clk_enable(hdp);
 600 +       imx8qm_ipg_clk_enable(imx_mhdp);
 601
 602 -       imx8qm_clk_mux(hdp->plat_data->is_dp);
 603 +       imx8qm_clk_mux(imx_mhdp->mhdp.plat_data->is_dp);
 604
 605 -       imx8qm_pixel_clk_enable(hdp);
 606 +       imx8qm_pixel_clk_enable(imx_mhdp);
 607
 608         imx8qm_phy_reset(1);
 609 -
 610 -       hdp->csr_pxl_mux_reg = 0;
 611 -       hdp->csr_ctrl0_reg = 0x8;
 612 -       hdp->csr_ctrl0_sec = 0xc;
 613 -       /* iMX8QM HDP register, Remap HPD memory address to low 4K */
 614 -       regmap_write(hdp->regmap_csr, hdp->csr_ctrl0_reg, 0);
 615 -
 616 -       /* configure HDMI/DP core clock */
 617 -       rate = clk_get_rate(hdp->clks.clk_core);
 618 -       cdns_mhdp_set_fw_clk(&hdp->mhdp, rate);
 619 -
 620 -       /* un-reset ucpu */
 621 -       writel(0,  (APB_CTRL << 2) + hdp->mhdp.regs);
 622 -       DRM_INFO("Started firmware!\n");
 623 -
 624 -       ret = cdns_mhdp_check_alive(&hdp->mhdp);
 625 -       if (ret == false) {
 626 -               DRM_ERROR("NO HDMI FW running\n");
 627 -               return -ENXIO;
 628 -       }
 629 -
 630 -       /* turn on IP activity */
 631 -       cdns_mhdp_set_firmware_active(&hdp->mhdp, 1);
 632 -
 633 -       DRM_INFO("HDP FW Version - ver %d verlib %d\n",
 634 -                       __raw_readb(VER_L + hdp->mhdp.regs) + (__raw_readb(VER_H + hdp->mhdp.regs) << 8),
 635 -       __raw_readb(VER_LIB_L_ADDR + hdp->mhdp.regs) + (__raw_readb(VER_LIB_H_ADDR + hdp->mhdp.regs) << 8));
 636 -
 637 -       return 0;
 638  }
 639
 640 -static void cdns_hdmi_imx_encoder_disable(struct drm_encoder *encoder)
 641 +void cdns_mhdp_plat_init_imx8qm(struct cdns_mhdp_device *mhdp)
 642  {
 643 -       struct imx_mhdp_device *hdp = encoder->bridge->driver_private;
 644 +       struct imx_mhdp_device *imx_mhdp =
 645 +                               container_of(mhdp, struct imx_mhdp_device, mhdp);
 646
 647 -       imx8qm_pixel_link_sync_disable(hdp->dual_mode);
 648 -       imx8qm_pixel_link_invalid(hdp->dual_mode);
 649 +       imx8qm_pixel_link_sync_disable(imx_mhdp->dual_mode);
 650 +       imx8qm_pixel_link_invalid(imx_mhdp->dual_mode);
 651  }
 652
 653 -static void cdns_hdmi_imx_encoder_enable(struct drm_encoder *encoder)
 654 +void cdns_mhdp_plat_deinit_imx8qm(struct cdns_mhdp_device *mhdp)
 655  {
 656 -       struct imx_mhdp_device *hdp = encoder->bridge->driver_private;
 657 +       struct imx_mhdp_device *imx_mhdp =
 658 +                               container_of(mhdp, struct imx_mhdp_device, mhdp);
 659
 660 -       imx8qm_pixel_link_valid(hdp->dual_mode);
 661 -       imx8qm_pixel_link_sync_enable(hdp->dual_mode);
 662 +       imx8qm_pixel_link_valid(imx_mhdp->dual_mode);
 663 +       imx8qm_pixel_link_sync_enable(imx_mhdp->dual_mode);
 664  }
 665
 666 -static int cdns_hdmi_imx_encoder_atomic_check(struct drm_encoder *encoder,
 667 -                                   struct drm_crtc_state *crtc_state,
 668 -                                   struct drm_connector_state *conn_state)
 669 +void cdns_mhdp_pclk_rate_imx8qm(struct cdns_mhdp_device *mhdp)
 670  {
 671 -       struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc_state);
 672 -
 673 -       imx_crtc_state->bus_format = MEDIA_BUS_FMT_RGB101010_1X30;
 674 -       return 0;
 675 -}
 676 +       struct imx_mhdp_device *imx_mhdp =
 677 +                               container_of(mhdp, struct imx_mhdp_device, mhdp);
 678
 679 -static const struct drm_encoder_helper_funcs cdns_hdmi_imx_encoder_helper_funcs = {
 680 -       .enable     = cdns_hdmi_imx_encoder_enable,
 681 -       .disable    = cdns_hdmi_imx_encoder_disable,
 682 -       .atomic_check = cdns_hdmi_imx_encoder_atomic_check,
 683 -};
 684 -
 685 -static const struct drm_encoder_funcs cdns_hdmi_imx_encoder_funcs = {
 686 -       .destroy = drm_encoder_cleanup,
 687 -};
 688 -
 689 -#if 0
 690 -static struct cdn_plat_data imx8mq_hdmi_drv_data = {
 691 -       .bind   = cdns_hdmi_bind,
 692 -       .unbind = cdns_hdmi_unbind,
 693 -       .phy_init = cdns_hdmi_phy_set_imx8mq,
 694 -};
 695 -
 696 -static struct cdn_plat_data imx8mq_dp_drv_data = {
 697 -       .bind   = cdns_dp_bind,
 698 -       .unbind = cdns_dp_unbind,
 699 -       .phy_init = cdns_dp_phy_init_imx8mq,
 700 -};
 701 -#endif
 702 -
 703 -static struct cdn_plat_data imx8qm_hdmi_drv_data = {
 704 -       .bind   = cdns_hdmi_bind,
 705 -       .unbind = cdns_hdmi_unbind,
 706 -       .phy_init = cdns_hdmi_phy_set_imx8qm,
 707 -       .fw_init = imx8qm_firmware_init,
 708 -       .pclock_change = imx8qm_pixel_clk_rate_change,
 709 -};
 710 -
 711 -static struct cdn_plat_data imx8qm_dp_drv_data = {
 712 -       .bind   = cdns_dp_bind,
 713 -       .unbind = cdns_dp_unbind,
 714 -       .phy_init = cdns_dp_phy_init_imx8qm,
 715 -       .fw_init = imx8qm_firmware_init,
 716 -       .pclock_change = imx8qm_pixel_clk_rate_change,
 717 -       .is_dp = true,
 718 -};
 719 -
 720 -static const struct of_device_id cdns_hdmi_imx_dt_ids[] = {
 721 -#if 0
 722 -       { .compatible = "cdn,imx8mq-hdmi",
 723 -         .data = &imx8mq_hdmi_drv_data
 724 -       },
 725 -       { .compatible = "cdn,imx8mq-dp",
 726 -         .data = &imx8mq_dp_drv_data
 727 -       },
 728 -#endif
 729 -       { .compatible = "cdn,imx8qm-hdmi",
 730 -         .data = &imx8qm_hdmi_drv_data
 731 -       },
 732 -       { .compatible = "cdn,imx8qm-dp",
 733 -         .data = &imx8qm_dp_drv_data
 734 -       },
 735 -       {},
 736 -};
 737 -MODULE_DEVICE_TABLE(of, cdns_hdmi_imx_dt_ids);
 738 -
 739 -static int cdns_hdmi_imx_bind(struct device *dev, struct device *master,
 740 -                           void *data)
 741 -{
 742 -       struct platform_device *pdev = to_platform_device(dev);
 743 -       const struct cdn_plat_data *plat_data;
 744 -       const struct of_device_id *match;
 745 -       struct drm_device *drm = data;
 746 -       struct drm_encoder *encoder;
 747 -       struct imx_hdmi *hdmi;
 748 -       int ret;
 749 +       /* set pixel clock before video mode setup */
 750 +       imx8qm_pixel_clk_disable(imx_mhdp);
 751
 752 -       if (!pdev->dev.of_node)
 753 -               return -ENODEV;
 754 +       imx8qm_pixel_clk_set_rate(imx_mhdp, imx_mhdp->mhdp.mode.clock * 1000);
 755
 756 -       hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL);
 757 -       if (!hdmi)
 758 -               return -ENOMEM;
 759 -
 760 -       match = of_match_node(cdns_hdmi_imx_dt_ids, pdev->dev.of_node);
 761 -       plat_data = match->data;
 762 -       hdmi->dev = &pdev->dev;
 763 -       encoder = &hdmi->encoder;
 764 -
 765 -       encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node);
 766 -       /*
 767 -        * If we failed to find the CRTC(s) which this encoder is
 768 -        * supposed to be connected to, it's because the CRTC has
 769 -        * not been registered yet.  Defer probing, and hope that
 770 -        * the required CRTC is added later.
 771 -        */
 772 -       if (encoder->possible_crtcs == 0)
 773 -               return -EPROBE_DEFER;
 774 -
 775 -       drm_encoder_helper_add(encoder, &cdns_hdmi_imx_encoder_helper_funcs);
 776 -       drm_encoder_init(drm, encoder, &cdns_hdmi_imx_encoder_funcs,
 777 -                        DRM_MODE_ENCODER_TMDS, NULL);
 778 -
 779 -       ret = plat_data->bind(pdev, encoder, plat_data);
 780 -
 781 -       /*
 782 -        * If cdns_hdmi_bind() fails we'll never call cdns_hdmi_unbind(),
 783 -        * which would have called the encoder cleanup.  Do it manually.
 784 -        */
 785 -       if (ret)
 786 -               drm_encoder_cleanup(encoder);
 787 +       imx8qm_pixel_clk_enable(imx_mhdp);
 788
 789 -       return ret;
 790 +       /* Config pixel link mux */
 791 +       imx8qm_pixel_link_mux(imx_mhdp);
 792  }
 793
 794 -static void cdns_hdmi_imx_unbind(struct device *dev, struct device *master,
 795 -                              void *data)
 796 +int cdns_mhdp_firmware_init_imx8qm(struct cdns_mhdp_device *mhdp)
 797  {
 798 -       struct imx_mhdp_device *hdp = dev_get_drvdata(dev);
 799 +       struct imx_mhdp_device *imx_mhdp =
 800 +                               container_of(mhdp, struct imx_mhdp_device, mhdp);
 801 +       u32 rate;
 802 +       int ret;
 803
 804 -       hdp->plat_data->unbind(dev);
 805 -}
 806 +       imx8qm_mhdp_power_on(mhdp);
 807
 808 -static const struct component_ops cdns_hdmi_imx8qm_ops = {
 809 -       .bind   = cdns_hdmi_imx_bind,
 810 -       .unbind = cdns_hdmi_imx_unbind,
 811 -};
 812 +       /* configure HDMI/DP core clock */
 813 +       rate = clk_get_rate(imx_mhdp->clks.clk_core);
 814 +       cdns_mhdp_set_fw_clk(&imx_mhdp->mhdp, rate);
 815
 816 -static int cdns_hdmi_imx_probe(struct platform_device *pdev)
 817 -{
 818 -       return component_add(&pdev->dev, &cdns_hdmi_imx8qm_ops);
 819 -}
 820 +       /* un-reset ucpu */
 821 +       cdns_mhdp_bus_write(0, &imx_mhdp->mhdp, APB_CTRL);
 822 +       DRM_INFO("Started firmware!\n");
 823
 824 -static int cdns_hdmi_imx_remove(struct platform_device *pdev)
 825 -{
 826 -       component_del(&pdev->dev, &cdns_hdmi_imx8qm_ops);
 827 +       ret = cdns_mhdp_check_alive(&imx_mhdp->mhdp);
 828 +       if (ret == false) {
 829 +               DRM_ERROR("NO HDMI FW running\n");
 830 +               return -ENXIO;
 831 +       }
 832 +
 833 +       /* turn on IP activity */
 834 +       cdns_mhdp_set_firmware_active(&imx_mhdp->mhdp, 1);
 835 +
 836 +       DRM_INFO("HDP FW Version - ver %d verlib %d\n",
 837 +                       cdns_mhdp_bus_read(mhdp, VER_L) + (cdns_mhdp_bus_read(mhdp, VER_H) << 8),
 838 +                       cdns_mhdp_bus_read(mhdp, VER_LIB_H_ADDR) + (cdns_mhdp_bus_read(mhdp, VER_LIB_H_ADDR) << 8));
 839
 840         return 0;
 841  }
 842 -
 843 -static struct platform_driver cdns_hdmi_imx_platform_driver = {
 844 -       .probe  = cdns_hdmi_imx_probe,
 845 -       .remove = cdns_hdmi_imx_remove,
 846 -       .driver = {
 847 -               .name = "cdn-hdp-imx8qm",
 848 -               .of_match_table = cdns_hdmi_imx_dt_ids,
 849 -       },
 850 -};
 851 -
 852 -module_platform_driver(cdns_hdmi_imx_platform_driver);
 853 -
 854 -MODULE_AUTHOR("Sandor YU <sandor.yu@nxp.com>");
 855 -MODULE_LICENSE("GPL");
 856 -MODULE_ALIAS("platform:cdnhdmi-imx");
 857 --- /dev/null
 858 +++ b/drivers/gpu/drm/imx/cdn-mhdp-imxdrv.c
 859 @@ -0,0 +1,202 @@
 860 +/*
 861 + * copyright (c) 2019 nxp semiconductor, inc.
 862 + *
 863 + * this program is free software; you can redistribute it and/or modify
 864 + * it under the terms of the gnu general public license version 2 as
 865 + * published by the free software foundation.
 866 + */
 867 +#include <linux/module.h>
 868 +#include <linux/platform_device.h>
 869 +#include <linux/component.h>
 870 +#include <drm/drm_of.h>
 871 +#include <drm/drmP.h>
 872 +#include <drm/drm_crtc_helper.h>
 873 +#include <drm/drm_encoder_slave.h>
 874 +
 875 +#include "cdns-mhdp-imx.h"
 876 +#include "cdn-mhdp-phy.h"
 877 +#include "imx-drm.h"
 878 +
 879 +static void cdns_mhdp_imx_encoder_disable(struct drm_encoder *encoder)
 880 +{
 881 +       struct cdns_mhdp_device *mhdp = encoder->bridge->driver_private;
 882 +
 883 +       cdns_mhdp_plat_call(mhdp, plat_init);
 884 +}
 885 +
 886 +static void cdns_mhdp_imx_encoder_enable(struct drm_encoder *encoder)
 887 +{
 888 +       struct cdns_mhdp_device *mhdp = encoder->bridge->driver_private;
 889 +
 890 +       cdns_mhdp_plat_call(mhdp, plat_deinit);
 891 +}
 892 +
 893 +static int cdns_mhdp_imx_encoder_atomic_check(struct drm_encoder *encoder,
 894 +                                   struct drm_crtc_state *crtc_state,
 895 +                                   struct drm_connector_state *conn_state)
 896 +{
 897 +       struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc_state);
 898 +       struct cdns_mhdp_device *mhdp = encoder->bridge->driver_private;
 899 +
 900 +       if (mhdp->plat_data->video_format != 0)
 901 +               imx_crtc_state->bus_format = mhdp->plat_data->video_format;
 902 +       return 0;
 903 +}
 904 +
 905 +static const struct drm_encoder_helper_funcs cdns_mhdp_imx_encoder_helper_funcs = {
 906 +       .enable     = cdns_mhdp_imx_encoder_enable,
 907 +       .disable    = cdns_mhdp_imx_encoder_disable,
 908 +       .atomic_check = cdns_mhdp_imx_encoder_atomic_check,
 909 +};
 910 +
 911 +static const struct drm_encoder_funcs cdns_mhdp_imx_encoder_funcs = {
 912 +       .destroy = drm_encoder_cleanup,
 913 +};
 914 +
 915 +static struct cdns_plat_data imx8mq_hdmi_drv_data = {
 916 +       .bind   = cdns_hdmi_bind,
 917 +       .unbind = cdns_hdmi_unbind,
 918 +       .phy_set = cdns_hdmi_phy_set_imx8mq,
 919 +       .bus_type = BUS_TYPE_NORMAL_APB,
 920 +};
 921 +
 922 +static struct cdns_plat_data imx8mq_dp_drv_data = {
 923 +       .bind   = cdns_dp_bind,
 924 +       .unbind = cdns_dp_unbind,
 925 +       .phy_set = cdns_dp_phy_set_imx8mq,
 926 +       .bus_type = BUS_TYPE_NORMAL_APB,
 927 +};
 928 +
 929 +static struct cdns_plat_data imx8qm_hdmi_drv_data = {
 930 +       .bind   = cdns_hdmi_bind,
 931 +       .unbind = cdns_hdmi_unbind,
 932 +       .phy_set = cdns_hdmi_phy_set_imx8qm,
 933 +       .firmware_init = cdns_mhdp_firmware_init_imx8qm,
 934 +       .pclk_rate = cdns_mhdp_pclk_rate_imx8qm,
 935 +       .plat_init = cdns_mhdp_plat_init_imx8qm,
 936 +       .plat_deinit = cdns_mhdp_plat_deinit_imx8qm,
 937 +       .bus_type = BUS_TYPE_LOW4K_APB,
 938 +       .video_format =  MEDIA_BUS_FMT_RGB101010_1X30,
 939 +};
 940 +
 941 +static struct cdns_plat_data imx8qm_dp_drv_data = {
 942 +       .bind   = cdns_dp_bind,
 943 +       .unbind = cdns_dp_unbind,
 944 +       .phy_set = cdns_dp_phy_set_imx8qm,
 945 +       .firmware_init = cdns_mhdp_firmware_init_imx8qm,
 946 +       .pclk_rate = cdns_mhdp_pclk_rate_imx8qm,
 947 +       .plat_init = cdns_mhdp_plat_init_imx8qm,
 948 +       .plat_deinit = cdns_mhdp_plat_deinit_imx8qm,
 949 +       .bus_type = BUS_TYPE_LOW4K_APB,
 950 +       .video_format =  MEDIA_BUS_FMT_RGB101010_1X30,
 951 +       .is_dp = true,
 952 +};
 953 +
 954 +static const struct of_device_id cdns_mhdp_imx_dt_ids[] = {
 955 +       { .compatible = "cdn,imx8mq-hdmi",
 956 +         .data = &imx8mq_hdmi_drv_data
 957 +       },
 958 +       { .compatible = "cdn,imx8mq-dp",
 959 +         .data = &imx8mq_dp_drv_data
 960 +       },
 961 +       { .compatible = "cdn,imx8qm-hdmi",
 962 +         .data = &imx8qm_hdmi_drv_data
 963 +       },
 964 +       { .compatible = "cdn,imx8qm-dp",
 965 +         .data = &imx8qm_dp_drv_data
 966 +       },
 967 +       {},
 968 +};
 969 +MODULE_DEVICE_TABLE(of, cdns_mhdp_imx_dt_ids);
 970 +
 971 +static int cdns_mhdp_imx_bind(struct device *dev, struct device *master,
 972 +                           void *data)
 973 +{
 974 +       struct platform_device *pdev = to_platform_device(dev);
 975 +       const struct cdns_plat_data *plat_data;
 976 +       const struct of_device_id *match;
 977 +       struct drm_device *drm = data;
 978 +       struct drm_encoder *encoder;
 979 +       struct imx_mhdp_device *imx_mhdp;
 980 +       int ret;
 981 +
 982 +       if (!pdev->dev.of_node)
 983 +               return -ENODEV;
 984 +
 985 +       imx_mhdp = devm_kzalloc(&pdev->dev, sizeof(*imx_mhdp), GFP_KERNEL);
 986 +       if (!imx_mhdp)
 987 +               return -ENOMEM;
 988 +
 989 +       match = of_match_node(cdns_mhdp_imx_dt_ids, pdev->dev.of_node);
 990 +       plat_data = match->data;
 991 +       encoder = &imx_mhdp->encoder;
 992 +
 993 +       encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node);
 994 +       /*
 995 +        * If we failed to find the CRTC(s) which this encoder is
 996 +        * supposed to be connected to, it's because the CRTC has
 997 +        * not been registered yet.  Defer probing, and hope that
 998 +        * the required CRTC is added later.
 999 +        */
1000 +       if (encoder->possible_crtcs == 0)
1001 +               return -EPROBE_DEFER;
1002 +
1003 +       drm_encoder_helper_add(encoder, &cdns_mhdp_imx_encoder_helper_funcs);
1004 +       drm_encoder_init(drm, encoder, &cdns_mhdp_imx_encoder_funcs,
1005 +                        DRM_MODE_ENCODER_TMDS, NULL);
1006 +
1007 +
1008 +       imx_mhdp->mhdp.plat_data = plat_data;
1009 +       imx_mhdp->mhdp.dev = dev;
1010 +       imx_mhdp->mhdp.bus_type = plat_data->bus_type;
1011 +       ret = plat_data->bind(pdev, encoder, &imx_mhdp->mhdp);
1012 +       /*
1013 +        * If cdns_mhdp_bind() fails we'll never call cdns_mhdp_unbind(),
1014 +        * which would have called the encoder cleanup.  Do it manually.
1015 +        */
1016 +       if (ret < 0)
1017 +               drm_encoder_cleanup(encoder);
1018 +
1019 +       imx_mhdp->dual_mode = false;
1020 +       return ret;
1021 +}
1022 +
1023 +static void cdns_mhdp_imx_unbind(struct device *dev, struct device *master,
1024 +                              void *data)
1025 +{
1026 +       struct imx_mhdp_device *imx_mhdp = dev_get_drvdata(dev);
1027 +
1028 +       imx_mhdp->mhdp.plat_data->unbind(dev);
1029 +}
1030 +
1031 +static const struct component_ops cdns_mhdp_imx_ops = {
1032 +       .bind   = cdns_mhdp_imx_bind,
1033 +       .unbind = cdns_mhdp_imx_unbind,
1034 +};
1035 +
1036 +static int cdns_mhdp_imx_probe(struct platform_device *pdev)
1037 +{
1038 +       return component_add(&pdev->dev, &cdns_mhdp_imx_ops);
1039 +}
1040 +
1041 +static int cdns_mhdp_imx_remove(struct platform_device *pdev)
1042 +{
1043 +       component_del(&pdev->dev, &cdns_mhdp_imx_ops);
1044 +
1045 +       return 0;
1046 +}
1047 +
1048 +static struct platform_driver cdns_mhdp_imx_platform_driver = {
1049 +       .probe  = cdns_mhdp_imx_probe,
1050 +       .remove = cdns_mhdp_imx_remove,
1051 +       .driver = {
1052 +               .name = "cdn-hdp-imx8qm",
1053 +               .of_match_table = cdns_mhdp_imx_dt_ids,
1054 +       },
1055 +};
1056 +
1057 +module_platform_driver(cdns_mhdp_imx_platform_driver);
1058 +
1059 +MODULE_AUTHOR("Sandor YU <sandor.yu@nxp.com>");
1060 +MODULE_LICENSE("GPL");
1061 +MODULE_ALIAS("platform:cdnhdmi-imx");
1062 --- a/drivers/gpu/drm/imx/cdn-mhdp-phy.h
1063 +++ b/drivers/gpu/drm/imx/cdn-mhdp-phy.h
1064 @@ -10,7 +10,7 @@
1065  #ifndef _CDN_DP_PHY_H
1066  #define _CDN_DP_PHY_H
1067
1068 -#include <drm/bridge/cdns-mhdp-imx.h>
1069 +#include <drm/bridge/cdns-mhdp-common.h>
1070
1071  #define CMN_SSM_BIAS_TMR                0x0022
1072  #define CMN_PLLSM0_PLLEN_TMR            0x0029
1073 @@ -146,8 +146,8 @@
1074  #define PHY_PMA_ISO_RX_DATA_LO          0xCC16
1075  #define PHY_PMA_ISO_RX_DATA_HI          0xCC17
1076
1077 -int cdns_dp_phy_init_imx8mq(struct imx_mhdp_device *hdp);
1078 -int cdns_dp_phy_init_imx8qm(struct imx_mhdp_device *hdp);
1079 -int cdns_hdmi_phy_set_imx8mq(struct imx_mhdp_device *hdp);
1080 -int cdns_hdmi_phy_set_imx8qm(struct imx_mhdp_device *hdp);
1081 -#endif /* _CDN_DP_PHY_H */
1082 +int cdns_dp_phy_set_imx8mq(struct cdns_mhdp_device *hdp);
1083 +int cdns_dp_phy_set_imx8qm(struct cdns_mhdp_device *hdp);
1084 +int cdns_hdmi_phy_set_imx8mq(struct cdns_mhdp_device *hdp);
1085 +int cdns_hdmi_phy_set_imx8qm(struct cdns_mhdp_device *hdp);
1086 +#endif /* _CDNS_MHDP_PHY_H */
1087 --- /dev/null
1088 +++ b/drivers/gpu/drm/imx/cdns-mhdp-imx.h
1089 @@ -0,0 +1,80 @@
1090 +/*
1091 + * Cadence High-Definition Multimedia Interface (HDMI) driver
1092 + *
1093 + * Copyright (C) 2019 NXP Semiconductor, Inc.
1094 + *
1095 + * This program is free software; you can redistribute it and/or modify
1096 + * it under the terms of the GNU General Public License as published by
1097 + * the Free Software Foundation; either version 2 of the License, or
1098 + * (at your option) any later version.
1099 + *
1100 + */
1101 +#ifndef CDNS_MHDP_IMX_H_
1102 +#define CDNS_MHDP_IMX_H_
1103 +
1104 +#include <drm/bridge/cdns-mhdp-common.h>
1105 +#include <drm/drm_encoder_slave.h>
1106 +
1107 +
1108 +#define HDP_DUAL_MODE_MIN_PCLK_RATE    300000  /* KHz */
1109 +#define HDP_SINGLE_MODE_MAX_WIDTH      1920
1110 +
1111 +static inline bool video_is_dual_mode(const struct drm_display_mode *mode)
1112 +{
1113 +       return (mode->clock > HDP_DUAL_MODE_MIN_PCLK_RATE ||
1114 +               mode->hdisplay > HDP_SINGLE_MODE_MAX_WIDTH) ? true : false;
1115 +}
1116 +
1117 +struct imx_mhdp_device;
1118 +
1119 +struct imx_hdp_clks {
1120 +       struct clk *av_pll;
1121 +       struct clk *dig_pll;
1122 +       struct clk *clk_ipg;
1123 +       struct clk *clk_core;
1124 +       struct clk *clk_pxl;
1125 +       struct clk *clk_pxl_mux;
1126 +       struct clk *clk_pxl_link;
1127 +
1128 +       struct clk *lpcg_hdp;
1129 +       struct clk *lpcg_msi;
1130 +       struct clk *lpcg_pxl;
1131 +       struct clk *lpcg_vif;
1132 +       struct clk *lpcg_lis;
1133 +       struct clk *lpcg_apb;
1134 +       struct clk *lpcg_apb_csr;
1135 +       struct clk *lpcg_apb_ctrl;
1136 +
1137 +       struct clk *lpcg_i2s;
1138 +       struct clk *clk_i2s_bypass;
1139 +};
1140 +
1141 +struct imx_mhdp_device {
1142 +       struct cdns_mhdp_device mhdp;
1143 +       struct drm_encoder encoder;
1144 +
1145 +       struct mutex audio_mutex;
1146 +       spinlock_t audio_lock;
1147 +       bool connected;
1148 +       bool active;
1149 +       bool suspended;
1150 +       struct imx_hdp_clks clks;
1151 +
1152 +       int bus_type;
1153 +
1154 +       u32 dual_mode;
1155 +
1156 +       struct device           *pd_mhdp_dev;
1157 +       struct device           *pd_pll0_dev;
1158 +       struct device           *pd_pll1_dev;
1159 +       struct device_link      *pd_mhdp_link;
1160 +       struct device_link      *pd_pll0_link;
1161 +       struct device_link      *pd_pll1_link;
1162 +
1163 +//     u32 phy_init;
1164 +};
1165 +void cdns_mhdp_plat_init_imx8qm(struct cdns_mhdp_device *mhdp);
1166 +void cdns_mhdp_plat_deinit_imx8qm(struct cdns_mhdp_device *mhdp);
1167 +void cdns_mhdp_pclk_rate_imx8qm(struct cdns_mhdp_device *mhdp);
1168 +int cdns_mhdp_firmware_init_imx8qm(struct cdns_mhdp_device *mhdp);
1169 +#endif /* CDNS_MHDP_IMX_H_ */