target/linux/layerscape/patches-5.4/813-pm-0002-fsl_pmc-update-device-bindings.patch

   1 From f48ec27500239c0400114327ecbbfec34bfc2deb Mon Sep 17 00:00:00 2001
   2 From: Li Yang <leoli@freescale.com>
   3 Date: Wed, 22 Feb 2012 15:52:50 +0000
   4 Subject: [PATCH] fsl_pmc: update device bindings
   5
   6 Signed-off-by: Li Yang <leoyang.li@nxp.com>
   7 Signed-off-by: Zhao Chenhui <chenhui.zhao@nxp.com>
   8 Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
   9 ---
  10  .../devicetree/bindings/powerpc/fsl/pmc.txt        | 59 +++++++++++++---------
  11  1 file changed, 34 insertions(+), 25 deletions(-)
  12
  13 --- a/Documentation/devicetree/bindings/powerpc/fsl/pmc.txt
  14 +++ b/Documentation/devicetree/bindings/powerpc/fsl/pmc.txt
  15 @@ -9,15 +9,20 @@ Properties:
  16
  17    "fsl,mpc8548-pmc" should be listed for any chip whose PMC is
  18    compatible.  "fsl,mpc8536-pmc" should also be listed for any chip
  19 -  whose PMC is compatible, and implies deep-sleep capability.
  20 +  whose PMC is compatible, and implies deep-sleep capability and
  21 +  wake on user defined packet(wakeup on ARP).
  22 +
  23 +  "fsl,p1022-pmc" should be listed for any chip whose PMC is
  24 +  compatible, and implies lossless Ethernet capability during sleep.
  25
  26    "fsl,mpc8641d-pmc" should be listed for any chip whose PMC is
  27    compatible; all statements below that apply to "fsl,mpc8548-pmc" also
  28    apply to "fsl,mpc8641d-pmc".
  29
  30    Compatibility does not include bit assignments in SCCR/PMCDR/DEVDISR; these
  31 -  bit assignments are indicated via the sleep specifier in each device's
  32 -  sleep property.
  33 +  bit assignments are indicated via the clock nodes.  Device which has a
  34 +  controllable clock source should have a "fsl,pmc-handle" property pointing
  35 +  to the clock node.
  36
  37  - reg: For devices compatible with "fsl,mpc8349-pmc", the first resource
  38    is the PMC block, and the second resource is the Clock Configuration
  39 @@ -33,31 +38,35 @@ Properties:
  40    this is a phandle to an "fsl,gtm" node on which timer 4 can be used as
  41    a wakeup source from deep sleep.
  42
  43 -Sleep specifiers:
  44 -
  45 -  fsl,mpc8349-pmc: Sleep specifiers consist of one cell.  For each bit
  46 -  that is set in the cell, the corresponding bit in SCCR will be saved
  47 -  and cleared on suspend, and restored on resume.  This sleep controller
  48 -  supports disabling and resuming devices at any time.
  49 -
  50 -  fsl,mpc8536-pmc: Sleep specifiers consist of three cells, the third of
  51 -  which will be ORed into PMCDR upon suspend, and cleared from PMCDR
  52 -  upon resume.  The first two cells are as described for fsl,mpc8578-pmc.
  53 -  This sleep controller only supports disabling devices during system
  54 -  sleep, or permanently.
  55 -
  56 -  fsl,mpc8548-pmc: Sleep specifiers consist of one or two cells, the
  57 -  first of which will be ORed into DEVDISR (and the second into
  58 -  DEVDISR2, if present -- this cell should be zero or absent if the
  59 -  hardware does not have DEVDISR2) upon a request for permanent device
  60 -  disabling.  This sleep controller does not support configuring devices
  61 -  to disable during system sleep (unless supported by another compatible
  62 -  match), or dynamically.
  63 +Clock nodes:
  64 +The clock nodes are to describe the masks in PM controller registers for each
  65 +soc clock.
  66 +- fsl,pmcdr-mask: For "fsl,mpc8548-pmc"-compatible devices, the mask will be
  67 +  ORed into PMCDR before suspend if the device using this clock is the wake-up
  68 +  source and need to be running during low power mode; clear the mask if
  69 +  otherwise.
  70 +
  71 +- fsl,sccr-mask: For "fsl,mpc8349-pmc"-compatible devices, the corresponding
  72 +  bit specified by the mask in SCCR will be saved and cleared on suspend, and
  73 +  restored on resume.
  74 +
  75 +- fsl,devdisr-mask: Contain one or two cells, depending on the availability of
  76 +  DEVDISR2 register.  For compatible devices, the mask will be ORed into DEVDISR
  77 +  or DEVDISR2 when the clock should be permenently disabled.
  78
  79  Example:
  80
  81 -       power@b00 {
  82 -               compatible = "fsl,mpc8313-pmc", "fsl,mpc8349-pmc";
  83 -               reg = <0xb00 0x100 0xa00 0x100>;
  84 -               interrupts = <80 8>;
  85 +       power@e0070 {
  86 +               compatible = "fsl,mpc8536-pmc", "fsl,mpc8548-pmc";
  87 +               reg = <0xe0070 0x20>;
  88 +
  89 +               etsec1_clk: soc-clk@24 {
  90 +                       fsl,pmcdr-mask = <0x00000080>;
  91 +               };
  92 +               etsec2_clk: soc-clk@25 {
  93 +                       fsl,pmcdr-mask = <0x00000040>;
  94 +               };
  95 +               etsec3_clk: soc-clk@26 {
  96 +                       fsl,pmcdr-mask = <0x00000020>;
  97 +               };
  98         };