target/linux/layerscape/patches-5.4/813-pm-0003-drivers-soc-fsl-add-EPU-FSM-configuration-for-deep-s.patch

   1 From 051f3793314e2fb3f1945f3e6fa6942a355ebb50 Mon Sep 17 00:00:00 2001
   2 From: Ran Wang <ran.wang_1@nxp.com>
   3 Date: Thu, 12 Apr 2018 14:35:40 +0800
   4 Subject: [PATCH] drivers/soc/fsl: add EPU FSM configuration for deep sleep
   5
   6 In the last stage of deep sleep, software will trigger a Finite
   7 State Machine (FSM) to control the hardware procedure, such a
   8 board isolation, killing PLLs, removing power, and so on.
   9
  10 When the system is waked up by an interrupt, the FSM controls
  11 the hardware to complete the early resume procedure.
  12
  13 This patch configure the EPU FSM preparing for deep sleep.
  14
  15 Signed-off-by: Hongbo Zhang <hongbo.zhang@freescale.com>
  16 Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com>
  17 Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
  18 ---
  19  drivers/soc/fsl/Kconfig     |   7 ++
  20  drivers/soc/fsl/Makefile    |   1 +
  21  drivers/soc/fsl/sleep_fsm.c | 279 ++++++++++++++++++++++++++++++++++++++++++++
  22  drivers/soc/fsl/sleep_fsm.h | 130 +++++++++++++++++++++
  23  4 files changed, 417 insertions(+)
  24  create mode 100644 drivers/soc/fsl/sleep_fsm.c
  25  create mode 100644 drivers/soc/fsl/sleep_fsm.h
  26
  27 --- a/drivers/soc/fsl/Kconfig
  28 +++ b/drivers/soc/fsl/Kconfig
  29 @@ -31,6 +31,13 @@ config FSL_MC_DPIO
  30           objects individually, but groups them under a service layer
  31           API.
  32
  33 +config FSL_SLEEP_FSM
  34 +       bool
  35 +       help
  36 +         This driver configures a hardware FSM (Finite State Machine) for deep sleep.
  37 +         The FSM is used to finish clean-ups at the last stage of system entering deep
  38 +         sleep, and also wakes up system when a wake up event happens.
  39 +
  40  config DPAA2_CONSOLE
  41         tristate "QorIQ DPAA2 console driver"
  42         depends on OF && (ARCH_LAYERSCAPE || COMPILE_TEST)
  43 --- a/drivers/soc/fsl/Makefile
  44 +++ b/drivers/soc/fsl/Makefile
  45 @@ -11,3 +11,4 @@ obj-$(CONFIG_FSL_GUTS)                        += guts.o
  46  obj-$(CONFIG_FSL_MC_DPIO)              += dpio/
  47  obj-$(CONFIG_DPAA2_CONSOLE)            += dpaa2-console.o
  48  obj-$(CONFIG_FSL_RCPM)                 += rcpm.o
  49 +obj-$(CONFIG_FSL_SLEEP_FSM)            += sleep_fsm.o
  50 --- /dev/null
  51 +++ b/drivers/soc/fsl/sleep_fsm.c
  52 @@ -0,0 +1,279 @@
  53 +/*
  54 + * deep sleep FSM (finite-state machine) configuration
  55 + *
  56 + * Copyright 2018 NXP
  57 + *
  58 + * Author: Hongbo Zhang <hongbo.zhang@freescale.com>
  59 + *         Chenhui Zhao <chenhui.zhao@freescale.com>
  60 + *
  61 + * Redistribution and use in source and binary forms, with or without
  62 + * modification, are permitted provided that the following conditions are met:
  63 + *     * Redistributions of source code must retain the above copyright
  64 + *      notice, this list of conditions and the following disclaimer.
  65 + *     * Redistributions in binary form must reproduce the above copyright
  66 + *      notice, this list of conditions and the following disclaimer in the
  67 + *      documentation and/or other materials provided with the distribution.
  68 + *     * Neither the name of the above-listed copyright holders nor the
  69 + *      names of any contributors may be used to endorse or promote products
  70 + *      derived from this software without specific prior written permission.
  71 + *
  72 + * ALTERNATIVELY, this software may be distributed under the terms of the
  73 + * GNU General Public License ("GPL") as published by the Free Software
  74 + * Foundation, either version 2 of that License or (at your option) any
  75 + * later version.
  76 + *
  77 + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  78 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  79 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  80 + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
  81 + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  82 + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  83 + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  84 + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  85 + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  86 + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  87 + * POSSIBILITY OF SUCH DAMAGE.
  88 + */
  89 +
  90 +#include <linux/kernel.h>
  91 +#include <linux/io.h>
  92 +#include <linux/types.h>
  93 +
  94 +#include "sleep_fsm.h"
  95 +/*
  96 + * These values are from chip's reference manual. For example,
  97 + * the values for T1040 can be found in "8.4.3.8 Programming
  98 + * supporting deep sleep mode" of Chapter 8 "Run Control and
  99 + * Power Management (RCPM)".
 100 + * The default value can be applied to T104x, LS1021.
 101 + */
 102 +struct fsm_reg_vals epu_default_val[] = {
 103 +       /* EPGCR (Event Processor Global Control Register) */
 104 +       {EPGCR, 0},
 105 +       /* EPECR (Event Processor Event Control Registers) */
 106 +       {EPECR0 + EPECR_STRIDE * 0, 0},
 107 +       {EPECR0 + EPECR_STRIDE * 1, 0},
 108 +       {EPECR0 + EPECR_STRIDE * 2, 0xF0004004},
 109 +       {EPECR0 + EPECR_STRIDE * 3, 0x80000084},
 110 +       {EPECR0 + EPECR_STRIDE * 4, 0x20000084},
 111 +       {EPECR0 + EPECR_STRIDE * 5, 0x08000004},
 112 +       {EPECR0 + EPECR_STRIDE * 6, 0x80000084},
 113 +       {EPECR0 + EPECR_STRIDE * 7, 0x80000084},
 114 +       {EPECR0 + EPECR_STRIDE * 8, 0x60000084},
 115 +       {EPECR0 + EPECR_STRIDE * 9, 0x08000084},
 116 +       {EPECR0 + EPECR_STRIDE * 10, 0x42000084},
 117 +       {EPECR0 + EPECR_STRIDE * 11, 0x90000084},
 118 +       {EPECR0 + EPECR_STRIDE * 12, 0x80000084},
 119 +       {EPECR0 + EPECR_STRIDE * 13, 0x08000084},
 120 +       {EPECR0 + EPECR_STRIDE * 14, 0x02000084},
 121 +       {EPECR0 + EPECR_STRIDE * 15, 0x00000004},
 122 +       /*
 123 +        * EPEVTCR (Event Processor EVT Pin Control Registers)
 124 +        * SCU8 triger EVT2, and SCU11 triger EVT9
 125 +        */
 126 +       {EPEVTCR0 + EPEVTCR_STRIDE * 0, 0},
 127 +       {EPEVTCR0 + EPEVTCR_STRIDE * 1, 0},
 128 +       {EPEVTCR0 + EPEVTCR_STRIDE * 2, 0x80000001},
 129 +       {EPEVTCR0 + EPEVTCR_STRIDE * 3, 0},
 130 +       {EPEVTCR0 + EPEVTCR_STRIDE * 4, 0},
 131 +       {EPEVTCR0 + EPEVTCR_STRIDE * 5, 0},
 132 +       {EPEVTCR0 + EPEVTCR_STRIDE * 6, 0},
 133 +       {EPEVTCR0 + EPEVTCR_STRIDE * 7, 0},
 134 +       {EPEVTCR0 + EPEVTCR_STRIDE * 8, 0},
 135 +       {EPEVTCR0 + EPEVTCR_STRIDE * 9, 0xB0000001},
 136 +       /* EPCMPR (Event Processor Counter Compare Registers) */
 137 +       {EPCMPR0 + EPCMPR_STRIDE * 0, 0},
 138 +       {EPCMPR0 + EPCMPR_STRIDE * 1, 0},
 139 +       {EPCMPR0 + EPCMPR_STRIDE * 2, 0x000000FF},
 140 +       {EPCMPR0 + EPCMPR_STRIDE * 3, 0},
 141 +       {EPCMPR0 + EPCMPR_STRIDE * 4, 0x000000FF},
 142 +       {EPCMPR0 + EPCMPR_STRIDE * 5, 0x00000020},
 143 +       {EPCMPR0 + EPCMPR_STRIDE * 6, 0},
 144 +       {EPCMPR0 + EPCMPR_STRIDE * 7, 0},
 145 +       {EPCMPR0 + EPCMPR_STRIDE * 8, 0x000000FF},
 146 +       {EPCMPR0 + EPCMPR_STRIDE * 9, 0x000000FF},
 147 +       {EPCMPR0 + EPCMPR_STRIDE * 10, 0x000000FF},
 148 +       {EPCMPR0 + EPCMPR_STRIDE * 11, 0x000000FF},
 149 +       {EPCMPR0 + EPCMPR_STRIDE * 12, 0x000000FF},
 150 +       {EPCMPR0 + EPCMPR_STRIDE * 13, 0},
 151 +       {EPCMPR0 + EPCMPR_STRIDE * 14, 0x000000FF},
 152 +       {EPCMPR0 + EPCMPR_STRIDE * 15, 0x000000FF},
 153 +       /* EPCCR (Event Processor Counter Control Registers) */
 154 +       {EPCCR0 + EPCCR_STRIDE * 0, 0},
 155 +       {EPCCR0 + EPCCR_STRIDE * 1, 0},
 156 +       {EPCCR0 + EPCCR_STRIDE * 2, 0x92840000},
 157 +       {EPCCR0 + EPCCR_STRIDE * 3, 0},
 158 +       {EPCCR0 + EPCCR_STRIDE * 4, 0x92840000},
 159 +       {EPCCR0 + EPCCR_STRIDE * 5, 0x92840000},
 160 +       {EPCCR0 + EPCCR_STRIDE * 6, 0},
 161 +       {EPCCR0 + EPCCR_STRIDE * 7, 0},
 162 +       {EPCCR0 + EPCCR_STRIDE * 8, 0x92840000},
 163 +       {EPCCR0 + EPCCR_STRIDE * 9, 0x92840000},
 164 +       {EPCCR0 + EPCCR_STRIDE * 10, 0x92840000},
 165 +       {EPCCR0 + EPCCR_STRIDE * 11, 0x92840000},
 166 +       {EPCCR0 + EPCCR_STRIDE * 12, 0x92840000},
 167 +       {EPCCR0 + EPCCR_STRIDE * 13, 0},
 168 +       {EPCCR0 + EPCCR_STRIDE * 14, 0x92840000},
 169 +       {EPCCR0 + EPCCR_STRIDE * 15, 0x92840000},
 170 +       /* EPSMCR (Event Processor SCU Mux Control Registers) */
 171 +       {EPSMCR0 + EPSMCR_STRIDE * 0, 0},
 172 +       {EPSMCR0 + EPSMCR_STRIDE * 1, 0},
 173 +       {EPSMCR0 + EPSMCR_STRIDE * 2, 0x6C700000},
 174 +       {EPSMCR0 + EPSMCR_STRIDE * 3, 0x2F000000},
 175 +       {EPSMCR0 + EPSMCR_STRIDE * 4, 0x002F0000},
 176 +       {EPSMCR0 + EPSMCR_STRIDE * 5, 0x00002E00},
 177 +       {EPSMCR0 + EPSMCR_STRIDE * 6, 0x7C000000},
 178 +       {EPSMCR0 + EPSMCR_STRIDE * 7, 0x30000000},
 179 +       {EPSMCR0 + EPSMCR_STRIDE * 8, 0x64300000},
 180 +       {EPSMCR0 + EPSMCR_STRIDE * 9, 0x00003000},
 181 +       {EPSMCR0 + EPSMCR_STRIDE * 10, 0x65000030},
 182 +       {EPSMCR0 + EPSMCR_STRIDE * 11, 0x31740000},
 183 +       {EPSMCR0 + EPSMCR_STRIDE * 12, 0x7F000000},
 184 +       {EPSMCR0 + EPSMCR_STRIDE * 13, 0x00003100},
 185 +       {EPSMCR0 + EPSMCR_STRIDE * 14, 0x00000031},
 186 +       {EPSMCR0 + EPSMCR_STRIDE * 15, 0x76000000},
 187 +       /* EPACR (Event Processor Action Control Registers) */
 188 +       {EPACR0 + EPACR_STRIDE * 0, 0},
 189 +       {EPACR0 + EPACR_STRIDE * 1, 0},
 190 +       {EPACR0 + EPACR_STRIDE * 2, 0},
 191 +       {EPACR0 + EPACR_STRIDE * 3, 0x00000080},
 192 +       {EPACR0 + EPACR_STRIDE * 4, 0},
 193 +       {EPACR0 + EPACR_STRIDE * 5, 0x00000040},
 194 +       {EPACR0 + EPACR_STRIDE * 6, 0},
 195 +       {EPACR0 + EPACR_STRIDE * 7, 0},
 196 +       {EPACR0 + EPACR_STRIDE * 8, 0},
 197 +       {EPACR0 + EPACR_STRIDE * 9, 0x0000001C},
 198 +       {EPACR0 + EPACR_STRIDE * 10, 0x00000020},
 199 +       {EPACR0 + EPACR_STRIDE * 11, 0},
 200 +       {EPACR0 + EPACR_STRIDE * 12, 0x00000003},
 201 +       {EPACR0 + EPACR_STRIDE * 13, 0x06000000},
 202 +       {EPACR0 + EPACR_STRIDE * 14, 0x04000000},
 203 +       {EPACR0 + EPACR_STRIDE * 15, 0x02000000},
 204 +       /* EPIMCR (Event Processor Input Mux Control Registers) */
 205 +       {EPIMCR0 + EPIMCR_STRIDE * 0, 0},
 206 +       {EPIMCR0 + EPIMCR_STRIDE * 1, 0},
 207 +       {EPIMCR0 + EPIMCR_STRIDE * 2, 0},
 208 +       {EPIMCR0 + EPIMCR_STRIDE * 3, 0},
 209 +       {EPIMCR0 + EPIMCR_STRIDE * 4, 0x44000000},
 210 +       {EPIMCR0 + EPIMCR_STRIDE * 5, 0x40000000},
 211 +       {EPIMCR0 + EPIMCR_STRIDE * 6, 0},
 212 +       {EPIMCR0 + EPIMCR_STRIDE * 7, 0},
 213 +       {EPIMCR0 + EPIMCR_STRIDE * 8, 0},
 214 +       {EPIMCR0 + EPIMCR_STRIDE * 9, 0},
 215 +       {EPIMCR0 + EPIMCR_STRIDE * 10, 0},
 216 +       {EPIMCR0 + EPIMCR_STRIDE * 11, 0},
 217 +       {EPIMCR0 + EPIMCR_STRIDE * 12, 0x44000000},
 218 +       {EPIMCR0 + EPIMCR_STRIDE * 13, 0},
 219 +       {EPIMCR0 + EPIMCR_STRIDE * 14, 0},
 220 +       {EPIMCR0 + EPIMCR_STRIDE * 15, 0},
 221 +       {EPIMCR0 + EPIMCR_STRIDE * 16, 0x6A000000},
 222 +       {EPIMCR0 + EPIMCR_STRIDE * 17, 0},
 223 +       {EPIMCR0 + EPIMCR_STRIDE * 18, 0},
 224 +       {EPIMCR0 + EPIMCR_STRIDE * 19, 0},
 225 +       {EPIMCR0 + EPIMCR_STRIDE * 20, 0x48000000},
 226 +       {EPIMCR0 + EPIMCR_STRIDE * 21, 0},
 227 +       {EPIMCR0 + EPIMCR_STRIDE * 22, 0x6C000000},
 228 +       {EPIMCR0 + EPIMCR_STRIDE * 23, 0},
 229 +       {EPIMCR0 + EPIMCR_STRIDE * 24, 0},
 230 +       {EPIMCR0 + EPIMCR_STRIDE * 25, 0},
 231 +       {EPIMCR0 + EPIMCR_STRIDE * 26, 0},
 232 +       {EPIMCR0 + EPIMCR_STRIDE * 27, 0},
 233 +       {EPIMCR0 + EPIMCR_STRIDE * 28, 0x76000000},
 234 +       {EPIMCR0 + EPIMCR_STRIDE * 29, 0},
 235 +       {EPIMCR0 + EPIMCR_STRIDE * 30, 0},
 236 +       {EPIMCR0 + EPIMCR_STRIDE * 31, 0x76000000},
 237 +       /* EPXTRIGCR (Event Processor Crosstrigger Control Register) */
 238 +       {EPXTRIGCR, 0x0000FFDF},
 239 +       /* end */
 240 +       {FSM_END_FLAG, 0},
 241 +};
 242 +
 243 +struct fsm_reg_vals npc_default_val[] = {
 244 +       /* NPC triggered Memory-Mapped Access Registers */
 245 +       {NCR, 0x80000000},
 246 +       {MCCR1, 0},
 247 +       {MCSR1, 0},
 248 +       {MMAR1LO, 0},
 249 +       {MMAR1HI, 0},
 250 +       {MMDR1, 0},
 251 +       {MCSR2, 0},
 252 +       {MMAR2LO, 0},
 253 +       {MMAR2HI, 0},
 254 +       {MMDR2, 0},
 255 +       {MCSR3, 0x80000000},
 256 +       {MMAR3LO, 0x000E2130},
 257 +       {MMAR3HI, 0x00030000},
 258 +       {MMDR3, 0x00020000},
 259 +       /* end */
 260 +       {FSM_END_FLAG, 0},
 261 +};
 262 +
 263 +/**
 264 + * fsl_fsm_setup - Configure EPU's FSM registers
 265 + * @base: the base address of registers
 266 + * @val: Pointer to address-value pairs for FSM registers
 267 + */
 268 +void fsl_fsm_setup(void __iomem *base, struct fsm_reg_vals *val)
 269 +{
 270 +       struct fsm_reg_vals *data = val;
 271 +
 272 +       WARN_ON(!base || !data);
 273 +       while (data->offset != FSM_END_FLAG) {
 274 +               iowrite32be(data->value, base + data->offset);
 275 +               data++;
 276 +       }
 277 +}
 278 +
 279 +void fsl_epu_setup_default(void __iomem *epu_base)
 280 +{
 281 +       fsl_fsm_setup(epu_base, epu_default_val);
 282 +}
 283 +
 284 +void fsl_npc_setup_default(void __iomem *npc_base)
 285 +{
 286 +       fsl_fsm_setup(npc_base, npc_default_val);
 287 +}
 288 +
 289 +void fsl_epu_clean_default(void __iomem *epu_base)
 290 +{
 291 +       u32 offset;
 292 +
 293 +       /* follow the exact sequence to clear the registers */
 294 +       /* Clear EPACRn */
 295 +       for (offset = EPACR0; offset <= EPACR15; offset += EPACR_STRIDE)
 296 +               iowrite32be(0, epu_base + offset);
 297 +
 298 +       /* Clear EPEVTCRn */
 299 +       for (offset = EPEVTCR0; offset <= EPEVTCR9; offset += EPEVTCR_STRIDE)
 300 +               iowrite32be(0, epu_base + offset);
 301 +
 302 +       /* Clear EPGCR */
 303 +       iowrite32be(0, epu_base + EPGCR);
 304 +
 305 +       /* Clear EPSMCRn */
 306 +       for (offset = EPSMCR0; offset <= EPSMCR15; offset += EPSMCR_STRIDE)
 307 +               iowrite32be(0, epu_base + offset);
 308 +
 309 +       /* Clear EPCCRn */
 310 +       for (offset = EPCCR0; offset <= EPCCR31; offset += EPCCR_STRIDE)
 311 +               iowrite32be(0, epu_base + offset);
 312 +
 313 +       /* Clear EPCMPRn */
 314 +       for (offset = EPCMPR0; offset <= EPCMPR31; offset += EPCMPR_STRIDE)
 315 +               iowrite32be(0, epu_base + offset);
 316 +
 317 +       /* Clear EPCTRn */
 318 +       for (offset = EPCTR0; offset <= EPCTR31; offset += EPCTR_STRIDE)
 319 +               iowrite32be(0, epu_base + offset);
 320 +
 321 +       /* Clear EPIMCRn */
 322 +       for (offset = EPIMCR0; offset <= EPIMCR31; offset += EPIMCR_STRIDE)
 323 +               iowrite32be(0, epu_base + offset);
 324 +
 325 +       /* Clear EPXTRIGCRn */
 326 +       iowrite32be(0, epu_base + EPXTRIGCR);
 327 +
 328 +       /* Clear EPECRn */
 329 +       for (offset = EPECR0; offset <= EPECR15; offset += EPECR_STRIDE)
 330 +               iowrite32be(0, epu_base + offset);
 331 +}
 332 --- /dev/null
 333 +++ b/drivers/soc/fsl/sleep_fsm.h
 334 @@ -0,0 +1,130 @@
 335 +/*
 336 + * deep sleep FSM (finite-state machine) configuration
 337 + *
 338 + * Copyright 2018 NXP
 339 + *
 340 + * Redistribution and use in source and binary forms, with or without
 341 + * modification, are permitted provided that the following conditions are met:
 342 + *     * Redistributions of source code must retain the above copyright
 343 + *      notice, this list of conditions and the following disclaimer.
 344 + *     * Redistributions in binary form must reproduce the above copyright
 345 + *      notice, this list of conditions and the following disclaimer in the
 346 + *      documentation and/or other materials provided with the distribution.
 347 + *     * Neither the name of the above-listed copyright holders nor the
 348 + *      names of any contributors may be used to endorse or promote products
 349 + *      derived from this software without specific prior written permission.
 350 + *
 351 + *
 352 + * ALTERNATIVELY, this software may be distributed under the terms of the
 353 + * GNU General Public License ("GPL") as published by the Free Software
 354 + * Foundation, either version 2 of that License or (at your option) any
 355 + * later version.
 356 + *
 357 + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 358 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 359 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 360 + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
 361 + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 362 + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 363 + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 364 + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 365 + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 366 + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 367 + * POSSIBILITY OF SUCH DAMAGE.
 368 + */
 369 +
 370 +#ifndef _FSL_SLEEP_FSM_H
 371 +#define _FSL_SLEEP_FSM_H
 372 +
 373 +#define FSL_STRIDE_4B  4
 374 +#define FSL_STRIDE_8B  8
 375 +
 376 +/* End flag */
 377 +#define FSM_END_FLAG           0xFFFFFFFFUL
 378 +
 379 +/* Block offsets */
 380 +#define RCPM_BLOCK_OFFSET      0x00022000
 381 +#define EPU_BLOCK_OFFSET       0x00000000
 382 +#define NPC_BLOCK_OFFSET       0x00001000
 383 +
 384 +/* EPGCR (Event Processor Global Control Register) */
 385 +#define EPGCR          0x000
 386 +
 387 +/* EPEVTCR0-9 (Event Processor EVT Pin Control Registers) */
 388 +#define EPEVTCR0       0x050
 389 +#define EPEVTCR9       0x074
 390 +#define EPEVTCR_STRIDE FSL_STRIDE_4B
 391 +
 392 +/* EPXTRIGCR (Event Processor Crosstrigger Control Register) */
 393 +#define EPXTRIGCR      0x090
 394 +
 395 +/* EPIMCR0-31 (Event Processor Input Mux Control Registers) */
 396 +#define EPIMCR0                0x100
 397 +#define EPIMCR31       0x17C
 398 +#define EPIMCR_STRIDE  FSL_STRIDE_4B
 399 +
 400 +/* EPSMCR0-15 (Event Processor SCU Mux Control Registers) */
 401 +#define EPSMCR0                0x200
 402 +#define EPSMCR15       0x278
 403 +#define EPSMCR_STRIDE  FSL_STRIDE_8B
 404 +
 405 +/* EPECR0-15 (Event Processor Event Control Registers) */
 406 +#define EPECR0         0x300
 407 +#define EPECR15                0x33C
 408 +#define EPECR_STRIDE   FSL_STRIDE_4B
 409 +
 410 +/* EPACR0-15 (Event Processor Action Control Registers) */
 411 +#define EPACR0         0x400
 412 +#define EPACR15                0x43C
 413 +#define EPACR_STRIDE   FSL_STRIDE_4B
 414 +
 415 +/* EPCCRi0-15 (Event Processor Counter Control Registers) */
 416 +#define EPCCR0         0x800
 417 +#define EPCCR15                0x83C
 418 +#define EPCCR31                0x87C
 419 +#define EPCCR_STRIDE   FSL_STRIDE_4B
 420 +
 421 +/* EPCMPR0-15 (Event Processor Counter Compare Registers) */
 422 +#define EPCMPR0                0x900
 423 +#define EPCMPR15       0x93C
 424 +#define EPCMPR31       0x97C
 425 +#define EPCMPR_STRIDE  FSL_STRIDE_4B
 426 +
 427 +/* EPCTR0-31 (Event Processor Counter Register) */
 428 +#define EPCTR0         0xA00
 429 +#define EPCTR31                0xA7C
 430 +#define EPCTR_STRIDE   FSL_STRIDE_4B
 431 +
 432 +/* NPC triggered Memory-Mapped Access Registers */
 433 +#define NCR            0x000
 434 +#define MCCR1          0x0CC
 435 +#define MCSR1          0x0D0
 436 +#define MMAR1LO                0x0D4
 437 +#define MMAR1HI                0x0D8
 438 +#define MMDR1          0x0DC
 439 +#define MCSR2          0x0E0
 440 +#define MMAR2LO                0x0E4
 441 +#define MMAR2HI                0x0E8
 442 +#define MMDR2          0x0EC
 443 +#define MCSR3          0x0F0
 444 +#define MMAR3LO                0x0F4
 445 +#define MMAR3HI                0x0F8
 446 +#define MMDR3          0x0FC
 447 +
 448 +/* RCPM Core State Action Control Register 0 */
 449 +#define CSTTACR0       0xB00
 450 +
 451 +/* RCPM Core Group 1 Configuration Register 0 */
 452 +#define CG1CR0         0x31C
 453 +
 454 +struct fsm_reg_vals {
 455 +       u32 offset;
 456 +       u32 value;
 457 +};
 458 +
 459 +void fsl_fsm_setup(void __iomem *base, struct fsm_reg_vals *val);
 460 +void fsl_epu_setup_default(void __iomem *epu_base);
 461 +void fsl_npc_setup_default(void __iomem *npc_base);
 462 +void fsl_epu_clean_default(void __iomem *epu_base);
 463 +
 464 +#endif /* _FSL_SLEEP_FSM_H */