target/linux/layerscape/patches-5.4/818-thermal-0003-thermal-qoriq-add-thermal-monitor-unit-version-2-sup.patch

   1 From 031573a8a1e73b0ac548812c10c3e426c2b4ce61 Mon Sep 17 00:00:00 2001
   2 From: Yuantian Tang <andy.tang@nxp.com>
   3 Date: Tue, 15 Oct 2019 20:08:58 +0800
   4 Subject: [PATCH] thermal: qoriq: add thermal monitor unit version 2 support
   5
   6 Thermal Monitor Unit v2 is introduced on new Layscape SoC.
   7 Compared to v1, TMUv2 has a little different register layout
   8 and digital output is fairly linear.
   9
  10 Signed-off-by: Yuantian Tang <andy.tang@nxp.com>
  11 Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
  12 ---
  13  drivers/thermal/qoriq_thermal.c | 118 ++++++++++++++++++++++++++++++++--------
  14  1 file changed, 96 insertions(+), 22 deletions(-)
  15
  16 --- a/drivers/thermal/qoriq_thermal.c
  17 +++ b/drivers/thermal/qoriq_thermal.c
  18 @@ -16,6 +16,15 @@
  19
  20  #define SITES_MAX      16
  21  #define TMU_TEMP_PASSIVE_COOL_DELTA    10000
  22 +#define TMR_DISABLE            0x0
  23 +#define TMR_ME                 0x80000000
  24 +#define TMR_ALPF               0x0c000000
  25 +#define TMR_ALPF_V2            0x03000000
  26 +#define TMTMIR_DEFAULT 0x0000000f
  27 +#define TIER_DISABLE   0x0
  28 +#define TEUMR0_V2              0x51009c00
  29 +#define TMU_VER1               0x1
  30 +#define TMU_VER2               0x2
  31
  32  /*
  33   * QorIQ TMU Registers
  34 @@ -26,17 +35,12 @@ struct qoriq_tmu_site_regs {
  35         u8 res0[0x8];
  36  };
  37
  38 -struct qoriq_tmu_regs {
  39 +struct qoriq_tmu_regs_v1 {
  40         u32 tmr;                /* Mode Register */
  41 -#define TMR_DISABLE    0x0
  42 -#define TMR_ME         0x80000000
  43 -#define TMR_ALPF       0x0c000000
  44         u32 tsr;                /* Status Register */
  45         u32 tmtmir;             /* Temperature measurement interval Register */
  46 -#define TMTMIR_DEFAULT 0x0000000f
  47         u8 res0[0x14];
  48         u32 tier;               /* Interrupt Enable Register */
  49 -#define TIER_DISABLE   0x0
  50         u32 tidr;               /* Interrupt Detect Register */
  51         u32 tiscr;              /* Interrupt Site Capture Register */
  52         u32 ticscr;             /* Interrupt Critical Site Capture Register */
  53 @@ -56,12 +60,52 @@ struct qoriq_tmu_regs {
  54         u32 ipbrr0;             /* IP Block Revision Register 0 */
  55         u32 ipbrr1;             /* IP Block Revision Register 1 */
  56         u8 res6[0x310];
  57 -       u32 ttr0cr;             /* Temperature Range 0 Control Register */
  58 -       u32 ttr1cr;             /* Temperature Range 1 Control Register */
  59 -       u32 ttr2cr;             /* Temperature Range 2 Control Register */
  60 -       u32 ttr3cr;             /* Temperature Range 3 Control Register */
  61 +       u32 ttrcr[4];           /* Temperature Range Control Register */
  62  };
  63
  64 +struct qoriq_tmu_regs_v2 {
  65 +       u32 tmr;                /* Mode Register */
  66 +       u32 tsr;                /* Status Register */
  67 +       u32 tmsr;               /* monitor site register */
  68 +       u32 tmtmir;             /* Temperature measurement interval Register */
  69 +       u8 res0[0x10];
  70 +       u32 tier;               /* Interrupt Enable Register */
  71 +       u32 tidr;               /* Interrupt Detect Register */
  72 +       u8 res1[0x8];
  73 +       u32 tiiscr;             /* interrupt immediate site capture register */
  74 +       u32 tiascr;             /* interrupt average site capture register */
  75 +       u32 ticscr;             /* Interrupt Critical Site Capture Register */
  76 +       u32 res2;
  77 +       u32 tmhtcr;             /* monitor high temperature capture register */
  78 +       u32 tmltcr;             /* monitor low temperature capture register */
  79 +       u32 tmrtrcr;    /* monitor rising temperature rate capture register */
  80 +       u32 tmftrcr;    /* monitor falling temperature rate capture register */
  81 +       u32 tmhtitr;    /* High Temperature Immediate Threshold */
  82 +       u32 tmhtatr;    /* High Temperature Average Threshold */
  83 +       u32 tmhtactr;   /* High Temperature Average Crit Threshold */
  84 +       u32 res3;
  85 +       u32 tmltitr;    /* monitor low temperature immediate threshold */
  86 +       u32 tmltatr;    /* monitor low temperature average threshold register */
  87 +       u32 tmltactr;   /* monitor low temperature average critical threshold */
  88 +       u32 res4;
  89 +       u32 tmrtrctr;   /* monitor rising temperature rate critical threshold */
  90 +       u32 tmftrctr;   /* monitor falling temperature rate critical threshold*/
  91 +       u8 res5[0x8];
  92 +       u32 ttcfgr;     /* Temperature Configuration Register */
  93 +       u32 tscfgr;     /* Sensor Configuration Register */
  94 +       u8 res6[0x78];
  95 +       struct qoriq_tmu_site_regs site[SITES_MAX];
  96 +       u8 res7[0x9f8];
  97 +       u32 ipbrr0;             /* IP Block Revision Register 0 */
  98 +       u32 ipbrr1;             /* IP Block Revision Register 1 */
  99 +       u8 res8[0x300];
 100 +       u32 teumr0;
 101 +       u32 teumr1;
 102 +       u32 teumr2;
 103 +       u32 res9;
 104 +       u32 ttrcr[4];   /* Temperature Range Control Register */
 105 + };
 106 +
 107  struct qoriq_tmu_data;
 108
 109  /*
 110 @@ -77,7 +121,9 @@ struct qoriq_sensor {
 111  };
 112
 113  struct qoriq_tmu_data {
 114 -       struct qoriq_tmu_regs __iomem *regs;
 115 +       int ver;
 116 +       struct qoriq_tmu_regs_v1 __iomem *regs;
 117 +       struct qoriq_tmu_regs_v2 __iomem *regs_v2;
 118         struct clk *clk;
 119         bool little_endian;
 120         struct qoriq_sensor     *sensor[SITES_MAX];
 121 @@ -210,12 +256,23 @@ static int qoriq_tmu_register_tmu_zone(s
 122                         qdata->sensor[id]->temp_critical = trip[1].temperature;
 123                 }
 124
 125 -               sites |= 0x1 << (15 - id);
 126 +               if (qdata->ver == TMU_VER1)
 127 +                       sites |= 0x1 << (15 - id);
 128 +               else
 129 +                       sites |= 0x1 << id;
 130         }
 131
 132         /* Enable monitoring */
 133 -       if (sites != 0)
 134 -               tmu_write(qdata, sites | TMR_ME | TMR_ALPF, &qdata->regs->tmr);
 135 +       if (sites != 0) {
 136 +               if (qdata->ver == TMU_VER1) {
 137 +                       tmu_write(qdata, sites | TMR_ME | TMR_ALPF,
 138 +                                       &qdata->regs->tmr);
 139 +               } else {
 140 +                       tmu_write(qdata, sites, &qdata->regs_v2->tmsr);
 141 +                       tmu_write(qdata, TMR_ME | TMR_ALPF_V2,
 142 +                                       &qdata->regs_v2->tmr);
 143 +               }
 144 +       }
 145
 146         return 0;
 147  }
 148 @@ -228,16 +285,21 @@ static int qoriq_tmu_calibration(struct
 149         struct device_node *np = pdev->dev.of_node;
 150         struct qoriq_tmu_data *data = platform_get_drvdata(pdev);
 151
 152 -       if (of_property_read_u32_array(np, "fsl,tmu-range", range, 4)) {
 153 -               dev_err(&pdev->dev, "missing calibration range.\n");
 154 -               return -ENODEV;
 155 +       len = of_property_count_u32_elems(np, "fsl,tmu-range");
 156 +       if (len < 0 || len > 4) {
 157 +               dev_err(&pdev->dev, "invalid range data.\n");
 158 +               return len;
 159 +       }
 160 +
 161 +       val = of_property_read_u32_array(np, "fsl,tmu-range", range, len);
 162 +       if (val != 0) {
 163 +               dev_err(&pdev->dev, "failed to read range data.\n");
 164 +               return val;
 165         }
 166
 167         /* Init temperature range registers */
 168 -       tmu_write(data, range[0], &data->regs->ttr0cr);
 169 -       tmu_write(data, range[1], &data->regs->ttr1cr);
 170 -       tmu_write(data, range[2], &data->regs->ttr2cr);
 171 -       tmu_write(data, range[3], &data->regs->ttr3cr);
 172 +       for (i = 0; i < len; i++)
 173 +               tmu_write(data, range[i], &data->regs->ttrcr[i]);
 174
 175         calibration = of_get_property(np, "fsl,tmu-calibration", &len);
 176         if (calibration == NULL || len % 8) {
 177 @@ -261,7 +323,12 @@ static void qoriq_tmu_init_device(struct
 178         tmu_write(data, TIER_DISABLE, &data->regs->tier);
 179
 180         /* Set update_interval */
 181 -       tmu_write(data, TMTMIR_DEFAULT, &data->regs->tmtmir);
 182 +       if (data->ver == TMU_VER1) {
 183 +               tmu_write(data, TMTMIR_DEFAULT, &data->regs->tmtmir);
 184 +       } else {
 185 +               tmu_write(data, TMTMIR_DEFAULT, &data->regs_v2->tmtmir);
 186 +               tmu_write(data, TEUMR0_V2, &data->regs_v2->teumr0);
 187 +       }
 188
 189         /* Disable monitoring */
 190         tmu_write(data, TMR_DISABLE, &data->regs->tmr);
 191 @@ -270,6 +337,7 @@ static void qoriq_tmu_init_device(struct
 192  static int qoriq_tmu_probe(struct platform_device *pdev)
 193  {
 194         int ret;
 195 +       u32 ver;
 196         struct qoriq_tmu_data *data;
 197         struct device_node *np = pdev->dev.of_node;
 198
 199 @@ -298,6 +366,12 @@ static int qoriq_tmu_probe(struct platfo
 200                 return ret;
 201         }
 202
 203 +       /* version register offset at: 0xbf8 on both v1 and v2 */
 204 +       ver = tmu_read(data, &data->regs->ipbrr0);
 205 +       data->ver = (ver >> 8) & 0xff;
 206 +       if (data->ver == TMU_VER2)
 207 +               data->regs_v2 = (void __iomem *)data->regs;
 208 +
 209         qoriq_tmu_init_device(data);    /* TMU initialization */
 210
 211         ret = qoriq_tmu_calibration(pdev);      /* TMU calibration */