target/linux/mediatek/files-4.19/arch/arm64/boot/dts/mediatek/mt7622-lynx-rfb1.dts

   1 /*
   2  * Copyright (c) 2017 MediaTek Inc.
   3  * Author: Ming Huang <ming.huang@mediatek.com>
   4  *         Sean Wang <sean.wang@mediatek.com>
   5  *
   6  * SPDX-License-Identifier: (GPL-2.0 OR MIT)
   7  */
   8
   9 /dts-v1/;
  10 #include <dt-bindings/input/input.h>
  11 #include <dt-bindings/gpio/gpio.h>
  12
  13 #include "mt7622.dtsi"
  14 #include "mt6380.dtsi"
  15
  16 / {
  17         model = "MediaTek MT7622 RFB1 board";
  18         compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622";
  19
  20         aliases {
  21                 serial0 = &uart0;
  22         };
  23
  24         chosen {
  25                 stdout-path = "serial0:115200n8";
  26                 bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512";
  27         };
  28
  29         cpus {
  30                 cpu@0 {
  31                         proc-supply = <&mt6380_vcpu_reg>;
  32                         sram-supply = <&mt6380_vm_reg>;
  33                 };
  34
  35                 cpu@1 {
  36                         proc-supply = <&mt6380_vcpu_reg>;
  37                         sram-supply = <&mt6380_vm_reg>;
  38                 };
  39         };
  40
  41         gpio-keys {
  42                 compatible = "gpio-keys";
  43                 poll-interval = <100>;
  44
  45                 factory {
  46                         label = "factory";
  47                         linux,code = <BTN_0>;
  48                         gpios = <&pio 0 0>;
  49                 };
  50
  51                 wps {
  52                         label = "wps";
  53                         linux,code = <KEY_WPS_BUTTON>;
  54                         gpios = <&pio 102 0>;
  55                 };
  56         };
  57
  58         gsw: gsw@0 {
  59                 compatible = "mediatek,mt753x";
  60                 mediatek,ethsys = <&ethsys>;
  61                 #address-cells = <1>;
  62                 #size-cells = <0>;
  63         };
  64
  65         memory {
  66                 reg = <0 0x40000000 0 0x3F000000>;
  67         };
  68
  69         reg_1p8v: regulator-1p8v {
  70                 compatible = "regulator-fixed";
  71                 regulator-name = "fixed-1.8V";
  72                 regulator-min-microvolt = <1800000>;
  73                 regulator-max-microvolt = <1800000>;
  74                 regulator-always-on;
  75         };
  76
  77         reg_3p3v: regulator-3p3v {
  78                 compatible = "regulator-fixed";
  79                 regulator-name = "fixed-3.3V";
  80                 regulator-min-microvolt = <3300000>;
  81                 regulator-max-microvolt = <3300000>;
  82                 regulator-boot-on;
  83                 regulator-always-on;
  84         };
  85
  86         reg_5v: regulator-5v {
  87                 compatible = "regulator-fixed";
  88                 regulator-name = "fixed-5V";
  89                 regulator-min-microvolt = <5000000>;
  90                 regulator-max-microvolt = <5000000>;
  91                 regulator-boot-on;
  92                 regulator-always-on;
  93         };
  94 };
  95
  96 &pcie {
  97         pinctrl-names = "default", "pcie1_pins";
  98         pinctrl-0 = <&pcie0_pins>;
  99         pinctrl-1 = <&pcie1_pins>;
 100         status = "okay";
 101
 102         pcie@0,0 {
 103                 status = "okay";
 104         };
 105
 106         pcie@1,0 {
 107                 status = "okay";
 108         };
 109
 110 };
 111
 112 &pio {
 113         /* eMMC is shared pin with parallel NAND */
 114         emmc_pins_default: emmc-pins-default {
 115                 mux {
 116                         function = "emmc", "emmc_rst";
 117                         groups = "emmc";
 118                 };
 119
 120                 /* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7",
 121                  * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4,
 122                  * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively
 123                  */
 124                 conf-cmd-dat {
 125                         pins = "NDL0", "NDL1", "NDL2",
 126                                "NDL3", "NDL4", "NDL5",
 127                                "NDL6", "NDL7", "NRB";
 128                         input-enable;
 129                         bias-pull-up;
 130                 };
 131
 132                 conf-clk {
 133                         pins = "NCLE";
 134                         bias-pull-down;
 135                 };
 136         };
 137
 138         emmc_pins_uhs: emmc-pins-uhs {
 139                 mux {
 140                         function = "emmc";
 141                         groups = "emmc";
 142                 };
 143
 144                 conf-cmd-dat {
 145                         pins = "NDL0", "NDL1", "NDL2",
 146                                "NDL3", "NDL4", "NDL5",
 147                                "NDL6", "NDL7", "NRB";
 148                         input-enable;
 149                         drive-strength = <4>;
 150                         bias-pull-up;
 151                 };
 152
 153                 conf-clk {
 154                         pins = "NCLE";
 155                         drive-strength = <4>;
 156                         bias-pull-down;
 157                 };
 158         };
 159
 160         eth_pins: eth-pins {
 161                 mux {
 162                         function = "eth";
 163                         groups = "mdc_mdio", "rgmii_via_gmac2";
 164                 };
 165         };
 166
 167         i2c1_pins: i2c1-pins {
 168                 mux {
 169                         function = "i2c";
 170                         groups =  "i2c1_0";
 171                 };
 172         };
 173
 174         i2c2_pins: i2c2-pins {
 175                 mux {
 176                         function = "i2c";
 177                         groups =  "i2c2_0";
 178                 };
 179         };
 180
 181         i2s1_pins: i2s1-pins {
 182                 mux {
 183                         function = "i2s";
 184                         groups =  "i2s_out_mclk_bclk_ws",
 185                                   "i2s1_in_data",
 186                                   "i2s1_out_data";
 187                 };
 188
 189                 conf {
 190                         pins = "I2S1_IN", "I2S1_OUT", "I2S_BCLK",
 191                                "I2S_WS", "I2S_MCLK";
 192                         drive-strength = <12>;
 193                         bias-pull-down;
 194                 };
 195         };
 196
 197         irrx_pins: irrx-pins {
 198                 mux {
 199                         function = "ir";
 200                         groups =  "ir_1_rx";
 201                 };
 202         };
 203
 204         irtx_pins: irtx-pins {
 205                 mux {
 206                         function = "ir";
 207                         groups =  "ir_1_tx";
 208                 };
 209         };
 210
 211         /* Parallel nand is shared pin with eMMC */
 212         parallel_nand_pins: parallel-nand-pins {
 213                 mux {
 214                         function = "flash";
 215                         groups = "par_nand";
 216                 };
 217         };
 218
 219         pcie0_pins: pcie0-pins {
 220                 mux {
 221                         function = "pcie";
 222                         groups = "pcie0_pad_perst",
 223                                  "pcie0_1_waken",
 224                                  "pcie0_1_clkreq";
 225                 };
 226         };
 227
 228         pcie1_pins: pcie1-pins {
 229                 mux {
 230                         function = "pcie";
 231                         groups = "pcie1_pad_perst",
 232                                  "pcie1_0_waken",
 233                                  "pcie1_0_clkreq";
 234                 };
 235         };
 236
 237         pmic_bus_pins: pmic-bus-pins {
 238                 mux {
 239                         function = "pmic";
 240                         groups = "pmic_bus";
 241                 };
 242         };
 243
 244         pwm7_pins: pwm1-2-pins {
 245                 mux {
 246                         function = "pwm";
 247                         groups = "pwm_ch7_2";
 248                 };
 249         };
 250
 251         wled_pins: wled-pins {
 252                 mux {
 253                         function = "led";
 254                         groups = "wled";
 255                 };
 256         };
 257
 258         sd0_pins_default: sd0-pins-default {
 259                 mux {
 260                         function = "sd";
 261                         groups = "sd_0";
 262                 };
 263
 264                 /* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN",
 265                  *  "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1,
 266                  *  DAT2, DAT3, CMD, CLK for SD respectively.
 267                  */
 268                 conf-cmd-data {
 269                         pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
 270                                "I2S2_IN","I2S4_OUT";
 271                         input-enable;
 272                         drive-strength = <8>;
 273                         bias-pull-up;
 274                 };
 275                 conf-clk {
 276                         pins = "I2S3_OUT";
 277                         drive-strength = <12>;
 278                         bias-pull-down;
 279                 };
 280                 conf-cd {
 281                         pins = "TXD3";
 282                         bias-pull-up;
 283                 };
 284         };
 285
 286         sd0_pins_uhs: sd0-pins-uhs {
 287                 mux {
 288                         function = "sd";
 289                         groups = "sd_0";
 290                 };
 291
 292                 conf-cmd-data {
 293                         pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
 294                                "I2S2_IN","I2S4_OUT";
 295                         input-enable;
 296                         bias-pull-up;
 297                 };
 298
 299                 conf-clk {
 300                         pins = "I2S3_OUT";
 301                         bias-pull-down;
 302                 };
 303         };
 304
 305         /* Serial NAND is shared pin with SPI-NOR */
 306         serial_nand_pins: serial-nand-pins {
 307                 mux {
 308                         function = "flash";
 309                         groups = "snfi";
 310                 };
 311         };
 312
 313         spic0_pins: spic0-pins {
 314                 mux {
 315                         function = "spi";
 316                         groups = "spic0_0";
 317                 };
 318         };
 319
 320         spic1_pins: spic1-pins {
 321                 mux {
 322                         function = "spi";
 323                         groups = "spic1_0";
 324                 };
 325         };
 326
 327         /* SPI-NOR is shared pin with serial NAND */
 328         spi_nor_pins: spi-nor-pins {
 329                 mux {
 330                         function = "flash";
 331                         groups = "spi_nor";
 332                 };
 333         };
 334
 335         /* serial NAND is shared pin with SPI-NOR */
 336         serial_nand_pins: serial-nand-pins {
 337                 mux {
 338                         function = "flash";
 339                         groups = "snfi";
 340                 };
 341         };
 342
 343         uart0_pins: uart0-pins {
 344                 mux {
 345                         function = "uart";
 346                         groups = "uart0_0_tx_rx" ;
 347                 };
 348         };
 349
 350         uart2_pins: uart2-pins {
 351                 mux {
 352                         function = "uart";
 353                         groups = "uart2_1_tx_rx" ;
 354                 };
 355         };
 356
 357         watchdog_pins: watchdog-pins {
 358                 mux {
 359                         function = "watchdog";
 360                         groups = "watchdog";
 361                 };
 362         };
 363 };
 364
 365 &bch {
 366         status = "okay";
 367 };
 368
 369 &btif {
 370         status = "okay";
 371 };
 372
 373 &cir {
 374         pinctrl-names = "default";
 375         pinctrl-0 = <&irrx_pins>;
 376         status = "okay";
 377 };
 378
 379 &eth {
 380         status = "okay";
 381         gmac0: mac@0 {
 382                 compatible = "mediatek,eth-mac";
 383                 reg = <0>;
 384                 phy-mode = "sgmii";
 385                 fixed-link {
 386                         speed = <1000>;
 387                         full-duplex;
 388                         pause;
 389                 };
 390         };
 391         gmac1: mac@1 {
 392                 compatible = "mediatek,eth-mac";
 393                 reg = <1>;
 394                 phy-mode = "rgmii";
 395                 fixed-link {
 396                         speed = <1000>;
 397                         full-duplex;
 398                         pause;
 399                 };
 400         };
 401         mdio: mdio-bus {
 402                 #address-cells = <1>;
 403                 #size-cells = <0>;
 404         };
 405 };
 406
 407 &gsw {
 408         mediatek,mdio = <&mdio>;
 409         mediatek,portmap = "llllw";
 410         mediatek,mdio_master_pinmux = <0>;
 411         reset-gpios = <&pio 54 0>;
 412         interrupt-parent = <&pio>;
 413         interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
 414         status = "okay";
 415
 416         port5: port@5 {
 417                 compatible = "mediatek,mt753x-port";
 418                 reg = <5>;
 419                 phy-mode = "rgmii";
 420                 fixed-link {
 421                         speed = <1000>;
 422                         full-duplex;
 423                 };
 424         };
 425
 426         port6: port@6 {
 427                 compatible = "mediatek,mt753x-port";
 428                 reg = <6>;
 429                 phy-mode = "sgmii";
 430                 fixed-link {
 431                         speed = <2500>;
 432                         full-duplex;
 433                 };
 434         };
 435 };
 436
 437 &i2c1 {
 438         pinctrl-names = "default";
 439         pinctrl-0 = <&i2c1_pins>;
 440         status = "okay";
 441 };
 442
 443 &i2c2 {
 444         pinctrl-names = "default";
 445         pinctrl-0 = <&i2c2_pins>;
 446         status = "okay";
 447 };
 448
 449 &mmc0 {
 450         pinctrl-names = "default", "state_uhs";
 451         pinctrl-0 = <&emmc_pins_default>;
 452         pinctrl-1 = <&emmc_pins_uhs>;
 453         status = "okay";
 454         bus-width = <8>;
 455         max-frequency = <50000000>;
 456         cap-mmc-highspeed;
 457         mmc-hs200-1_8v;
 458         vmmc-supply = <&reg_3p3v>;
 459         vqmmc-supply = <&reg_1p8v>;
 460         assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
 461         assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
 462         non-removable;
 463 };
 464
 465 &mmc1 {
 466         pinctrl-names = "default", "state_uhs";
 467         pinctrl-0 = <&sd0_pins_default>;
 468         pinctrl-1 = <&sd0_pins_uhs>;
 469         status = "okay";
 470         bus-width = <4>;
 471         max-frequency = <50000000>;
 472         cap-sd-highspeed;
 473         r_smpl = <1>;
 474         cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>;
 475         vmmc-supply = <&reg_3p3v>;
 476         vqmmc-supply = <&reg_3p3v>;
 477         assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
 478         assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
 479 };
 480
 481 &nandc {
 482         pinctrl-names = "default";
 483         pinctrl-0 = <&parallel_nand_pins>;
 484         status = "disabled";
 485 };
 486
 487 &nor_flash {
 488         pinctrl-names = "default";
 489         pinctrl-0 = <&spi_nor_pins>;
 490         status = "disabled";
 491
 492         flash@0 {
 493                 compatible = "jedec,spi-nor";
 494                 reg = <0>;
 495         };
 496 };
 497
 498 &pwm {
 499         pinctrl-names = "default";
 500         pinctrl-0 = <&pwm7_pins>;
 501         status = "okay";
 502 };
 503
 504 &pwrap {
 505         pinctrl-names = "default";
 506         pinctrl-0 = <&pmic_bus_pins>;
 507
 508         status = "okay";
 509 };
 510
 511 &snfi {
 512         pinctrl-names = "default";
 513         pinctrl-0 = <&serial_nand_pins>;
 514         status = "okay";
 515
 516         spi_nand@0 {
 517                 #address-cells = <1>;
 518                 #size-cells = <1>;
 519                 compatible = "spi-nand";
 520                 spi-max-frequency = <104000000>;
 521                 reg = <0>;
 522
 523                 partitions {
 524                         compatible = "fixed-partitions";
 525                         #address-cells = <1>;
 526                         #size-cells = <1>;
 527
 528                         partition@0 {
 529                                 label = "Preloader";
 530                                 reg = <0x00000 0x0080000>;
 531                                 read-only;
 532                         };
 533
 534                         partition@80000 {
 535                                 label = "ATF";
 536                                 reg = <0x80000 0x0040000>;
 537                         };
 538
 539                         partition@c0000 {
 540                                 label = "Bootloader";
 541                                 reg = <0xc0000 0x0080000>;
 542                         };
 543
 544                         partition@140000 {
 545                                 label = "Config";
 546                                 reg = <0x140000 0x0080000>;
 547                         };
 548
 549                         partition@1c0000 {
 550                                 label = "Factory";
 551                                 reg = <0x1c0000 0x0040000>;
 552                         };
 553
 554                         partition@200000 {
 555                                 label = "Kernel";
 556                                 reg = <0x200000 0x2000000>;
 557                         };
 558
 559                         partition@2200000 {
 560                                 label = "User_data";
 561                                 reg = <0x2200000 0x4000000>;
 562                         };
 563                 };
 564         };
 565 };
 566
 567 &spi0 {
 568         pinctrl-names = "default";
 569         pinctrl-0 = <&spic0_pins>;
 570         status = "okay";
 571 };
 572
 573 &spi1 {
 574         pinctrl-names = "default";
 575         pinctrl-0 = <&spic1_pins>;
 576         status = "okay";
 577 };
 578
 579 &ssusb {
 580         vusb33-supply = <&reg_3p3v>;
 581         vbus-supply = <&reg_5v>;
 582         status = "okay";
 583 };
 584
 585 &u3phy {
 586         status = "okay";
 587 };
 588
 589 &uart0 {
 590         pinctrl-names = "default";
 591         pinctrl-0 = <&uart0_pins>;
 592         status = "okay";
 593 };
 594
 595 &uart2 {
 596         pinctrl-names = "default";
 597         pinctrl-0 = <&uart2_pins>;
 598         status = "okay";
 599 };
 600
 601 &watchdog {
 602         pinctrl-names = "default";
 603         pinctrl-0 = <&watchdog_pins>;
 604         status = "okay";
 605 };