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[openwrt/openwrt.git] / target / linux / mediatek / files-5.10 / drivers / net / phy / mtk / mt753x / mt7530.c
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2018 MediaTek Inc.
4 * Author: Weijie Gao <weijie.gao@mediatek.com>
5 */
6
7 #include <linux/kernel.h>
8 #include <linux/delay.h>
9
10 #include "mt753x.h"
11 #include "mt753x_regs.h"
12
13 /* MT7530 registers */
14
15 /* Unique fields of PMCR for MT7530 */
16 #define FORCE_MODE BIT(15)
17
18 /* Unique fields of GMACCR for MT7530 */
19 #define VLAN_SUPT_NO_S 14
20 #define VLAN_SUPT_NO_M 0x1c000
21 #define LATE_COL_DROP BIT(13)
22
23 /* Unique fields of (M)HWSTRAP for MT7530 */
24 #define BOND_OPTION BIT(24)
25 #define P5_PHY0_SEL BIT(20)
26 #define CHG_TRAP BIT(16)
27 #define LOOPDET_DIS BIT(14)
28 #define P5_INTF_SEL_GMAC5 BIT(13)
29 #define SMI_ADDR_S 11
30 #define SMI_ADDR_M 0x1800
31 #define XTAL_FSEL_S 9
32 #define XTAL_FSEL_M 0x600
33 #define P6_INTF_DIS BIT(8)
34 #define P5_INTF_MODE_RGMII BIT(7)
35 #define P5_INTF_DIS_S BIT(6)
36 #define C_MDIO_BPS_S BIT(5)
37 #define EEPROM_EN_S BIT(4)
38
39 /* PHY EEE Register bitmap of define */
40 #define PHY_DEV07 0x07
41 #define PHY_DEV07_REG_03C 0x3c
42
43 /* PHY Extend Register 0x14 bitmap of define */
44 #define PHY_EXT_REG_14 0x14
45
46 /* Fields of PHY_EXT_REG_14 */
47 #define PHY_EN_DOWN_SHFIT BIT(4)
48
49 /* PHY Token Ring Register 0x10 bitmap of define */
50 #define PHY_TR_REG_10 0x10
51
52 /* PHY Token Ring Register 0x12 bitmap of define */
53 #define PHY_TR_REG_12 0x12
54
55 /* PHY LPI PCS/DSP Control Register bitmap of define */
56 #define PHY_LPI_REG_11 0x11
57
58 /* PHY DEV 0x1e Register bitmap of define */
59 #define PHY_DEV1E 0x1e
60 #define PHY_DEV1E_REG_123 0x123
61 #define PHY_DEV1E_REG_A6 0xa6
62
63 /* Values of XTAL_FSEL */
64 #define XTAL_20MHZ 1
65 #define XTAL_40MHZ 2
66 #define XTAL_25MHZ 3
67
68 #define P6ECR 0x7830
69 #define P6_INTF_MODE_TRGMII BIT(0)
70
71 #define TRGMII_TXCTRL 0x7a40
72 #define TRAIN_TXEN BIT(31)
73 #define TXC_INV BIT(30)
74 #define TX_DOEO BIT(29)
75 #define TX_RST BIT(28)
76
77 #define TRGMII_TD0_CTRL 0x7a50
78 #define TRGMII_TD1_CTRL 0x7a58
79 #define TRGMII_TD2_CTRL 0x7a60
80 #define TRGMII_TD3_CTRL 0x7a68
81 #define TRGMII_TXCTL_CTRL 0x7a70
82 #define TRGMII_TCK_CTRL 0x7a78
83 #define TRGMII_TD_CTRL(n) (0x7a50 + (n) * 8)
84 #define NUM_TRGMII_CTRL 6
85 #define TX_DMPEDRV BIT(31)
86 #define TX_DM_SR BIT(15)
87 #define TX_DMERODT BIT(14)
88 #define TX_DMOECTL BIT(13)
89 #define TX_TAP_S 8
90 #define TX_TAP_M 0xf00
91 #define TX_TRAIN_WD_S 0
92 #define TX_TRAIN_WD_M 0xff
93
94 #define TRGMII_TD0_ODT 0x7a54
95 #define TRGMII_TD1_ODT 0x7a5c
96 #define TRGMII_TD2_ODT 0x7a64
97 #define TRGMII_TD3_ODT 0x7a6c
98 #define TRGMII_TXCTL_ODT 0x7574
99 #define TRGMII_TCK_ODT 0x757c
100 #define TRGMII_TD_ODT(n) (0x7a54 + (n) * 8)
101 #define NUM_TRGMII_ODT 6
102 #define TX_DM_DRVN_PRE_S 30
103 #define TX_DM_DRVN_PRE_M 0xc0000000
104 #define TX_DM_DRVP_PRE_S 28
105 #define TX_DM_DRVP_PRE_M 0x30000000
106 #define TX_DM_TDSEL_S 24
107 #define TX_DM_TDSEL_M 0xf000000
108 #define TX_ODTEN BIT(23)
109 #define TX_DME_PRE BIT(20)
110 #define TX_DM_DRVNT0 BIT(19)
111 #define TX_DM_DRVPT0 BIT(18)
112 #define TX_DM_DRVNTE BIT(17)
113 #define TX_DM_DRVPTE BIT(16)
114 #define TX_DM_ODTN_S 12
115 #define TX_DM_ODTN_M 0x7000
116 #define TX_DM_ODTP_S 8
117 #define TX_DM_ODTP_M 0x700
118 #define TX_DM_DRVN_S 4
119 #define TX_DM_DRVN_M 0xf0
120 #define TX_DM_DRVP_S 0
121 #define TX_DM_DRVP_M 0x0f
122
123 #define P5RGMIIRXCR 0x7b00
124 #define CSR_RGMII_RCTL_CFG_S 24
125 #define CSR_RGMII_RCTL_CFG_M 0x7000000
126 #define CSR_RGMII_RXD_CFG_S 16
127 #define CSR_RGMII_RXD_CFG_M 0x70000
128 #define CSR_RGMII_EDGE_ALIGN BIT(8)
129 #define CSR_RGMII_RXC_90DEG_CFG_S 4
130 #define CSR_RGMII_RXC_90DEG_CFG_M 0xf0
131 #define CSR_RGMII_RXC_0DEG_CFG_S 0
132 #define CSR_RGMII_RXC_0DEG_CFG_M 0x0f
133
134 #define P5RGMIITXCR 0x7b04
135 #define CSR_RGMII_TXEN_CFG_S 16
136 #define CSR_RGMII_TXEN_CFG_M 0x70000
137 #define CSR_RGMII_TXD_CFG_S 8
138 #define CSR_RGMII_TXD_CFG_M 0x700
139 #define CSR_RGMII_TXC_CFG_S 0
140 #define CSR_RGMII_TXC_CFG_M 0x1f
141
142 #define CHIP_REV 0x7ffc
143 #define CHIP_NAME_S 16
144 #define CHIP_NAME_M 0xffff0000
145 #define CHIP_REV_S 0
146 #define CHIP_REV_M 0x0f
147
148 /* MMD registers */
149 #define CORE_PLL_GROUP2 0x401
150 #define RG_SYSPLL_EN_NORMAL BIT(15)
151 #define RG_SYSPLL_VODEN BIT(14)
152 #define RG_SYSPLL_POSDIV_S 5
153 #define RG_SYSPLL_POSDIV_M 0x60
154
155 #define CORE_PLL_GROUP4 0x403
156 #define RG_SYSPLL_DDSFBK_EN BIT(12)
157 #define RG_SYSPLL_BIAS_EN BIT(11)
158 #define RG_SYSPLL_BIAS_LPF_EN BIT(10)
159
160 #define CORE_PLL_GROUP5 0x404
161 #define RG_LCDDS_PCW_NCPO1_S 0
162 #define RG_LCDDS_PCW_NCPO1_M 0xffff
163
164 #define CORE_PLL_GROUP6 0x405
165 #define RG_LCDDS_PCW_NCPO0_S 0
166 #define RG_LCDDS_PCW_NCPO0_M 0xffff
167
168 #define CORE_PLL_GROUP7 0x406
169 #define RG_LCDDS_PWDB BIT(15)
170 #define RG_LCDDS_ISO_EN BIT(13)
171 #define RG_LCCDS_C_S 4
172 #define RG_LCCDS_C_M 0x70
173 #define RG_LCDDS_PCW_NCPO_CHG BIT(3)
174
175 #define CORE_PLL_GROUP10 0x409
176 #define RG_LCDDS_SSC_DELTA_S 0
177 #define RG_LCDDS_SSC_DELTA_M 0xfff
178
179 #define CORE_PLL_GROUP11 0x40a
180 #define RG_LCDDS_SSC_DELTA1_S 0
181 #define RG_LCDDS_SSC_DELTA1_M 0xfff
182
183 #define CORE_GSWPLL_GCR_1 0x040d
184 #define GSWPLL_PREDIV_S 14
185 #define GSWPLL_PREDIV_M 0xc000
186 #define GSWPLL_POSTDIV_200M_S 12
187 #define GSWPLL_POSTDIV_200M_M 0x3000
188 #define GSWPLL_EN_PRE BIT(11)
189 #define GSWPLL_FBKSEL BIT(10)
190 #define GSWPLL_BP BIT(9)
191 #define GSWPLL_BR BIT(8)
192 #define GSWPLL_FBKDIV_200M_S 0
193 #define GSWPLL_FBKDIV_200M_M 0xff
194
195 #define CORE_GSWPLL_GCR_2 0x040e
196 #define GSWPLL_POSTDIV_500M_S 8
197 #define GSWPLL_POSTDIV_500M_M 0x300
198 #define GSWPLL_FBKDIV_500M_S 0
199 #define GSWPLL_FBKDIV_500M_M 0xff
200
201 #define TRGMII_GSW_CLK_CG 0x0410
202 #define TRGMIICK_EN BIT(1)
203 #define GSWCK_EN BIT(0)
204
205 static int mt7530_mii_read(struct gsw_mt753x *gsw, int phy, int reg)
206 {
207 if (phy < MT753X_NUM_PHYS)
208 phy = (gsw->phy_base + phy) & MT753X_SMI_ADDR_MASK;
209
210 return mdiobus_read(gsw->host_bus, phy, reg);
211 }
212
213 static void mt7530_mii_write(struct gsw_mt753x *gsw, int phy, int reg, u16 val)
214 {
215 if (phy < MT753X_NUM_PHYS)
216 phy = (gsw->phy_base + phy) & MT753X_SMI_ADDR_MASK;
217
218 mdiobus_write(gsw->host_bus, phy, reg, val);
219 }
220
221 static int mt7530_mmd_read(struct gsw_mt753x *gsw, int addr, int devad, u16 reg)
222 {
223 u16 val;
224
225 if (addr < MT753X_NUM_PHYS)
226 addr = (gsw->phy_base + addr) & MT753X_SMI_ADDR_MASK;
227
228 mutex_lock(&gsw->host_bus->mdio_lock);
229
230 gsw->host_bus->write(gsw->host_bus, addr, MII_MMD_ACC_CTL_REG,
231 (MMD_ADDR << MMD_CMD_S) |
232 ((devad << MMD_DEVAD_S) & MMD_DEVAD_M));
233
234 gsw->host_bus->write(gsw->host_bus, addr, MII_MMD_ADDR_DATA_REG, reg);
235
236 gsw->host_bus->write(gsw->host_bus, addr, MII_MMD_ACC_CTL_REG,
237 (MMD_DATA << MMD_CMD_S) |
238 ((devad << MMD_DEVAD_S) & MMD_DEVAD_M));
239
240 val = gsw->host_bus->read(gsw->host_bus, addr, MII_MMD_ADDR_DATA_REG);
241
242 mutex_unlock(&gsw->host_bus->mdio_lock);
243
244 return val;
245 }
246
247 static void mt7530_mmd_write(struct gsw_mt753x *gsw, int addr, int devad,
248 u16 reg, u16 val)
249 {
250 if (addr < MT753X_NUM_PHYS)
251 addr = (gsw->phy_base + addr) & MT753X_SMI_ADDR_MASK;
252
253 mutex_lock(&gsw->host_bus->mdio_lock);
254
255 gsw->host_bus->write(gsw->host_bus, addr, MII_MMD_ACC_CTL_REG,
256 (MMD_ADDR << MMD_CMD_S) |
257 ((devad << MMD_DEVAD_S) & MMD_DEVAD_M));
258
259 gsw->host_bus->write(gsw->host_bus, addr, MII_MMD_ADDR_DATA_REG, reg);
260
261 gsw->host_bus->write(gsw->host_bus, addr, MII_MMD_ACC_CTL_REG,
262 (MMD_DATA << MMD_CMD_S) |
263 ((devad << MMD_DEVAD_S) & MMD_DEVAD_M));
264
265 gsw->host_bus->write(gsw->host_bus, addr, MII_MMD_ADDR_DATA_REG, val);
266
267 mutex_unlock(&gsw->host_bus->mdio_lock);
268 }
269
270 static void mt7530_core_reg_write(struct gsw_mt753x *gsw, u32 reg, u32 val)
271 {
272 gsw->mmd_write(gsw, 0, 0x1f, reg, val);
273 }
274
275 static void mt7530_trgmii_setting(struct gsw_mt753x *gsw)
276 {
277 u16 i;
278
279 mt7530_core_reg_write(gsw, CORE_PLL_GROUP5, 0x0780);
280 mdelay(1);
281 mt7530_core_reg_write(gsw, CORE_PLL_GROUP6, 0);
282 mt7530_core_reg_write(gsw, CORE_PLL_GROUP10, 0x87);
283 mdelay(1);
284 mt7530_core_reg_write(gsw, CORE_PLL_GROUP11, 0x87);
285
286 /* PLL BIAS enable */
287 mt7530_core_reg_write(gsw, CORE_PLL_GROUP4,
288 RG_SYSPLL_DDSFBK_EN | RG_SYSPLL_BIAS_EN);
289 mdelay(1);
290
291 /* PLL LPF enable */
292 mt7530_core_reg_write(gsw, CORE_PLL_GROUP4,
293 RG_SYSPLL_DDSFBK_EN |
294 RG_SYSPLL_BIAS_EN | RG_SYSPLL_BIAS_LPF_EN);
295
296 /* sys PLL enable */
297 mt7530_core_reg_write(gsw, CORE_PLL_GROUP2,
298 RG_SYSPLL_EN_NORMAL | RG_SYSPLL_VODEN |
299 (1 << RG_SYSPLL_POSDIV_S));
300
301 /* LCDDDS PWDS */
302 mt7530_core_reg_write(gsw, CORE_PLL_GROUP7,
303 (3 << RG_LCCDS_C_S) |
304 RG_LCDDS_PWDB | RG_LCDDS_ISO_EN);
305 mdelay(1);
306
307 /* Enable MT7530 TRGMII clock */
308 mt7530_core_reg_write(gsw, TRGMII_GSW_CLK_CG, GSWCK_EN | TRGMIICK_EN);
309
310 /* lower Tx Driving */
311 for (i = 0 ; i < NUM_TRGMII_ODT; i++)
312 mt753x_reg_write(gsw, TRGMII_TD_ODT(i),
313 (4 << TX_DM_DRVP_S) | (4 << TX_DM_DRVN_S));
314 }
315
316 static void mt7530_rgmii_setting(struct gsw_mt753x *gsw)
317 {
318 u32 val;
319
320 mt7530_core_reg_write(gsw, CORE_PLL_GROUP5, 0x0c80);
321 mdelay(1);
322 mt7530_core_reg_write(gsw, CORE_PLL_GROUP6, 0);
323 mt7530_core_reg_write(gsw, CORE_PLL_GROUP10, 0x87);
324 mdelay(1);
325 mt7530_core_reg_write(gsw, CORE_PLL_GROUP11, 0x87);
326
327 val = mt753x_reg_read(gsw, TRGMII_TXCTRL);
328 val &= ~TXC_INV;
329 mt753x_reg_write(gsw, TRGMII_TXCTRL, val);
330
331 mt753x_reg_write(gsw, TRGMII_TCK_CTRL,
332 (8 << TX_TAP_S) | (0x55 << TX_TRAIN_WD_S));
333 }
334
335 static int mt7530_mac_port_setup(struct gsw_mt753x *gsw)
336 {
337 u32 hwstrap, p6ecr = 0, p5mcr, p6mcr, phyad;
338
339 hwstrap = mt753x_reg_read(gsw, MHWSTRAP);
340 hwstrap &= ~(P6_INTF_DIS | P5_INTF_MODE_RGMII | P5_INTF_DIS_S);
341 hwstrap |= P5_INTF_SEL_GMAC5;
342 if (!gsw->port5_cfg.enabled) {
343 p5mcr = FORCE_MODE;
344 hwstrap |= P5_INTF_DIS_S;
345 } else {
346 p5mcr = (IPG_96BIT_WITH_SHORT_IPG << IPG_CFG_S) |
347 MAC_MODE | MAC_TX_EN | MAC_RX_EN |
348 BKOFF_EN | BACKPR_EN;
349
350 if (gsw->port5_cfg.force_link) {
351 p5mcr |= FORCE_MODE | FORCE_LINK | FORCE_RX_FC |
352 FORCE_TX_FC;
353 p5mcr |= gsw->port5_cfg.speed << FORCE_SPD_S;
354
355 if (gsw->port5_cfg.duplex)
356 p5mcr |= FORCE_DPX;
357 }
358
359 switch (gsw->port5_cfg.phy_mode) {
360 case PHY_INTERFACE_MODE_MII:
361 case PHY_INTERFACE_MODE_GMII:
362 break;
363 case PHY_INTERFACE_MODE_RGMII:
364 hwstrap |= P5_INTF_MODE_RGMII;
365 break;
366 default:
367 dev_info(gsw->dev, "%s is not supported by port5\n",
368 phy_modes(gsw->port5_cfg.phy_mode));
369 p5mcr = FORCE_MODE;
370 hwstrap |= P5_INTF_DIS_S;
371 }
372
373 /* Port5 to PHY direct mode */
374 if (of_property_read_u32(gsw->port5_cfg.np, "phy-address",
375 &phyad))
376 goto parse_p6;
377
378 if (phyad != 0 && phyad != 4) {
379 dev_info(gsw->dev,
380 "Only PHY 0/4 can be connected to Port 5\n");
381 goto parse_p6;
382 }
383
384 hwstrap &= ~P5_INTF_SEL_GMAC5;
385 if (phyad == 0)
386 hwstrap |= P5_PHY0_SEL;
387 else
388 hwstrap &= ~P5_PHY0_SEL;
389 }
390
391 parse_p6:
392 if (!gsw->port6_cfg.enabled) {
393 p6mcr = FORCE_MODE;
394 hwstrap |= P6_INTF_DIS;
395 } else {
396 p6mcr = (IPG_96BIT_WITH_SHORT_IPG << IPG_CFG_S) |
397 MAC_MODE | MAC_TX_EN | MAC_RX_EN |
398 BKOFF_EN | BACKPR_EN;
399
400 if (gsw->port6_cfg.force_link) {
401 p6mcr |= FORCE_MODE | FORCE_LINK | FORCE_RX_FC |
402 FORCE_TX_FC;
403 p6mcr |= gsw->port6_cfg.speed << FORCE_SPD_S;
404
405 if (gsw->port6_cfg.duplex)
406 p6mcr |= FORCE_DPX;
407 }
408
409 switch (gsw->port6_cfg.phy_mode) {
410 case PHY_INTERFACE_MODE_RGMII:
411 p6ecr = BIT(1);
412 break;
413 case PHY_INTERFACE_MODE_TRGMII:
414 /* set MT7530 central align */
415 p6ecr = BIT(0);
416 break;
417 default:
418 dev_info(gsw->dev, "%s is not supported by port6\n",
419 phy_modes(gsw->port6_cfg.phy_mode));
420 p6mcr = FORCE_MODE;
421 hwstrap |= P6_INTF_DIS;
422 }
423 }
424
425 mt753x_reg_write(gsw, MHWSTRAP, hwstrap);
426 mt753x_reg_write(gsw, P6ECR, p6ecr);
427
428 mt753x_reg_write(gsw, PMCR(5), p5mcr);
429 mt753x_reg_write(gsw, PMCR(6), p6mcr);
430
431 return 0;
432 }
433
434 static void mt7530_core_pll_setup(struct gsw_mt753x *gsw)
435 {
436 u32 hwstrap;
437
438 hwstrap = mt753x_reg_read(gsw, HWSTRAP);
439
440 switch ((hwstrap & XTAL_FSEL_M) >> XTAL_FSEL_S) {
441 case XTAL_40MHZ:
442 /* Disable MT7530 core clock */
443 mt7530_core_reg_write(gsw, TRGMII_GSW_CLK_CG, 0);
444
445 /* disable MT7530 PLL */
446 mt7530_core_reg_write(gsw, CORE_GSWPLL_GCR_1,
447 (2 << GSWPLL_POSTDIV_200M_S) |
448 (32 << GSWPLL_FBKDIV_200M_S));
449
450 /* For MT7530 core clock = 500Mhz */
451 mt7530_core_reg_write(gsw, CORE_GSWPLL_GCR_2,
452 (1 << GSWPLL_POSTDIV_500M_S) |
453 (25 << GSWPLL_FBKDIV_500M_S));
454
455 /* Enable MT7530 PLL */
456 mt7530_core_reg_write(gsw, CORE_GSWPLL_GCR_1,
457 (2 << GSWPLL_POSTDIV_200M_S) |
458 (32 << GSWPLL_FBKDIV_200M_S) |
459 GSWPLL_EN_PRE);
460
461 usleep_range(20, 40);
462
463 /* Enable MT7530 core clock */
464 mt7530_core_reg_write(gsw, TRGMII_GSW_CLK_CG, GSWCK_EN);
465 break;
466 default:
467 /* TODO: PLL settings for 20/25MHz */
468 break;
469 }
470
471 hwstrap = mt753x_reg_read(gsw, HWSTRAP);
472 hwstrap |= CHG_TRAP;
473 if (gsw->direct_phy_access)
474 hwstrap &= ~C_MDIO_BPS_S;
475 else
476 hwstrap |= C_MDIO_BPS_S;
477
478 mt753x_reg_write(gsw, MHWSTRAP, hwstrap);
479
480 if (gsw->port6_cfg.enabled &&
481 gsw->port6_cfg.phy_mode == PHY_INTERFACE_MODE_TRGMII) {
482 mt7530_trgmii_setting(gsw);
483 } else {
484 /* RGMII */
485 mt7530_rgmii_setting(gsw);
486 }
487
488 /* delay setting for 10/1000M */
489 mt753x_reg_write(gsw, P5RGMIIRXCR,
490 CSR_RGMII_EDGE_ALIGN |
491 (2 << CSR_RGMII_RXC_0DEG_CFG_S));
492 mt753x_reg_write(gsw, P5RGMIITXCR, 0x14 << CSR_RGMII_TXC_CFG_S);
493 }
494
495 static int mt7530_sw_detect(struct gsw_mt753x *gsw, struct chip_rev *crev)
496 {
497 u32 rev;
498
499 rev = mt753x_reg_read(gsw, CHIP_REV);
500
501 if (((rev & CHIP_NAME_M) >> CHIP_NAME_S) == MT7530) {
502 if (crev) {
503 crev->rev = rev & CHIP_REV_M;
504 crev->name = "MT7530";
505 }
506
507 return 0;
508 }
509
510 return -ENODEV;
511 }
512
513 static void mt7530_phy_setting(struct gsw_mt753x *gsw)
514 {
515 int i;
516 u32 val;
517
518 for (i = 0; i < MT753X_NUM_PHYS; i++) {
519 /* Disable EEE */
520 gsw->mmd_write(gsw, i, PHY_DEV07, PHY_DEV07_REG_03C, 0);
521
522 /* Enable HW auto downshift */
523 gsw->mii_write(gsw, i, 0x1f, 0x1);
524 val = gsw->mii_read(gsw, i, PHY_EXT_REG_14);
525 val |= PHY_EN_DOWN_SHFIT;
526 gsw->mii_write(gsw, i, PHY_EXT_REG_14, val);
527
528 /* Increase SlvDPSready time */
529 gsw->mii_write(gsw, i, 0x1f, 0x52b5);
530 gsw->mii_write(gsw, i, PHY_TR_REG_10, 0xafae);
531 gsw->mii_write(gsw, i, PHY_TR_REG_12, 0x2f);
532 gsw->mii_write(gsw, i, PHY_TR_REG_10, 0x8fae);
533
534 /* Increase post_update_timer */
535 gsw->mii_write(gsw, i, 0x1f, 0x3);
536 gsw->mii_write(gsw, i, PHY_LPI_REG_11, 0x4b);
537 gsw->mii_write(gsw, i, 0x1f, 0);
538
539 /* Adjust 100_mse_threshold */
540 gsw->mmd_write(gsw, i, PHY_DEV1E, PHY_DEV1E_REG_123, 0xffff);
541
542 /* Disable mcc */
543 gsw->mmd_write(gsw, i, PHY_DEV1E, PHY_DEV1E_REG_A6, 0x300);
544 }
545 }
546
547 static inline bool get_phy_access_mode(const struct device_node *np)
548 {
549 return of_property_read_bool(np, "mt7530,direct-phy-access");
550 }
551
552 static int mt7530_sw_init(struct gsw_mt753x *gsw)
553 {
554 int i;
555 u32 val;
556
557 gsw->direct_phy_access = get_phy_access_mode(gsw->dev->of_node);
558
559 /* Force MT7530 to use (in)direct PHY access */
560 val = mt753x_reg_read(gsw, HWSTRAP);
561 val |= CHG_TRAP;
562 if (gsw->direct_phy_access)
563 val &= ~C_MDIO_BPS_S;
564 else
565 val |= C_MDIO_BPS_S;
566 mt753x_reg_write(gsw, MHWSTRAP, val);
567
568 /* Read PHY address base from HWSTRAP */
569 gsw->phy_base = (((val & SMI_ADDR_M) >> SMI_ADDR_S) << 3) + 8;
570 gsw->phy_base &= MT753X_SMI_ADDR_MASK;
571
572 if (gsw->direct_phy_access) {
573 gsw->mii_read = mt7530_mii_read;
574 gsw->mii_write = mt7530_mii_write;
575 gsw->mmd_read = mt7530_mmd_read;
576 gsw->mmd_write = mt7530_mmd_write;
577 } else {
578 gsw->mii_read = mt753x_mii_read;
579 gsw->mii_write = mt753x_mii_write;
580 gsw->mmd_read = mt753x_mmd_ind_read;
581 gsw->mmd_write = mt753x_mmd_ind_write;
582 }
583
584 for (i = 0; i < MT753X_NUM_PHYS; i++) {
585 val = gsw->mii_read(gsw, i, MII_BMCR);
586 val |= BMCR_PDOWN;
587 gsw->mii_write(gsw, i, MII_BMCR, val);
588 }
589
590 /* Force MAC link down before reset */
591 mt753x_reg_write(gsw, PMCR(5), FORCE_MODE);
592 mt753x_reg_write(gsw, PMCR(6), FORCE_MODE);
593
594 /* Switch soft reset */
595 /* BUG: sw reset causes gsw int flooding */
596 mt753x_reg_write(gsw, SYS_CTRL, SW_PHY_RST | SW_SYS_RST | SW_REG_RST);
597 usleep_range(10, 20);
598
599 /* global mac control settings configuration */
600 mt753x_reg_write(gsw, GMACCR,
601 LATE_COL_DROP | (15 << MTCC_LMT_S) |
602 (2 << MAX_RX_JUMBO_S) | RX_PKT_LEN_MAX_JUMBO);
603
604 mt7530_core_pll_setup(gsw);
605 mt7530_mac_port_setup(gsw);
606
607 return 0;
608 }
609
610 static int mt7530_sw_post_init(struct gsw_mt753x *gsw)
611 {
612 int i;
613 u32 val;
614
615 mt7530_phy_setting(gsw);
616
617 for (i = 0; i < MT753X_NUM_PHYS; i++) {
618 val = gsw->mii_read(gsw, i, MII_BMCR);
619 val &= ~BMCR_PDOWN;
620 gsw->mii_write(gsw, i, MII_BMCR, val);
621 }
622
623 return 0;
624 }
625
626 struct mt753x_sw_id mt7530_id = {
627 .model = MT7530,
628 .detect = mt7530_sw_detect,
629 .init = mt7530_sw_init,
630 .post_init = mt7530_sw_post_init
631 };
OpenWrt Source Repository