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[openwrt/openwrt.git] / target / linux / mediatek / files-5.15 / arch / arm64 / boot / dts / mediatek / mt7986a.dtsi
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /*
3 * Copyright (C) 2021 MediaTek Inc.
4 * Author: Sam.Shih <sam.shih@mediatek.com>
5 */
6
7 #include <dt-bindings/clock/mt7986-clk.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/phy/phy.h>
11 #include <dt-bindings/reset/mt7986-resets.h>
12 #include <dt-bindings/thermal/thermal.h>
13
14 / {
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
18
19 clk40m: oscillator@0 {
20 compatible = "fixed-clock";
21 clock-frequency = <40000000>;
22 #clock-cells = <0>;
23 clock-output-names = "clkxtal";
24 };
25
26 cpus {
27 #address-cells = <1>;
28 #size-cells = <0>;
29 cpu0: cpu@0 {
30 device_type = "cpu";
31 compatible = "arm,cortex-a53";
32 enable-method = "psci";
33 reg = <0x0>;
34 #cooling-cells = <2>;
35 };
36
37 cpu1: cpu@1 {
38 device_type = "cpu";
39 compatible = "arm,cortex-a53";
40 enable-method = "psci";
41 reg = <0x1>;
42 #cooling-cells = <2>;
43 };
44
45 cpu2: cpu@2 {
46 device_type = "cpu";
47 compatible = "arm,cortex-a53";
48 enable-method = "psci";
49 reg = <0x2>;
50 #cooling-cells = <2>;
51 };
52
53 cpu3: cpu@3 {
54 device_type = "cpu";
55 enable-method = "psci";
56 compatible = "arm,cortex-a53";
57 reg = <0x3>;
58 #cooling-cells = <2>;
59 };
60 };
61
62 psci {
63 compatible = "arm,psci-0.2";
64 method = "smc";
65 };
66
67 reserved-memory {
68 #address-cells = <2>;
69 #size-cells = <2>;
70 ranges;
71
72 /* 64 KiB reserved for ramoops/pstore */
73 ramoops@42ff0000 {
74 compatible = "ramoops";
75 reg = <0 0x42ff0000 0 0x10000>;
76 record-size = <0x1000>;
77 };
78
79 /* 192 KiB reserved for ARM Trusted Firmware (BL31) */
80 secmon_reserved: secmon@43000000 {
81 reg = <0 0x43000000 0 0x30000>;
82 no-map;
83 };
84
85 wmcpu_emi: wmcpu-reserved@4fc00000 {
86 no-map;
87 reg = <0 0x4fc00000 0 0x00100000>;
88 };
89 };
90
91 timer {
92 compatible = "arm,armv8-timer";
93 interrupt-parent = <&gic>;
94 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
95 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
96 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
97 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
98 };
99
100 soc {
101 #address-cells = <2>;
102 #size-cells = <2>;
103 compatible = "simple-bus";
104 ranges;
105
106 gic: interrupt-controller@c000000 {
107 compatible = "arm,gic-v3";
108 #interrupt-cells = <3>;
109 interrupt-parent = <&gic>;
110 interrupt-controller;
111 reg = <0 0x0c000000 0 0x10000>, /* GICD */
112 <0 0x0c080000 0 0x80000>, /* GICR */
113 <0 0x0c400000 0 0x2000>, /* GICC */
114 <0 0x0c410000 0 0x1000>, /* GICH */
115 <0 0x0c420000 0 0x2000>; /* GICV */
116 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
117 };
118
119 infracfg: infracfg@10001000 {
120 compatible = "mediatek,mt7986-infracfg", "syscon";
121 reg = <0 0x10001000 0 0x1000>;
122 #clock-cells = <1>;
123 };
124
125 topckgen: topckgen@1001b000 {
126 compatible = "mediatek,mt7986-topckgen", "syscon";
127 reg = <0 0x1001B000 0 0x1000>;
128 #clock-cells = <1>;
129 };
130
131 watchdog: watchdog@1001c000 {
132 compatible = "mediatek,mt7986-wdt",
133 "mediatek,mt6589-wdt";
134 reg = <0 0x1001c000 0 0x1000>;
135 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
136 #reset-cells = <1>;
137 };
138
139 pio: pinctrl@1001f000 {
140 compatible = "mediatek,mt7986a-pinctrl";
141 reg = <0 0x1001f000 0 0x1000>,
142 <0 0x11c30000 0 0x1000>,
143 <0 0x11c40000 0 0x1000>,
144 <0 0x11e20000 0 0x1000>,
145 <0 0x11e30000 0 0x1000>,
146 <0 0x11f00000 0 0x1000>,
147 <0 0x11f10000 0 0x1000>,
148 <0 0x1000b000 0 0x1000>;
149 reg-names = "gpio", "iocfg_rt", "iocfg_rb", "iocfg_lt",
150 "iocfg_lb", "iocfg_tr", "iocfg_tl", "eint";
151 gpio-controller;
152 #gpio-cells = <2>;
153 gpio-ranges = <&pio 0 0 100>;
154 interrupt-controller;
155 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
156 interrupt-parent = <&gic>;
157 #interrupt-cells = <2>;
158 };
159
160 apmixedsys: apmixedsys@1001e000 {
161 compatible = "mediatek,mt7986-apmixedsys";
162 reg = <0 0x1001E000 0 0x1000>;
163 #clock-cells = <1>;
164 };
165
166 sgmiisys0: syscon@10060000 {
167 compatible = "mediatek,mt7986-sgmiisys_0",
168 "syscon";
169 reg = <0 0x10060000 0 0x1000>;
170 #clock-cells = <1>;
171 };
172
173 sgmiisys1: syscon@10070000 {
174 compatible = "mediatek,mt7986-sgmiisys_1",
175 "syscon";
176 reg = <0 0x10070000 0 0x1000>;
177 #clock-cells = <1>;
178 };
179
180 trng: trng@1020f000 {
181 compatible = "mediatek,mt7986-rng";
182 reg = <0 0x1020f000 0 0x100>;
183 clocks = <&infracfg CLK_INFRA_TRNG_CK>;
184 clock-names = "rng";
185 status = "okay";
186 };
187
188 crypto: crypto@10320000 {
189 compatible = "inside-secure,safexcel-eip97";
190 reg = <0 0x10320000 0 0x40000>;
191 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
192 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
193 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
194 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
195 interrupt-names = "ring0", "ring1", "ring2", "ring3";
196 clocks = <&infracfg CLK_INFRA_EIP97_CK>;
197 clock-names = "infra_eip97_ck";
198 assigned-clocks = <&topckgen CLK_TOP_EIP_B_SEL>;
199 assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>;
200 status = "okay";
201 };
202
203 pwm: pwm@10048000 {
204 compatible = "mediatek,mt7986-pwm";
205 reg = <0 0x10048000 0 0x1000>;
206 #clock-cells = <1>;
207 #pwm-cells = <2>;
208 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
209 clocks = <&infracfg CLK_INFRA_PWM_HCK>,
210 <&infracfg CLK_INFRA_PWM_STA>,
211 <&infracfg CLK_INFRA_PWM1_CK>,
212 <&infracfg CLK_INFRA_PWM2_CK>;
213 clock-names = "top", "main", "pwm1", "pwm2";
214 status = "disabled";
215 };
216
217 uart0: serial@11002000 {
218 compatible = "mediatek,mt7986-uart",
219 "mediatek,mt6577-uart";
220 reg = <0 0x11002000 0 0x400>;
221 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
222 clocks = <&infracfg CLK_INFRA_UART0_SEL>,
223 <&infracfg CLK_INFRA_UART0_CK>;
224 clock-names = "baud", "bus";
225 assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
226 <&infracfg CLK_INFRA_UART0_SEL>;
227 assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
228 <&topckgen CLK_TOP_UART_SEL>;
229 status = "disabled";
230 };
231
232 uart1: serial@11003000 {
233 compatible = "mediatek,mt7986-uart",
234 "mediatek,mt6577-uart";
235 reg = <0 0x11003000 0 0x400>;
236 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
237 clocks = <&infracfg CLK_INFRA_UART1_SEL>,
238 <&infracfg CLK_INFRA_UART1_CK>;
239 clock-names = "baud", "bus";
240 assigned-clocks = <&infracfg CLK_INFRA_UART1_SEL>;
241 assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>;
242 status = "disabled";
243 };
244
245 uart2: serial@11004000 {
246 compatible = "mediatek,mt7986-uart",
247 "mediatek,mt6577-uart";
248 reg = <0 0x11004000 0 0x400>;
249 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
250 clocks = <&infracfg CLK_INFRA_UART2_SEL>,
251 <&infracfg CLK_INFRA_UART2_CK>;
252 clock-names = "baud", "bus";
253 assigned-clocks = <&infracfg CLK_INFRA_UART2_SEL>;
254 assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>;
255 status = "disabled";
256 };
257
258 i2c0: i2c@11008000 {
259 compatible = "mediatek,mt7986-i2c";
260 reg = <0 0x11008000 0 0x90>,
261 <0 0x10217080 0 0x80>;
262 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
263 clock-div = <5>;
264 clocks = <&infracfg CLK_INFRA_I2C0_CK>,
265 <&infracfg CLK_INFRA_AP_DMA_CK>;
266 clock-names = "main", "dma";
267 #address-cells = <1>;
268 #size-cells = <0>;
269 status = "disabled";
270 };
271
272 spi0: spi@1100a000 {
273 compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
274 reg = <0 0x1100a000 0 0x100>;
275 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
276 clocks = <&topckgen CLK_TOP_MPLL_D2>,
277 <&topckgen CLK_TOP_SPI_SEL>,
278 <&infracfg CLK_INFRA_SPI0_CK>,
279 <&infracfg CLK_INFRA_SPI0_HCK_CK>;
280 clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
281 status = "disabled";
282 };
283
284 spi1: spi@1100b000 {
285 compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
286 reg = <0 0x1100b000 0 0x100>;
287 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
288 clocks = <&topckgen CLK_TOP_MPLL_D2>,
289 <&topckgen CLK_TOP_SPIM_MST_SEL>,
290 <&infracfg CLK_INFRA_SPI1_CK>,
291 <&infracfg CLK_INFRA_SPI1_HCK_CK>;
292 clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
293 status = "disabled";
294 };
295
296 auxadc: adc@1100d000 {
297 compatible = "mediatek,mt7986-auxadc",
298 "mediatek,mt7622-auxadc";
299 reg = <0 0x1100d000 0 0x1000>;
300 clocks = <&infracfg CLK_INFRA_ADC_26M_CK>,
301 <&infracfg CLK_INFRA_ADC_FRC_CK>;
302 clock-names = "main", "32k";
303 #io-channel-cells = <1>;
304 };
305
306 ssusb: usb@11200000 {
307 compatible = "mediatek,mt7986-xhci",
308 "mediatek,mtk-xhci";
309 reg = <0 0x11200000 0 0x2e00>,
310 <0 0x11203e00 0 0x0100>;
311 reg-names = "mac", "ippc";
312 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
313 clocks = <&infracfg CLK_INFRA_IUSB_SYS_CK>,
314 <&topckgen CLK_TOP_U2U3_XHCI_SEL>,
315 <&infracfg CLK_INFRA_IUSB_CK>,
316 <&infracfg CLK_INFRA_IUSB_133_CK>,
317 <&infracfg CLK_INFRA_IUSB_66M_CK>;
318 clock-names = "sys_ck",
319 "xhci_ck",
320 "ref_ck",
321 "mcu_ck",
322 "dma_ck";
323 phys = <&u2port0 PHY_TYPE_USB2>,
324 <&u3port0 PHY_TYPE_USB3>,
325 <&u2port1 PHY_TYPE_USB2>;
326 status = "disabled";
327 };
328
329 mmc0: mmc@11230000 {
330 compatible = "mediatek,mt7986-mmc";
331 reg = <0 0x11230000 0 0x1000>,
332 <0 0x11c20000 0 0x1000>;
333 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
334 clocks = <&infracfg CLK_INFRA_MSDC_CK>,
335 <&infracfg CLK_INFRA_MSDC_HCK_CK>,
336 <&infracfg CLK_INFRA_MSDC_66M_CK>,
337 <&infracfg CLK_INFRA_MSDC_133M_CK>;
338 clock-names = "source", "hclk", "axi_cg", "ahb_cg";
339 assigned-clocks = <&topckgen CLK_TOP_EMMC_416M_SEL>,
340 <&topckgen CLK_TOP_EMMC_250M_SEL>;
341 assigned-clock-parents = <&apmixedsys CLK_APMIXED_MPLL>,
342 <&topckgen CLK_TOP_NET1PLL_D5_D2>;
343 status = "disabled";
344 };
345
346 thermal: thermal@1100c800 {
347 #thermal-sensor-cells = <1>;
348 compatible = "mediatek,mt7986-thermal";
349 reg = <0 0x1100c800 0 0x800>;
350 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
351 clocks = <&infracfg CLK_INFRA_THERM_CK>,
352 <&infracfg CLK_INFRA_ADC_26M_CK>,
353 <&infracfg CLK_INFRA_ADC_FRC_CK>;
354 clock-names = "therm", "auxadc", "adc_32k";
355 mediatek,auxadc = <&auxadc>;
356 mediatek,apmixedsys = <&apmixedsys>;
357 nvmem-cells = <&thermal_calibration>;
358 nvmem-cell-names = "calibration-data";
359 };
360
361 pcie: pcie@11280000 {
362 compatible = "mediatek,mt7986-pcie",
363 "mediatek,mt8192-pcie";
364 device_type = "pci";
365 #address-cells = <3>;
366 #size-cells = <2>;
367 reg = <0x00 0x11280000 0x00 0x4000>;
368 reg-names = "pcie-mac";
369 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
370 bus-range = <0x00 0xff>;
371 ranges = <0x82000000 0x00 0x20000000 0x00
372 0x20000000 0x00 0x10000000>;
373 clocks = <&infracfg CLK_INFRA_PCIE_SEL>,
374 <&infracfg CLK_INFRA_IPCIE_CK>,
375 <&infracfg CLK_INFRA_IPCIE_PIPE_CK>,
376 <&infracfg CLK_INFRA_IPCIER_CK>,
377 <&infracfg CLK_INFRA_IPCIEB_CK>;
378 status = "disabled";
379
380 phys = <&pcie_port PHY_TYPE_PCIE>;
381 phy-names = "pcie-phy";
382
383 #interrupt-cells = <1>;
384 interrupt-map-mask = <0 0 0 0x7>;
385 interrupt-map = <0 0 0 1 &pcie_intc 0>,
386 <0 0 0 2 &pcie_intc 1>,
387 <0 0 0 3 &pcie_intc 2>,
388 <0 0 0 4 &pcie_intc 3>;
389 pcie_intc: interrupt-controller {
390 #address-cells = <0>;
391 #interrupt-cells = <1>;
392 interrupt-controller;
393 };
394 };
395
396 pcie_phy: t-phy@11c00000 {
397 compatible = "mediatek,mt7986-tphy",
398 "mediatek,generic-tphy-v4";
399 #address-cells = <2>;
400 #size-cells = <2>;
401 ranges;
402 status = "disabled";
403
404 pcie_port: pcie-phy@11c00000 {
405 reg = <0 0x11c00000 0 0x20000>;
406 clocks = <&clk40m>;
407 clock-names = "ref";
408 #phy-cells = <1>;
409 auto_load_valid;
410 auto_load_valid_ln1;
411 nvmem-cells = <&pcie_intr_ln0>,
412 <&pcie_rx_imp_ln0>,
413 <&pcie_tx_imp_ln0>,
414 <&pcie_auto_load_valid_ln0>,
415 <&pcie_intr_ln1>,
416 <&pcie_rx_imp_ln1>,
417 <&pcie_tx_imp_ln1>,
418 <&pcie_auto_load_valid_ln1>;
419 nvmem-cell-names = "intr",
420 "rx_imp",
421 "tx_imp",
422 "auto_load_valid",
423 "intr_ln1",
424 "rx_imp_ln1",
425 "tx_imp_ln1",
426 "auto_load_valid_ln1";
427 };
428 };
429
430 efuse: efuse@11d00000 {
431 compatible = "mediatek,mt7986-efuse",
432 "mediatek,efuse";
433 reg = <0 0x11d00000 0 0x1000>;
434 #address-cells = <1>;
435 #size-cells = <1>;
436
437 thermal_calibration: calib@274 {
438 reg = <0x274 0xc>;
439 };
440
441 comb_auto_load_valid: usb3-alv-imp@8da {
442 reg = <0x8da 1>;
443 bits = <0 1>;
444 };
445
446 comb_rx_imp_p0: usb3-rx-imp@8d8 {
447 reg = <0x8d8 1>;
448 bits = <0 5>;
449 };
450
451 comb_tx_imp_p0: usb3-tx-imp@8d8 {
452 reg = <0x8d8 2>;
453 bits = <5 5>;
454 };
455
456 comb_intr_p0: usb3-intr@8d9 {
457 reg = <0x8d9 1>;
458 bits = <2 6>;
459 };
460
461 u2_auto_load_valid_p0: usb2-alv-p0@8e0 {
462 reg = <0x8e0 1>;
463 bits = <0 1>;
464 };
465
466 u2_intr_p0: usb2-intr-p0@8e0 {
467 reg = <0x8e0 1>;
468 bits = <1 5>;
469 };
470
471 u2_auto_load_valid_p1: usb2-alv-p1@8e0 {
472 reg = <0x8e0 2>;
473 bits = <6 1>;
474 };
475
476 u2_intr_p1: usb2-intr-p1@8e0 {
477 reg = <0x8e0 2>;
478 bits = <7 5>;
479 };
480
481 pcie_rx_imp_ln0: pcie-rx-imp@8d0 {
482 reg = <0x8d0 1>;
483 bits = <0 5>;
484 };
485
486 pcie_tx_imp_ln0: pcie-tx-imp@8d0 {
487 reg = <0x8d0 2>;
488 bits = <5 5>;
489 };
490
491 pcie_intr_ln0: pcie-intr@8d1 {
492 reg = <0x8d1 1>;
493 bits = <2 6>;
494 };
495
496 pcie_auto_load_valid_ln0: pcie-ln0-alv@8d4 {
497 reg = <0x8d4 1>;
498 bits = <0 1>;
499 };
500
501 pcie_rx_imp_ln1: pcie-rx-imp@8d2 {
502 reg = <0x8d2 1>;
503 bits = <0 5>;
504 };
505
506 pcie_tx_imp_ln1: pcie-tx-imp@8d2 {
507 reg = <0x8d2 2>;
508 bits = <5 5>;
509 };
510
511 pcie_intr_ln1: pcie-intr@8d3 {
512 reg = <0x8d3 1>;
513 bits = <2 6>;
514 };
515
516 pcie_auto_load_valid_ln1: pcie-ln1-alv@8d4 {
517 reg = <0x8d4 1>;
518 bits = <1 1>;
519 };
520 };
521
522 usb_phy: t-phy@11e10000 {
523 compatible = "mediatek,mt7986-tphy",
524 "mediatek,generic-tphy-v2";
525 #address-cells = <2>;
526 #size-cells = <2>;
527 ranges;
528 status = "disabled";
529
530 u2port0: usb-phy@11e10000 {
531 reg = <0 0x11e10000 0 0x700>;
532 clocks = <&topckgen CLK_TOP_DA_U2_REFSEL>,
533 <&topckgen CLK_TOP_DA_U2_CK_1P_SEL>;
534 clock-names = "ref", "da_ref";
535 #phy-cells = <1>;
536 auto_load_valid;
537 nvmem-cells = <&u2_intr_p0>, <&u2_auto_load_valid_p0>;
538 nvmem-cell-names = "intr", "auto_load_valid";
539 };
540
541 u3port0: usb-phy@11e10700 {
542 reg = <0 0x11e10700 0 0x900>;
543 clocks = <&topckgen CLK_TOP_USB3_PHY_SEL>;
544 clock-names = "ref";
545 #phy-cells = <1>;
546 auto_load_valid;
547 nvmem-cells = <&comb_intr_p0>,
548 <&comb_rx_imp_p0>,
549 <&comb_tx_imp_p0>,
550 <&comb_auto_load_valid>;
551 nvmem-cell-names = "intr", "rx_imp", "tx_imp", "auto_load_valid";
552 };
553
554 u2port1: usb-phy@11e11000 {
555 reg = <0 0x11e11000 0 0x700>;
556 clocks = <&topckgen CLK_TOP_DA_U2_REFSEL>,
557 <&topckgen CLK_TOP_DA_U2_CK_1P_SEL>;
558 clock-names = "ref", "da_ref";
559 #phy-cells = <1>;
560 auto_load_valid;
561 nvmem-cells = <&u2_intr_p1>, <&u2_auto_load_valid_p1>;
562 nvmem-cell-names = "intr", "auto_load_valid";
563 };
564 };
565
566 ethsys: syscon@15000000 {
567 #address-cells = <1>;
568 #size-cells = <1>;
569 compatible = "mediatek,mt7986-ethsys_ck",
570 "syscon";
571 reg = <0 0x15000000 0 0x1000>;
572 #clock-cells = <1>;
573 #reset-cells = <1>;
574 };
575
576 wed_pcie: wed-pcie@10003000 {
577 compatible = "mediatek,mt7986-wed-pcie",
578 "syscon";
579 reg = <0 0x10003000 0 0x10>;
580 };
581
582 wed0: wed@15010000 {
583 compatible = "mediatek,mt7986-wed",
584 "syscon";
585 reg = <0 0x15010000 0 0x1000>;
586 interrupt-parent = <&gic>;
587 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
588 };
589
590 wed1: wed@15011000 {
591 compatible = "mediatek,mt7986-wed",
592 "syscon";
593 reg = <0 0x15011000 0 0x1000>;
594 interrupt-parent = <&gic>;
595 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
596 };
597
598 eth: ethernet@15100000 {
599 compatible = "mediatek,mt7986-eth";
600 reg = <0 0x15100000 0 0x80000>;
601 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
602 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
603 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
604 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
605 clocks = <&ethsys CLK_ETH_FE_EN>,
606 <&ethsys CLK_ETH_GP2_EN>,
607 <&ethsys CLK_ETH_GP1_EN>,
608 <&ethsys CLK_ETH_WOCPU1_EN>,
609 <&ethsys CLK_ETH_WOCPU0_EN>,
610 <&sgmiisys0 CLK_SGMII0_TX250M_EN>,
611 <&sgmiisys0 CLK_SGMII0_RX250M_EN>,
612 <&sgmiisys0 CLK_SGMII0_CDR_REF>,
613 <&sgmiisys0 CLK_SGMII0_CDR_FB>,
614 <&sgmiisys1 CLK_SGMII1_TX250M_EN>,
615 <&sgmiisys1 CLK_SGMII1_RX250M_EN>,
616 <&sgmiisys1 CLK_SGMII1_CDR_REF>,
617 <&sgmiisys1 CLK_SGMII1_CDR_FB>,
618 <&topckgen CLK_TOP_NETSYS_SEL>,
619 <&topckgen CLK_TOP_NETSYS_500M_SEL>;
620 clock-names = "fe", "gp2", "gp1", "wocpu1", "wocpu0",
621 "sgmii_tx250m", "sgmii_rx250m",
622 "sgmii_cdr_ref", "sgmii_cdr_fb",
623 "sgmii2_tx250m", "sgmii2_rx250m",
624 "sgmii2_cdr_ref", "sgmii2_cdr_fb",
625 "netsys0", "netsys1";
626 assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
627 <&topckgen CLK_TOP_SGM_325M_SEL>;
628 assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>,
629 <&apmixedsys CLK_APMIXED_SGMPLL>;
630 mediatek,ethsys = <&ethsys>;
631 mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
632 mediatek,wed-pcie = <&wed_pcie>;
633 mediatek,wed = <&wed0>, <&wed1>;
634 #reset-cells = <1>;
635 #address-cells = <1>;
636 #size-cells = <0>;
637 status = "disabled";
638 };
639
640 consys: consys@10000000 {
641 compatible = "mediatek,mt7986-consys";
642 reg = <0 0x10000000 0 0x8600000>;
643 memory-region = <&wmcpu_emi>;
644 };
645
646 wmac: wmac@18000000 {
647 compatible = "mediatek,mt7986-wmac", "mediatek,wbsys";
648 resets = <&watchdog MT7986_TOPRGU_CONSYS_RST>;
649 reset-names = "consys";
650 reg = <0 0x18000000 0 0x1000000>,
651 <0 0x10003000 0 0x1000>,
652 <0 0x11d10000 0 0x1000>;
653 interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
654 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
655 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
656 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
657 clocks = <&topckgen CLK_TOP_CONN_MCUSYS_SEL>,
658 <&topckgen CLK_TOP_AP2CNN_HOST_SEL>;
659 clock-names = "mcu", "ap2conn";
660 memory-region = <&wmcpu_emi>;
661 status = "disabled";
662 };
663 };
664
665 fan: pwm-fan {
666 compatible = "pwm-fan";
667 /* cooling level (0, 1, 2, 3) : (0% duty, 33% duty, 66% duty, 100% duty) */
668 cooling-levels = <0 86 172 255>;
669 #cooling-cells = <2>;
670 status = "disabled";
671 };
672
673 thermal-zones {
674 cpu_thermal: cpu-thermal {
675 polling-delay-passive = <1000>;
676 polling-delay = <1000>;
677 thermal-sensors = <&thermal 0>;
678 trips {
679 cpu_trip_crit: crit {
680 temperature = <125000>;
681 hysteresis = <2000>;
682 type = "critical";
683 };
684
685 cpu_trip_hot: hot {
686 temperature = <120000>;
687 hysteresis = <2000>;
688 type = "hot";
689 };
690
691 cpu_trip_active_high: active-high {
692 temperature = <115000>;
693 hysteresis = <2000>;
694 type = "active";
695 };
696
697 cpu_trip_active_med: active-med {
698 temperature = <85000>;
699 hysteresis = <2000>;
700 type = "active";
701 };
702
703 cpu_trip_active_low: active-low {
704 temperature = <60000>;
705 hysteresis = <2000>;
706 type = "passive";
707 };
708 };
709
710 cooling-maps {
711 cpu-active-high {
712 /* active: set fan to cooling level 3 */
713 cooling-device = <&fan 3 3>;
714 trip = <&cpu_trip_active_high>;
715 };
716
717 cpu-active-med {
718 /* active: set fan to cooling level 2 */
719 cooling-device = <&fan 2 2>;
720 trip = <&cpu_trip_active_med>;
721 };
722
723 cpu-active-low {
724 /* passive: set fan to cooling level 1 */
725 cooling-device = <&fan 1 1>;
726 trip = <&cpu_trip_active_low>;
727 };
728 };
729 };
730 };
731 };
OpenWrt Source Repository