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[openwrt/openwrt.git] / target / linux / mediatek / patches-4.14 / 0186-ASoC-mediatek-update-MT2701-AFE-documentation-to-ada.patch
1 From 018219d340c0f7a10098683b8a4733618ea76ba3 Mon Sep 17 00:00:00 2001
2 From: Ryder Lee <ryder.lee@mediatek.com>
3 Date: Thu, 4 Jan 2018 15:44:09 +0800
4 Subject: [PATCH 186/224] ASoC: mediatek: update MT2701 AFE documentation to
5 adapt mfd device
6
7 As the new MFD parent is in place, modify MT2701 AFE documentation to
8 adapt it. Also add three core clocks in example.
9
10 Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
11 Signed-off-by: Mark Brown <broonie@kernel.org>
12 ---
13 .../devicetree/bindings/sound/mt2701-afe-pcm.txt | 171 +++++++++++----------
14 1 file changed, 93 insertions(+), 78 deletions(-)
15
16 diff --git a/Documentation/devicetree/bindings/sound/mt2701-afe-pcm.txt b/Documentation/devicetree/bindings/sound/mt2701-afe-pcm.txt
17 index 0450baad2813..6df87b97f7cb 100644
18 --- a/Documentation/devicetree/bindings/sound/mt2701-afe-pcm.txt
19 +++ b/Documentation/devicetree/bindings/sound/mt2701-afe-pcm.txt
20 @@ -2,15 +2,17 @@ Mediatek AFE PCM controller for mt2701
21
22 Required properties:
23 - compatible = "mediatek,mt2701-audio";
24 -- reg: register location and size
25 - interrupts: should contain AFE and ASYS interrupts
26 - interrupt-names: should be "afe" and "asys"
27 - power-domains: should define the power domain
28 - clocks: Must contain an entry for each entry in clock-names
29 See ../clocks/clock-bindings.txt for details
30 - clock-names: should have these clock names:
31 + "infra_sys_audio_clk",
32 "top_audio_mux1_sel",
33 "top_audio_mux2_sel",
34 + "top_audio_a1sys_hp",
35 + "top_audio_a2sys_hp",
36 "i2s0_src_sel",
37 "i2s1_src_sel",
38 "i2s2_src_sel",
39 @@ -45,85 +47,98 @@ Required properties:
40 - assigned-clocks-parents: parent of input clocks of assigned clocks.
41 - assigned-clock-rates: list of clock frequencies of assigned clocks.
42
43 +Must be a subnode of MediaTek audsys device tree node.
44 +See ../arm/mediatek/mediatek,audsys.txt for details about the parent node.
45 +
46 Example:
47
48 - afe: mt2701-afe-pcm@11220000 {
49 - compatible = "mediatek,mt2701-audio";
50 - reg = <0 0x11220000 0 0x2000>,
51 - <0 0x112A0000 0 0x20000>;
52 - interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
53 - <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
54 - interrupt-names = "afe", "asys";
55 - power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
56 - clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>,
57 - <&topckgen CLK_TOP_AUD_MUX2_SEL>,
58 - <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
59 - <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
60 - <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
61 - <&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
62 - <&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
63 - <&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
64 - <&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
65 - <&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
66 - <&topckgen CLK_TOP_AUD_I2S1_MCLK>,
67 - <&topckgen CLK_TOP_AUD_I2S2_MCLK>,
68 - <&topckgen CLK_TOP_AUD_I2S3_MCLK>,
69 - <&topckgen CLK_TOP_AUD_I2S4_MCLK>,
70 - <&audiosys CLK_AUD_I2SO1>,
71 - <&audiosys CLK_AUD_I2SO2>,
72 - <&audiosys CLK_AUD_I2SO3>,
73 - <&audiosys CLK_AUD_I2SO4>,
74 - <&audiosys CLK_AUD_I2SIN1>,
75 - <&audiosys CLK_AUD_I2SIN2>,
76 - <&audiosys CLK_AUD_I2SIN3>,
77 - <&audiosys CLK_AUD_I2SIN4>,
78 - <&audiosys CLK_AUD_ASRCO1>,
79 - <&audiosys CLK_AUD_ASRCO2>,
80 - <&audiosys CLK_AUD_ASRCO3>,
81 - <&audiosys CLK_AUD_ASRCO4>,
82 - <&audiosys CLK_AUD_AFE>,
83 - <&audiosys CLK_AUD_AFE_CONN>,
84 - <&audiosys CLK_AUD_A1SYS>,
85 - <&audiosys CLK_AUD_A2SYS>,
86 - <&audiosys CLK_AUD_AFE_MRGIF>;
87 + audsys: audio-subsystem@11220000 {
88 + compatible = "mediatek,mt2701-audsys", "syscon", "simple-mfd";
89 + ...
90 +
91 + afe: audio-controller {
92 + compatible = "mediatek,mt2701-audio";
93 + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
94 + <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
95 + interrupt-names = "afe", "asys";
96 + power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
97 +
98 + clocks = <&infracfg CLK_INFRA_AUDIO>,
99 + <&topckgen CLK_TOP_AUD_MUX1_SEL>,
100 + <&topckgen CLK_TOP_AUD_MUX2_SEL>,
101 + <&topckgen CLK_TOP_AUD_48K_TIMING>,
102 + <&topckgen CLK_TOP_AUD_44K_TIMING>,
103 + <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
104 + <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
105 + <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
106 + <&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
107 + <&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
108 + <&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
109 + <&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
110 + <&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
111 + <&topckgen CLK_TOP_AUD_I2S1_MCLK>,
112 + <&topckgen CLK_TOP_AUD_I2S2_MCLK>,
113 + <&topckgen CLK_TOP_AUD_I2S3_MCLK>,
114 + <&topckgen CLK_TOP_AUD_I2S4_MCLK>,
115 + <&audsys CLK_AUD_I2SO1>,
116 + <&audsys CLK_AUD_I2SO2>,
117 + <&audsys CLK_AUD_I2SO3>,
118 + <&audsys CLK_AUD_I2SO4>,
119 + <&audsys CLK_AUD_I2SIN1>,
120 + <&audsys CLK_AUD_I2SIN2>,
121 + <&audsys CLK_AUD_I2SIN3>,
122 + <&audsys CLK_AUD_I2SIN4>,
123 + <&audsys CLK_AUD_ASRCO1>,
124 + <&audsys CLK_AUD_ASRCO2>,
125 + <&audsys CLK_AUD_ASRCO3>,
126 + <&audsys CLK_AUD_ASRCO4>,
127 + <&audsys CLK_AUD_AFE>,
128 + <&audsys CLK_AUD_AFE_CONN>,
129 + <&audsys CLK_AUD_A1SYS>,
130 + <&audsys CLK_AUD_A2SYS>,
131 + <&audsys CLK_AUD_AFE_MRGIF>;
132
133 - clock-names = "top_audio_mux1_sel",
134 - "top_audio_mux2_sel",
135 - "i2s0_src_sel",
136 - "i2s1_src_sel",
137 - "i2s2_src_sel",
138 - "i2s3_src_sel",
139 - "i2s0_src_div",
140 - "i2s1_src_div",
141 - "i2s2_src_div",
142 - "i2s3_src_div",
143 - "i2s0_mclk_en",
144 - "i2s1_mclk_en",
145 - "i2s2_mclk_en",
146 - "i2s3_mclk_en",
147 - "i2so0_hop_ck",
148 - "i2so1_hop_ck",
149 - "i2so2_hop_ck",
150 - "i2so3_hop_ck",
151 - "i2si0_hop_ck",
152 - "i2si1_hop_ck",
153 - "i2si2_hop_ck",
154 - "i2si3_hop_ck",
155 - "asrc0_out_ck",
156 - "asrc1_out_ck",
157 - "asrc2_out_ck",
158 - "asrc3_out_ck",
159 - "audio_afe_pd",
160 - "audio_afe_conn_pd",
161 - "audio_a1sys_pd",
162 - "audio_a2sys_pd",
163 - "audio_mrgif_pd";
164 + clock-names = "infra_sys_audio_clk",
165 + "top_audio_mux1_sel",
166 + "top_audio_mux2_sel",
167 + "top_audio_a1sys_hp",
168 + "top_audio_a2sys_hp",
169 + "i2s0_src_sel",
170 + "i2s1_src_sel",
171 + "i2s2_src_sel",
172 + "i2s3_src_sel",
173 + "i2s0_src_div",
174 + "i2s1_src_div",
175 + "i2s2_src_div",
176 + "i2s3_src_div",
177 + "i2s0_mclk_en",
178 + "i2s1_mclk_en",
179 + "i2s2_mclk_en",
180 + "i2s3_mclk_en",
181 + "i2so0_hop_ck",
182 + "i2so1_hop_ck",
183 + "i2so2_hop_ck",
184 + "i2so3_hop_ck",
185 + "i2si0_hop_ck",
186 + "i2si1_hop_ck",
187 + "i2si2_hop_ck",
188 + "i2si3_hop_ck",
189 + "asrc0_out_ck",
190 + "asrc1_out_ck",
191 + "asrc2_out_ck",
192 + "asrc3_out_ck",
193 + "audio_afe_pd",
194 + "audio_afe_conn_pd",
195 + "audio_a1sys_pd",
196 + "audio_a2sys_pd",
197 + "audio_mrgif_pd";
198
199 - assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>,
200 - <&topckgen CLK_TOP_AUD_MUX2_SEL>,
201 - <&topckgen CLK_TOP_AUD_MUX1_DIV>,
202 - <&topckgen CLK_TOP_AUD_MUX2_DIV>;
203 - assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>,
204 - <&topckgen CLK_TOP_AUD2PLL_90M>;
205 - assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
206 + assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>,
207 + <&topckgen CLK_TOP_AUD_MUX2_SEL>,
208 + <&topckgen CLK_TOP_AUD_MUX1_DIV>,
209 + <&topckgen CLK_TOP_AUD_MUX2_DIV>;
210 + assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>,
211 + <&topckgen CLK_TOP_AUD2PLL_90M>;
212 + assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
213 + };
214 };
215 --
216 2.11.0
217
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