target/linux/mediatek/patches-4.14/0201-dt-bindings-clock-mediatek-add-missing-required-rese.patch

   1 From 4a1990ee249df257848f9583cef71478e3411c3e Mon Sep 17 00:00:00 2001
   2 From: Sean Wang <sean.wang@mediatek.com>
   3 Date: Thu, 28 Dec 2017 11:24:45 +0800
   4 Subject: [PATCH 201/224] dt-bindings: clock: mediatek: add missing required
   5  #reset-cells
   6
   7 All ethsys, pciesys and ssusbsys internally include reset controller, so
   8 explicitly add back these missing cell definitions to related bindings
   9 and examples.
  10
  11 Signed-off-by: Sean Wang <sean.wang@mediatek.com>
  12 Cc: Rob Herring <robh@kernel.org>
  13 Cc: Michael Turquette <mturquette@baylibre.com>
  14 Cc: Stephen Boyd <sboyd@codeaurora.org>
  15 Cc: linux-clk@vger.kernel.org
  16 Reviewed-by: Rob Herring <robh@kernel.org>
  17 ---
  18  Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt   | 1 +
  19  Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt  | 2 ++
  20  Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt | 2 ++
  21  3 files changed, 5 insertions(+)
  22
  23 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
  24 +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
  25 @@ -9,6 +9,7 @@ Required Properties:
  26         - "mediatek,mt2701-ethsys", "syscon"
  27         - "mediatek,mt7622-ethsys", "syscon"
  28  - #clock-cells: Must be 1
  29 +- #reset-cells: Must be 1
  30
  31  The ethsys controller uses the common clk binding from
  32  Documentation/devicetree/bindings/clock/clock-bindings.txt
  33 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt
  34 +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt
  35 @@ -8,6 +8,7 @@ Required Properties:
  36  - compatible: Should be:
  37         - "mediatek,mt7622-pciesys", "syscon"
  38  - #clock-cells: Must be 1
  39 +- #reset-cells: Must be 1
  40
  41  The PCIESYS controller uses the common clk binding from
  42  Documentation/devicetree/bindings/clock/clock-bindings.txt
  43 @@ -19,4 +20,5 @@ pciesys: pciesys@1a100800 {
  44         compatible = "mediatek,mt7622-pciesys", "syscon";
  45         reg = <0 0x1a100800 0 0x1000>;
  46         #clock-cells = <1>;
  47 +       #reset-cells = <1>;
  48  };
  49 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt
  50 +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt
  51 @@ -8,6 +8,7 @@ Required Properties:
  52  - compatible: Should be:
  53         - "mediatek,mt7622-ssusbsys", "syscon"
  54  - #clock-cells: Must be 1
  55 +- #reset-cells: Must be 1
  56
  57  The SSUSBSYS controller uses the common clk binding from
  58  Documentation/devicetree/bindings/clock/clock-bindings.txt
  59 @@ -19,4 +20,5 @@ ssusbsys: ssusbsys@1a000000 {
  60         compatible = "mediatek,mt7622-ssusbsys", "syscon";
  61         reg = <0 0x1a000000 0 0x1000>;
  62         #clock-cells = <1>;
  63 +       #reset-cells = <1>;
  64  };