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[openwrt/openwrt.git] / target / linux / mediatek / patches-4.4 / 0023-ARM-dts-mediatek-add-MT7623-basic-support.patch
1 From a4df3e7e4e906a4e9dac1f8c43f6192f22ef6242 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Tue, 5 Jan 2016 12:16:17 +0100
4 Subject: [PATCH 23/81] ARM: dts: mediatek: add MT7623 basic support
5
6 This adds basic chip support for Mediatek MT7623.
7
8 Signed-off-by: John Crispin <blogic@openwrt.org>
9 ---
10 arch/arm/boot/dts/Makefile | 1 +
11 arch/arm/boot/dts/mt7623-evb.dts | 459 +++++++++++++++++++++++++++++++++
12 arch/arm/boot/dts/mt7623.dtsi | 510 +++++++++++++++++++++++++++++++++++++
13 arch/arm/mach-mediatek/Kconfig | 4 +
14 arch/arm/mach-mediatek/mediatek.c | 1 +
15 5 files changed, 975 insertions(+)
16 create mode 100644 arch/arm/boot/dts/mt7623-evb.dts
17 create mode 100644 arch/arm/boot/dts/mt7623.dtsi
18
19 --- a/arch/arm/boot/dts/Makefile
20 +++ b/arch/arm/boot/dts/Makefile
21 @@ -774,6 +774,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
22 mt6580-evbp1.dtb \
23 mt6589-aquaris5.dtb \
24 mt6592-evb.dtb \
25 + mt7623-evb.dtb \
26 mt8127-moose.dtb \
27 mt8135-evbp1.dtb
28 dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb
29 --- /dev/null
30 +++ b/arch/arm/boot/dts/mt7623-evb.dts
31 @@ -0,0 +1,459 @@
32 +/*
33 + * Copyright (c) 2016 MediaTek Inc.
34 + * Author: John Crispin <blogic@openwrt.org>
35 + *
36 + * This program is free software; you can redistribute it and/or modify
37 + * it under the terms of the GNU General Public License version 2 as
38 + * published by the Free Software Foundation.
39 + *
40 + * This program is distributed in the hope that it will be useful,
41 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
42 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
43 + * GNU General Public License for more details.
44 + */
45 +
46 +/dts-v1/;
47 +
48 +#include "mt7623.dtsi"
49 +#include <dt-bindings/gpio/gpio.h>
50 +
51 +/ {
52 + model = "MediaTek MT7623 evaluation board";
53 + compatible = "mediatek,mt7623-evb", "mediatek,mt7623";
54 +
55 + chosen {
56 + stdout-path = &uart2;
57 + };
58 +
59 + memory {
60 + reg = <0 0x80000000 0 0x20000000>;
61 + };
62 +
63 + usb_p1_vbus: regulator@0 {
64 + compatible = "regulator-fixed";
65 + regulator-name = "usb_vbus";
66 + regulator-min-microvolt = <5000000>;
67 + regulator-max-microvolt = <5000000>;
68 + gpio = <&pio 135 GPIO_ACTIVE_HIGH>;
69 + enable-active-high;
70 + };
71 +};
72 +
73 +&pwrap {
74 + pmic: mt6323 {
75 + compatible = "mediatek,mt6323";
76 + interrupt-parent = <&pio>;
77 + interrupts = <150 IRQ_TYPE_LEVEL_HIGH>;
78 + interrupt-controller;
79 + #interrupt-cells = <2>;
80 +
81 + mt6323regulator: mt6323regulator{
82 + compatible = "mediatek,mt6323-regulator";
83 +
84 + mt6323_vproc_reg: buck_vproc{
85 + regulator-name = "vproc";
86 + regulator-min-microvolt = < 700000>;
87 + regulator-max-microvolt = <1350000>;
88 + regulator-ramp-delay = <12500>;
89 + regulator-always-on;
90 + regulator-boot-on;
91 + };
92 +
93 + mt6323_vsys_reg: buck_vsys{
94 + regulator-name = "vsys";
95 + regulator-min-microvolt = <1400000>;
96 + regulator-max-microvolt = <2987500>;
97 + regulator-ramp-delay = <25000>;
98 + regulator-always-on;
99 + regulator-boot-on;
100 + };
101 +
102 + mt6323_vpa_reg: buck_vpa{
103 + regulator-name = "vpa";
104 + regulator-min-microvolt = < 500000>;
105 + regulator-max-microvolt = <3650000>;
106 + };
107 +
108 + mt6323_vtcxo_reg: ldo_vtcxo{
109 + regulator-name = "vtcxo";
110 + regulator-min-microvolt = <2800000>;
111 + regulator-max-microvolt = <2800000>;
112 + regulator-enable-ramp-delay = <90>;
113 + regulator-always-on;
114 + regulator-boot-on;
115 + };
116 +
117 + mt6323_vcn28_reg: ldo_vcn28{
118 + regulator-name = "vcn28";
119 + regulator-min-microvolt = <2800000>;
120 + regulator-max-microvolt = <2800000>;
121 + regulator-enable-ramp-delay = <185>;
122 + };
123 +
124 + mt6323_vcn33_bt_reg: ldo_vcn33_bt{
125 + regulator-name = "vcn33_bt";
126 + regulator-min-microvolt = <3300000>;
127 + regulator-max-microvolt = <3600000>;
128 + regulator-enable-ramp-delay = <185>;
129 + };
130 +
131 + mt6323_vcn33_wifi_reg: ldo_vcn33_wifi{
132 + regulator-name = "vcn33_wifi";
133 + regulator-min-microvolt = <3300000>;
134 + regulator-max-microvolt = <3600000>;
135 + regulator-enable-ramp-delay = <185>;
136 + };
137 +
138 + mt6323_va_reg: ldo_va{
139 + regulator-name = "va";
140 + regulator-min-microvolt = <2800000>;
141 + regulator-max-microvolt = <2800000>;
142 + regulator-enable-ramp-delay = <216>;
143 + regulator-always-on;
144 + regulator-boot-on;
145 + };
146 +
147 + mt6323_vcama_reg: ldo_vcama{
148 + regulator-name = "vcama";
149 + regulator-min-microvolt = <1500000>;
150 + regulator-max-microvolt = <2800000>;
151 + regulator-enable-ramp-delay = <216>;
152 + };
153 +
154 + mt6323_vio28_reg: ldo_vio28{
155 + regulator-name = "vio28";
156 + regulator-min-microvolt = <2800000>;
157 + regulator-max-microvolt = <2800000>;
158 + regulator-enable-ramp-delay = <216>;
159 + regulator-always-on;
160 + regulator-boot-on;
161 + };
162 +
163 + mt6323_vusb_reg: ldo_vusb{
164 + regulator-name = "vusb";
165 + regulator-min-microvolt = <3300000>;
166 + regulator-max-microvolt = <3300000>;
167 + regulator-enable-ramp-delay = <216>;
168 + regulator-boot-on;
169 + };
170 +
171 + mt6323_vmc_reg: ldo_vmc{
172 + regulator-name = "vmc";
173 + regulator-min-microvolt = <1800000>;
174 + regulator-max-microvolt = <3300000>;
175 + regulator-enable-ramp-delay = <36>;
176 + regulator-boot-on;
177 + };
178 +
179 + mt6323_vmch_reg: ldo_vmch{
180 + regulator-name = "vmch";
181 + regulator-min-microvolt = <3000000>;
182 + regulator-max-microvolt = <3300000>;
183 + regulator-enable-ramp-delay = <36>;
184 + regulator-boot-on;
185 + };
186 +
187 + mt6323_vemc3v3_reg: ldo_vemc3v3{
188 + regulator-name = "vemc3v3";
189 + regulator-min-microvolt = <3000000>;
190 + regulator-max-microvolt = <3300000>;
191 + regulator-enable-ramp-delay = <36>;
192 + regulator-boot-on;
193 + };
194 +
195 + mt6323_vgp1_reg: ldo_vgp1{
196 + regulator-name = "vgp1";
197 + regulator-min-microvolt = <1200000>;
198 + regulator-max-microvolt = <3300000>;
199 + regulator-enable-ramp-delay = <216>;
200 + };
201 +
202 + mt6323_vgp2_reg: ldo_vgp2{
203 + regulator-name = "vgp2";
204 + regulator-min-microvolt = <1200000>;
205 + regulator-max-microvolt = <3000000>;
206 + regulator-enable-ramp-delay = <216>;
207 + };
208 +
209 + mt6323_vgp3_reg: ldo_vgp3{
210 + regulator-name = "vgp3";
211 + regulator-min-microvolt = <1200000>;
212 + regulator-max-microvolt = <1800000>;
213 + regulator-enable-ramp-delay = <216>;
214 + };
215 +
216 + mt6323_vcn18_reg: ldo_vcn18{
217 + regulator-name = "vcn18";
218 + regulator-min-microvolt = <1800000>;
219 + regulator-max-microvolt = <1800000>;
220 + regulator-enable-ramp-delay = <216>;
221 + };
222 +
223 + mt6323_vsim1_reg: ldo_vsim1{
224 + regulator-name = "vsim1";
225 + regulator-min-microvolt = <1800000>;
226 + regulator-max-microvolt = <3000000>;
227 + regulator-enable-ramp-delay = <216>;
228 + };
229 +
230 + mt6323_vsim2_reg: ldo_vsim2{
231 + regulator-name = "vsim2";
232 + regulator-min-microvolt = <1800000>;
233 + regulator-max-microvolt = <3000000>;
234 + regulator-enable-ramp-delay = <216>;
235 + };
236 +
237 + mt6323_vrtc_reg: ldo_vrtc{
238 + regulator-name = "vrtc";
239 + regulator-min-microvolt = <2800000>;
240 + regulator-max-microvolt = <2800000>;
241 + regulator-always-on;
242 + regulator-boot-on;
243 + };
244 +
245 + mt6323_vcamaf_reg: ldo_vcamaf{
246 + regulator-name = "vcamaf";
247 + regulator-min-microvolt = <1200000>;
248 + regulator-max-microvolt = <3300000>;
249 + regulator-enable-ramp-delay = <216>;
250 + };
251 +
252 + mt6323_vibr_reg: ldo_vibr{
253 + regulator-name = "vibr";
254 + regulator-min-microvolt = <1200000>;
255 + regulator-max-microvolt = <3300000>;
256 + regulator-enable-ramp-delay = <36>;
257 + };
258 +
259 + mt6323_vrf18_reg: ldo_vrf18{
260 + regulator-name = "vrf18";
261 + regulator-min-microvolt = <1825000>;
262 + regulator-max-microvolt = <1825000>;
263 + regulator-enable-ramp-delay = <187>;
264 + };
265 +
266 + mt6323_vm_reg: ldo_vm{
267 + regulator-name = "vm";
268 + regulator-min-microvolt = <1200000>;
269 + regulator-max-microvolt = <1800000>;
270 + regulator-enable-ramp-delay = <216>;
271 + regulator-always-on;
272 + regulator-boot-on;
273 + };
274 +
275 + mt6323_vio18_reg: ldo_vio18{
276 + regulator-name = "vio18";
277 + regulator-min-microvolt = <1800000>;
278 + regulator-max-microvolt = <1800000>;
279 + regulator-enable-ramp-delay = <216>;
280 + regulator-always-on;
281 + regulator-boot-on;
282 + };
283 +
284 + mt6323_vcamd_reg: ldo_vcamd{
285 + regulator-name = "vcamd";
286 + regulator-min-microvolt = <1200000>;
287 + regulator-max-microvolt = <1800000>;
288 + regulator-enable-ramp-delay = <216>;
289 + };
290 +
291 + mt6323_vcamio_reg: ldo_vcamio{
292 + regulator-name = "vcamio";
293 + regulator-min-microvolt = <1800000>;
294 + regulator-max-microvolt = <1800000>;
295 + regulator-enable-ramp-delay = <216>;
296 + };
297 + };
298 + };
299 +};
300 +
301 +&uart2 {
302 + status = "okay";
303 +};
304 +
305 +&mmc0 {
306 + status = "okay";
307 + pinctrl-names = "default", "state_uhs";
308 + pinctrl-0 = <&mmc0_pins_default>;
309 + pinctrl-1 = <&mmc0_pins_uhs>;
310 + bus-width = <8>;
311 + max-frequency = <50000000>;
312 + cap-mmc-highspeed;
313 + vmmc-supply = <&mt6323_vemc3v3_reg>;
314 + vqmmc-supply = <&mt6323_vio18_reg>;
315 + non-removable;
316 +};
317 +
318 +&mmc1 {
319 + status = "okay";
320 + pinctrl-names = "default", "state_uhs";
321 + pinctrl-0 = <&mmc1_pins_default>;
322 + pinctrl-1 = <&mmc1_pins_uhs>;
323 + bus-width = <4>;
324 + max-frequency = <50000000>;
325 + cap-sd-highspeed;
326 + sd-uhs-sdr25;
327 +// cd-gpios = <&pio 132 0>;
328 + vmmc-supply = <&mt6323_vmch_reg>;
329 + vqmmc-supply = <&mt6323_vmc_reg>;
330 +};
331 +
332 +&pio {
333 + mmc0_pins_default: mmc0default {
334 + pins_cmd_dat {
335 + pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
336 + <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
337 + <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
338 + <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>,
339 + <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>,
340 + <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>,
341 + <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>,
342 + <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>,
343 + <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>;
344 + input-enable;
345 + bias-pull-up;
346 + };
347 +
348 + pins_clk {
349 + pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
350 + bias-pull-down;
351 + };
352 +
353 + pins_rst {
354 + pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
355 + bias-pull-up;
356 + };
357 + };
358 +
359 + mmc0_pins_uhs: mmc0 {
360 + pins_cmd_dat {
361 + pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
362 + <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
363 + <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
364 + <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>,
365 + <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>,
366 + <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>,
367 + <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>,
368 + <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>,
369 + <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>;
370 + input-enable;
371 + drive-strength = <MTK_DRIVE_2mA>;
372 + bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
373 + };
374 +
375 + pins_clk {
376 + pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
377 + drive-strength = <MTK_DRIVE_2mA>;
378 + bias-pull-down = <MTK_PUPD_SET_R1R0_01>;
379 + };
380 +
381 + pins_rst {
382 + pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
383 + bias-pull-up;
384 + };
385 + };
386 +
387 + mmc1_pins_default: mmc1default {
388 + pins_cmd_dat {
389 + pinmux = <MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0>,
390 + <MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1>,
391 + <MT7623_PIN_109_MSDC1_DAT2_FUNC_MSDC1_DAT2>,
392 + <MT7623_PIN_110_MSDC1_DAT3_FUNC_MSDC1_DAT3>,
393 + <MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD>;
394 + input-enable;
395 + drive-strength = <MTK_DRIVE_4mA>;
396 + bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
397 + };
398 +
399 + pins_clk {
400 + pinmux = <MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK>;
401 + bias-pull-down;
402 + drive-strength = <MTK_DRIVE_4mA>;
403 + };
404 +
405 +// pins_insert {
406 +// pinmux = <MT8173_PIN_132_I2S0_DATA1_FUNC_GPIO132>;
407 +// bias-pull-up;
408 +// };
409 + };
410 +
411 + mmc1_pins_uhs: mmc1 {
412 + pins_cmd_dat {
413 + pinmux = <MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0>,
414 + <MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1>,
415 + <MT7623_PIN_109_MSDC1_DAT2_FUNC_MSDC1_DAT2>,
416 + <MT7623_PIN_110_MSDC1_DAT3_FUNC_MSDC1_DAT3>,
417 + <MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD>;
418 + input-enable;
419 + drive-strength = <MTK_DRIVE_4mA>;
420 + bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
421 + };
422 +
423 + pins_clk {
424 + pinmux = <MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK>;
425 + drive-strength = <MTK_DRIVE_4mA>;
426 + bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
427 + };
428 + };
429 +
430 + eth_default: eth {
431 + pins_eth {
432 + pinmux = <MT7623_PIN_275_G2_MDC_FUNC_MDC>,
433 + <MT7623_PIN_276_G2_MDIO_FUNC_MDIO>,
434 + <MT7623_PIN_262_G2_TXEN_FUNC_G2_TXEN>,
435 + <MT7623_PIN_263_G2_TXD3_FUNC_G2_TXD3>,
436 + <MT7623_PIN_264_G2_TXD2_FUNC_G2_TXD2>,
437 + <MT7623_PIN_265_G2_TXD1_FUNC_G2_TXD1>,
438 + <MT7623_PIN_266_G2_TXD0_FUNC_G2_TXD0>,
439 + <MT7623_PIN_267_G2_TXCLK_FUNC_G2_TXC>,
440 + <MT7623_PIN_268_G2_RXCLK_FUNC_G2_RXC>,
441 + <MT7623_PIN_269_G2_RXD0_FUNC_G2_RXD0>,
442 + <MT7623_PIN_270_G2_RXD1_FUNC_G2_RXD1>,
443 + <MT7623_PIN_271_G2_RXD2_FUNC_G2_RXD2>,
444 + <MT7623_PIN_272_G2_RXD3_FUNC_G2_RXD3>,
445 + <MT7623_PIN_273_ESW_INT_FUNC_ESW_INT>,
446 + <MT7623_PIN_274_G2_RXDV_FUNC_G2_RXDV>;
447 + };
448 +
449 + pins_eth_rst {
450 + pinmux = <MT7623_PIN_15_GPIO15_FUNC_GPIO15>;
451 + output-low;
452 + };
453 + };
454 +};
455 +
456 +&usb1 {
457 + vusb33-supply = <&mt6323_vusb_reg>;
458 + vbus-supply = <&usb_p1_vbus>;
459 +// mediatek,wakeup-src = <1>;
460 + status = "okay";
461 +};
462 +
463 +&u3phy1 {
464 + status = "okay";
465 +};
466 +
467 +&pcie {
468 + status = "okay";
469 +};
470 +
471 +&eth {
472 + status = "okay";
473 +};
474 +
475 +&gmac1 {
476 + mac-address = [00 11 22 33 44 56];
477 + status = "okay";
478 +};
479 +
480 +&gmac2 {
481 + mac-address = [00 11 22 33 44 55];
482 + status = "okay";
483 +};
484 +
485 +&gsw {
486 + pinctrl-names = "default";
487 + pinctrl-0 = <&eth_default>;
488 + mediatek,reset-pin = <&pio 15 0>;
489 + status = "okay";
490 +};
491 --- /dev/null
492 +++ b/arch/arm/boot/dts/mt7623.dtsi
493 @@ -0,0 +1,510 @@
494 +/*
495 + * Copyright (c) 2016 MediaTek Inc.
496 + * Author: John Crispin <blogic@openwrt.org>
497 + *
498 + * This program is free software; you can redistribute it and/or modify
499 + * it under the terms of the GNU General Public License version 2 as
500 + * published by the Free Software Foundation.
501 + *
502 + * This program is distributed in the hope that it will be useful,
503 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
504 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
505 + * GNU General Public License for more details.
506 + */
507 +
508 +#include <dt-bindings/interrupt-controller/irq.h>
509 +#include <dt-bindings/interrupt-controller/arm-gic.h>
510 +#include <dt-bindings/clock/mt2701-clk.h>
511 +#include <dt-bindings/power/mt2701-power.h>
512 +#include <dt-bindings/phy/phy.h>
513 +#include <dt-bindings/reset-controller/mt2701-resets.h>
514 +#include <dt-bindings/pinctrl/mt7623-pinfunc.h>
515 +#include "skeleton64.dtsi"
516 +
517 +
518 +/ {
519 + compatible = "mediatek,mt7623";
520 + interrupt-parent = <&sysirq>;
521 +
522 + cpus {
523 + #address-cells = <1>;
524 + #size-cells = <0>;
525 + enable-method = "mediatek,mt6589-smp";
526 +
527 + cpu@0 {
528 + device_type = "cpu";
529 + compatible = "arm,cortex-a7";
530 + reg = <0x0>;
531 + };
532 + cpu@1 {
533 + device_type = "cpu";
534 + compatible = "arm,cortex-a7";
535 + reg = <0x1>;
536 + };
537 + cpu@2 {
538 + device_type = "cpu";
539 + compatible = "arm,cortex-a7";
540 + reg = <0x2>;
541 + };
542 + cpu@3 {
543 + device_type = "cpu";
544 + compatible = "arm,cortex-a7";
545 + reg = <0x3>;
546 + };
547 + };
548 +
549 + system_clk: dummy13m {
550 + compatible = "fixed-clock";
551 + clock-frequency = <13000000>;
552 + #clock-cells = <0>;
553 + };
554 +
555 + rtc_clk: dummy32k {
556 + compatible = "fixed-clock";
557 + clock-frequency = <32000>;
558 + #clock-cells = <0>;
559 + clock-output-names = "clk32k";
560 + };
561 +
562 + clk26m: dummy26m {
563 + compatible = "fixed-clock";
564 + clock-frequency = <26000000>;
565 + #clock-cells = <0>;
566 + clock-output-names = "clk26m";
567 + };
568 +
569 + timer {
570 + compatible = "arm,armv7-timer";
571 + interrupt-parent = <&gic>;
572 + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
573 + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
574 + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
575 + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
576 + };
577 +
578 + topckgen: power-controller@10000000 {
579 + compatible = "mediatek,mt7623-topckgen",
580 + "mediatek,mt2701-topckgen",
581 + "syscon";
582 + reg = <0 0x10000000 0 0x1000>;
583 + #clock-cells = <1>;
584 + };
585 +
586 + infracfg: power-controller@10001000 {
587 + compatible = "mediatek,mt7623-infracfg",
588 + "mediatek,mt2701-infracfg",
589 + "syscon";
590 + reg = <0 0x10001000 0 0x1000>;
591 + #clock-cells = <1>;
592 + #reset-cells = <1>;
593 + };
594 +
595 + pericfg: pericfg@10003000 {
596 + compatible = "mediatek,mt7623-pericfg",
597 + "mediatek,mt2701-pericfg",
598 + "syscon";
599 + reg = <0 0x10003000 0 0x1000>;
600 + #clock-cells = <1>;
601 + #reset-cells = <1>;
602 + };
603 +
604 + pio: pinctrl@10005000 {
605 + compatible = "mediatek,mt7623-pinctrl";
606 + reg = <0 0x1000b000 0 0x1000>;
607 + mediatek,pctl-regmap = <&syscfg_pctl_a>;
608 + pins-are-numbered;
609 + gpio-controller;
610 + #gpio-cells = <2>;
611 + interrupt-controller;
612 + interrupt-parent = <&gic>;
613 + #interrupt-cells = <2>;
614 + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
615 + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
616 + };
617 +
618 + syscfg_pctl_a: syscfg@10005000 {
619 + compatible = "mediatek,mt7623-pctl-a-syscfg", "syscon";
620 + reg = <0 0x10005000 0 0x1000>;
621 + };
622 +
623 + scpsys: scpsys@10006000 {
624 + #power-domain-cells = <1>;
625 + compatible = "mediatek,mt7623-scpsys",
626 + "mediatek,mt2701-scpsys";
627 + reg = <0 0x10006000 0 0x1000>;
628 + infracfg = <&infracfg>;
629 + clocks = <&clk26m>,
630 + <&topckgen CLK_TOP_MM_SEL>;
631 + clock-names = "mfg", "mm";
632 + };
633 +
634 + watchdog: watchdog@10007000 {
635 + compatible = "mediatek,mt7623-wdt",
636 + "mediatek,mt6589-wdt";
637 + reg = <0 0x10007000 0 0x100>;
638 + };
639 +
640 + timer: timer@10008000 {
641 + compatible = "mediatek,mt7623-timer",
642 + "mediatek,mt6577-timer";
643 + reg = <0 0x10008000 0 0x80>;
644 + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
645 + clocks = <&system_clk>, <&rtc_clk>;
646 + clock-names = "system-clk", "rtc-clk";
647 + };
648 +
649 + pwrap: pwrap@1000d000 {
650 + compatible = "mediatek,mt7623-pwrap",
651 + "mediatek,mt2701-pwrap";
652 + reg = <0 0x1000d000 0 0x1000>;
653 + reg-names = "pwrap";
654 + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
655 + resets = <&infracfg MT2701_INFRA_PMIC_WRAP_RST>;
656 + reset-names = "pwrap";
657 + clocks = <&infracfg CLK_INFRA_PMICSPI>,
658 + <&infracfg CLK_INFRA_PMICWRAP>;
659 + clock-names = "spi", "wrap";
660 + };
661 +
662 + sysirq: interrupt-controller@10200100 {
663 + compatible = "mediatek,mt7623-sysirq",
664 + "mediatek,mt6577-sysirq";
665 + interrupt-controller;
666 + #interrupt-cells = <3>;
667 + interrupt-parent = <&gic>;
668 + reg = <0 0x10200100 0 0x1c>;
669 + };
670 +
671 + apmixedsys: apmixedsys@10209000 {
672 + compatible = "mediatek,mt7623-apmixedsys",
673 + "mediatek,mt2701-apmixedsys";
674 + reg = <0 0x10209000 0 0x1000>;
675 + #clock-cells = <1>;
676 + };
677 +
678 + gic: interrupt-controller@10211000 {
679 + compatible = "arm,cortex-a7-gic";
680 + interrupt-controller;
681 + #interrupt-cells = <3>;
682 + interrupt-parent = <&gic>;
683 + reg = <0 0x10211000 0 0x1000>,
684 + <0 0x10212000 0 0x1000>,
685 + <0 0x10214000 0 0x2000>,
686 + <0 0x10216000 0 0x2000>;
687 + };
688 +
689 + i2c0: i2c@11007000 {
690 + compatible = "mediatek,mt7623-i2c",
691 + "mediatek,mt6577-i2c";
692 + reg = <0 0x11007000 0 0x70>,
693 + <0 0x11000200 0 0x80>;
694 + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_LOW>;
695 + clock-div = <16>;
696 + clocks = <&pericfg CLK_PERI_I2C0>,
697 + <&pericfg CLK_PERI_AP_DMA>;
698 + clock-names = "main", "dma";
699 + #address-cells = <1>;
700 + #size-cells = <0>;
701 + status = "disabled";
702 + };
703 +
704 + i2c1: i2c@11008000 {
705 + compatible = "mediatek,mt7623-i2c",
706 + "mediatek,mt6577-i2c";
707 + reg = <0 0x11008000 0 0x70>,
708 + <0 0x11000280 0 0x80>;
709 + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>;
710 + clock-div = <16>;
711 + clocks = <&pericfg CLK_PERI_I2C1>,
712 + <&pericfg CLK_PERI_AP_DMA>;
713 + clock-names = "main", "dma";
714 + #address-cells = <1>;
715 + #size-cells = <0>;
716 + status = "disabled";
717 + };
718 +
719 + i2c2: i2c@11009000 {
720 + compatible = "mediatek,mt7623-i2c",
721 + "mediatek,mt6577-i2c";
722 + reg = <0 0x11009000 0 0x70>,
723 + <0 0x11000300 0 0x80>;
724 + interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_LOW>;
725 + clock-div = <16>;
726 + clocks = <&pericfg CLK_PERI_I2C2>,
727 + <&pericfg CLK_PERI_AP_DMA>;
728 + clock-names = "main", "dma";
729 + #address-cells = <1>;
730 + #size-cells = <0>;
731 + status = "disabled";
732 + };
733 +
734 + uart0: serial@11002000 {
735 + compatible = "mediatek,mt7623-uart",
736 + "mediatek,mt6577-uart";
737 + reg = <0 0x11002000 0 0x400>;
738 + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
739 + clocks = <&pericfg CLK_PERI_UART0_SEL>,
740 + <&pericfg CLK_PERI_UART0>;
741 + clock-names = "baud", "bus";
742 + status = "disabled";
743 + };
744 +
745 + uart1: serial@11003000 {
746 + compatible = "mediatek,mt7623-uart",
747 + "mediatek,mt6577-uart";
748 + reg = <0 0x11003000 0 0x400>;
749 + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
750 + clocks = <&pericfg CLK_PERI_UART1_SEL>,
751 + <&pericfg CLK_PERI_UART1>;
752 + clock-names = "baud", "bus";
753 + status = "disabled";
754 + };
755 +
756 + uart2: serial@11004000 {
757 + compatible = "mediatek,mt7623-uart",
758 + "mediatek,mt6577-uart";
759 + reg = <0 0x11004000 0 0x400>;
760 + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
761 + clocks = <&pericfg CLK_PERI_UART2_SEL>,
762 + <&pericfg CLK_PERI_UART2>;
763 + clock-names = "baud", "bus";
764 + status = "disabled";
765 + };
766 +
767 + uart3: serial@11005000 {
768 + compatible = "mediatek,mt7623-uart",
769 + "mediatek,mt6577-uart";
770 + reg = <0 0x11005000 0 0x400>;
771 + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
772 + clocks = <&pericfg CLK_PERI_UART3_SEL>,
773 + <&pericfg CLK_PERI_UART3>;
774 + clock-names = "baud", "bus";
775 + status = "disabled";
776 + };
777 +
778 + spi: spi@1100a000 {
779 + compatible = "mediatek,mt7623-spi", "mediatek,mt6589-spi";
780 + reg = <0 0x1100a000 0 0x1000>;
781 + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
782 + clocks = <&pericfg CLK_PERI_SPI0>;
783 + clock-names = "main";
784 +
785 + status = "disabled";
786 + };
787 +
788 + mmc0: mmc@11230000 {
789 + compatible = "mediatek,mt7623-mmc",
790 + "mediatek,mt8135-mmc";
791 + reg = <0 0x11230000 0 0x1000>;
792 + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>;
793 + clocks = <&pericfg CLK_PERI_MSDC30_0>,
794 + <&topckgen CLK_TOP_MSDC30_0_SEL>;
795 + clock-names = "source", "hclk";
796 + status = "disabled";
797 + };
798 +
799 + mmc1: mmc@11240000 {
800 + compatible = "mediatek,mt7623-mmc",
801 + "mediatek,mt8135-mmc";
802 + reg = <0 0x11240000 0 0x1000>;
803 + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>;
804 + clocks = <&pericfg CLK_PERI_MSDC30_1>,
805 + <&topckgen CLK_TOP_MSDC30_1_SEL>;
806 + clock-names = "source", "hclk";
807 + status = "disabled";
808 + };
809 +
810 + usb1: usb@1a1c0000 {
811 + compatible = "mediatek,mt2701-xhci",
812 + "mediatek,mt8173-xhci";
813 + reg = <0 0x1a1c0000 0 0x1000>,
814 + <0 0x1a1c4700 0 0x0100>;
815 + interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_LOW>;
816 + clocks = <&hifsys CLK_HIFSYS_USB0PHY>,
817 + <&topckgen CLK_TOP_ETHIF_SEL>;
818 + clock-names = "sys_ck", "ethif";
819 + power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
820 + phys = <&phy_port0 PHY_TYPE_USB3>;
821 + status = "disabled";
822 + };
823 +
824 + u3phy1: usb-phy@1a1c4000 {
825 + compatible = "mediatek,mt2701-u3phy",
826 + "mediatek,mt8173-u3phy";
827 + reg = <0 0x1a1c4000 0 0x0700>;
828 + clocks = <&clk26m>;
829 + clock-names = "u3phya_ref";
830 + #phy-cells = <1>;
831 + #address-cells = <2>;
832 + #size-cells = <2>;
833 + ranges;
834 + status = "disabled";
835 +
836 + phy_port0: phy_port0: port@1a1c4800 {
837 + reg = <0 0x1a1c4800 0 0x800>;
838 + #phy-cells = <1>;
839 + status = "okay";
840 + };
841 + };
842 +
843 + usb2: usb@1a240000 {
844 + compatible = "mediatek,mt2701-xhci",
845 + "mediatek,mt8173-xhci";
846 + reg = <0 0x1a240000 0 0x1000>,
847 + <0 0x1a244700 0 0x0100>;
848 + interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_LOW>;
849 + clocks = <&hifsys CLK_HIFSYS_USB1PHY>,
850 + <&topckgen CLK_TOP_ETHIF_SEL>;
851 + clock-names = "sys_ck", "ethif";
852 + power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
853 + phys = <&u3phy2 0>;
854 + status = "disabled";
855 + };
856 +
857 + u3phy2: usb-phy@1a244000 {
858 + compatible = "mediatek,mt2701-u3phy",
859 + "mediatek,mt8173-u3phy";
860 + reg = <0 0x1a244000 0 0x0700>,
861 + <0 0x1a244800 0 0x0800>;
862 + clocks = <&clk26m>;
863 + clock-names = "u3phya_ref";
864 + #phy-cells = <1>;
865 + status = "disabled";
866 + };
867 +
868 + hifsys: clock-controller@1a000000 {
869 + compatible = "mediatek,mt7623-hifsys",
870 + "mediatek,mt2701-hifsys",
871 + "syscon";
872 + reg = <0 0x1a000000 0 0x1000>;
873 + #clock-cells = <1>;
874 + #reset-cells = <1>;
875 + };
876 +
877 + pcie: pcie@1a140000 {
878 + compatible = "mediatek,mt7623-pcie";
879 + device_type = "pci";
880 + reg = <0 0x1a140000 0 0x8000>, /* PCI-Express registers */
881 + <0 0x1a149000 0 0x1000>, /* PCI-Express PHY0 */
882 + <0 0x1a14a000 0 0x1000>, /* PCI-Express PHY1 */
883 + <0 0x1a244000 0 0x1000>; /* PCI-Express PHY2 */
884 + reg-names = "pcie", "pcie phy0", "pcie phy1", "pcie phy2";
885 + interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
886 + <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,
887 + <GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
888 + interrupt-names = "pcie0", "pcie1", "pcie2";
889 + clocks = <&topckgen CLK_TOP_ETHIF_SEL>;
890 + clock-names = "pcie";
891 + power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
892 + resets = <&hifsys MT2701_HIFSYS_PCIE0_RST>,
893 + <&hifsys MT2701_HIFSYS_PCIE1_RST>,
894 + <&hifsys MT2701_HIFSYS_PCIE2_RST>;
895 + reset-names = "pcie0", "pcie1", "pcie2";
896 +
897 + mediatek,hifsys = <&hifsys>;
898 +
899 + bus-range = <0x00 0xff>;
900 + #address-cells = <3>;
901 + #size-cells = <2>;
902 +
903 + ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000 /* io space */
904 + 0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>; /* pci memory */
905 +
906 + status = "disabled";
907 +
908 + pcie@1,0 {
909 + device_type = "pci";
910 + reg = <0x0800 0 0 0 0>;
911 +
912 + #address-cells = <3>;
913 + #size-cells = <2>;
914 + ranges;
915 + };
916 +
917 + pcie@2,0{
918 + device_type = "pci";
919 + reg = <0x1000 0 0 0 0>;
920 +
921 + #address-cells = <3>;
922 + #size-cells = <2>;
923 + ranges;
924 + };
925 +
926 + pcie@3,0{
927 + device_type = "pci";
928 + reg = <0x1800 0 0 0 0>;
929 +
930 + #address-cells = <3>;
931 + #size-cells = <2>;
932 + ranges;
933 + };
934 + };
935 +
936 + ethsys: syscon@1b000000 {
937 + #address-cells = <1>;
938 + #size-cells = <1>;
939 + compatible = "mediatek,mt2701-ethsys", "syscon";
940 + reg = <0 0x1b000000 0 0x1000>;
941 + #clock-cells = <1>;
942 + };
943 +
944 + eth: ethernet@1b100000 {
945 + compatible = "mediatek,mt7623-eth";
946 + reg = <0 0x1b100000 0 0x10000>;
947 +
948 + clocks = <&topckgen CLK_TOP_ETHIF_SEL>;
949 + clock-names = "ethif";
950 + interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW
951 + GIC_SPI 199 IRQ_TYPE_LEVEL_LOW
952 + GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
953 + power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
954 +
955 + mediatek,ethsys = <&ethsys>;
956 + mediatek,switch = <&gsw>;
957 +
958 + #address-cells = <1>;
959 + #size-cells = <0>;
960 +
961 + status = "disabled";
962 +
963 + gmac1: mac@0 {
964 + compatible = "mediatek,eth-mac";
965 + reg = <0>;
966 +
967 + status = "disabled";
968 + };
969 +
970 + gmac2: mac@1 {
971 + compatible = "mediatek,eth-mac";
972 + reg = <1>;
973 +
974 + status = "disabled";
975 + };
976 +
977 + mdio-bus {
978 + #address-cells = <1>;
979 + #size-cells = <0>;
980 +
981 + phy1f: ethernet-phy@1f {
982 + reg = <0x1f>;
983 + phy-mode = "rgmii";
984 + };
985 + };
986 + };
987 +
988 + gsw: switch@1b100000 {
989 + compatible = "mediatek,mt7623-gsw";
990 + reg = <0 0x1b110000 0 0x300000>;
991 + interrupt-parent = <&pio>;
992 + interrupts = <168 IRQ_TYPE_EDGE_RISING>;
993 + clocks = <&apmixedsys CLK_APMIXED_TRGPLL>,
994 + <&ethsys CLK_ETHSYS_ESW>,
995 + <&ethsys CLK_ETHSYS_GP2>,
996 + <&ethsys CLK_ETHSYS_GP1>;
997 + clock-names = "trgpll", "esw", "gp2", "gp1";
998 + mt7530-supply = <&mt6323_vpa_reg>;
999 + mediatek,pctl-regmap = <&syscfg_pctl_a>;
1000 + mediatek,ethsys = <&ethsys>;
1001 + status = "disabled";
1002 + };
1003 +};
1004 --- a/arch/arm/mach-mediatek/Kconfig
1005 +++ b/arch/arm/mach-mediatek/Kconfig
1006 @@ -21,6 +21,10 @@ config MACH_MT6592
1007 bool "MediaTek MT6592 SoCs support"
1008 default ARCH_MEDIATEK
1009
1010 +config MACH_MT7623
1011 + bool "MediaTek MT7623 SoCs support"
1012 + default ARCH_MEDIATEK
1013 +
1014 config MACH_MT8127
1015 bool "MediaTek MT8127 SoCs support"
1016 default ARCH_MEDIATEK
1017 --- a/arch/arm/mach-mediatek/mediatek.c
1018 +++ b/arch/arm/mach-mediatek/mediatek.c
1019 @@ -46,6 +46,7 @@ static void __init mediatek_timer_init(v
1020 static const char * const mediatek_board_dt_compat[] = {
1021 "mediatek,mt6589",
1022 "mediatek,mt6592",
1023 + "mediatek,mt7623",
1024 "mediatek,mt8127",
1025 "mediatek,mt8135",
1026 NULL,
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