target/linux/mediatek/patches-4.9/0015-soc-mediatek-Add-MT2701-scpsys-driver.patch

   1 From 112ef1882e12094c823937f9d72f2f598db02df7 Mon Sep 17 00:00:00 2001
   2 From: Shunli Wang <shunli.wang@mediatek.com>
   3 Date: Thu, 20 Oct 2016 16:56:38 +0800
   4 Subject: [PATCH 2/2] soc: mediatek: Add MT2701 scpsys driver
   5
   6 Add scpsys driver for MT2701.
   7
   8 mtk-scpsys now supports MT8173 (arm64) and MT2701 (arm). So it should
   9 be enabled on both arm64 and arm platforms.
  10
  11 Signed-off-by: Shunli Wang <shunli.wang@mediatek.com>
  12 Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
  13 Reviewed-by: Kevin Hilman <khilman@baylibre.com>
  14 Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
  15 ---
  16  drivers/soc/mediatek/Kconfig      |   2 +-
  17  drivers/soc/mediatek/mtk-scpsys.c | 117 +++++++++++++++++++++++++++++++++++++-
  18  2 files changed, 117 insertions(+), 2 deletions(-)
  19
  20 Index: linux-4.9.14/drivers/soc/mediatek/Kconfig
  21 ===================================================================
  22 --- linux-4.9.14.orig/drivers/soc/mediatek/Kconfig
  23 +++ linux-4.9.14/drivers/soc/mediatek/Kconfig
  24 @@ -23,7 +23,7 @@ config MTK_PMIC_WRAP
  25  config MTK_SCPSYS
  26         bool "MediaTek SCPSYS Support"
  27         depends on ARCH_MEDIATEK || COMPILE_TEST
  28 -       default ARM64 && ARCH_MEDIATEK
  29 +       default ARCH_MEDIATEK
  30         select REGMAP
  31         select MTK_INFRACFG
  32         select PM_GENERIC_DOMAINS if PM
  33 Index: linux-4.9.14/drivers/soc/mediatek/mtk-scpsys.c
  34 ===================================================================
  35 --- linux-4.9.14.orig/drivers/soc/mediatek/mtk-scpsys.c
  36 +++ linux-4.9.14/drivers/soc/mediatek/mtk-scpsys.c
  37 @@ -20,6 +20,7 @@
  38  #include <linux/regulator/consumer.h>
  39  #include <linux/soc/mediatek/infracfg.h>
  40
  41 +#include <dt-bindings/power/mt2701-power.h>
  42  #include <dt-bindings/power/mt8173-power.h>
  43
  44  #define SPM_VDE_PWR_CON                        0x0210
  45 @@ -27,8 +28,13 @@
  46  #define SPM_VEN_PWR_CON                        0x0230
  47  #define SPM_ISP_PWR_CON                        0x0238
  48  #define SPM_DIS_PWR_CON                        0x023c
  49 +#define SPM_CONN_PWR_CON               0x0280
  50  #define SPM_VEN2_PWR_CON               0x0298
  51 -#define SPM_AUDIO_PWR_CON              0x029c
  52 +#define SPM_AUDIO_PWR_CON              0x029c  /* MT8173 */
  53 +#define SPM_BDP_PWR_CON                        0x029c  /* MT2701 */
  54 +#define SPM_ETH_PWR_CON                        0x02a0
  55 +#define SPM_HIF_PWR_CON                        0x02a4
  56 +#define SPM_IFR_MSC_PWR_CON            0x02a8
  57  #define SPM_MFG_2D_PWR_CON             0x02c0
  58  #define SPM_MFG_ASYNC_PWR_CON          0x02c4
  59  #define SPM_USB_PWR_CON                        0x02cc
  60 @@ -42,10 +48,15 @@
  61  #define PWR_ON_2ND_BIT                 BIT(3)
  62  #define PWR_CLK_DIS_BIT                        BIT(4)
  63
  64 +#define PWR_STATUS_CONN                        BIT(1)
  65  #define PWR_STATUS_DISP                        BIT(3)
  66  #define PWR_STATUS_MFG                 BIT(4)
  67  #define PWR_STATUS_ISP                 BIT(5)
  68  #define PWR_STATUS_VDEC                        BIT(7)
  69 +#define PWR_STATUS_BDP                 BIT(14)
  70 +#define PWR_STATUS_ETH                 BIT(15)
  71 +#define PWR_STATUS_HIF                 BIT(16)
  72 +#define PWR_STATUS_IFR_MSC             BIT(17)
  73  #define PWR_STATUS_VENC_LT             BIT(20)
  74  #define PWR_STATUS_VENC                        BIT(21)
  75  #define PWR_STATUS_MFG_2D              BIT(22)
  76 @@ -59,6 +70,7 @@ enum clk_id {
  77         CLK_MFG,
  78         CLK_VENC,
  79         CLK_VENC_LT,
  80 +       CLK_ETHIF,
  81         CLK_MAX,
  82  };
  83
  84 @@ -68,6 +80,7 @@ static const char * const clk_names[] =
  85         "mfg",
  86         "venc",
  87         "venc_lt",
  88 +       "ethif",
  89         NULL,
  90  };
  91
  92 @@ -455,6 +468,96 @@ static void mtk_register_power_domains(s
  93  }
  94
  95  /*
  96 + * MT2701 power domain support
  97 + */
  98 +
  99 +static const struct scp_domain_data scp_domain_data_mt2701[] = {
 100 +       [MT2701_POWER_DOMAIN_CONN] = {
 101 +               .name = "conn",
 102 +               .sta_mask = PWR_STATUS_CONN,
 103 +               .ctl_offs = SPM_CONN_PWR_CON,
 104 +               .bus_prot_mask = 0x0104,
 105 +               .clk_id = {CLK_NONE},
 106 +               .active_wakeup = true,
 107 +       },
 108 +       [MT2701_POWER_DOMAIN_DISP] = {
 109 +               .name = "disp",
 110 +               .sta_mask = PWR_STATUS_DISP,
 111 +               .ctl_offs = SPM_DIS_PWR_CON,
 112 +               .sram_pdn_bits = GENMASK(11, 8),
 113 +               .clk_id = {CLK_MM},
 114 +               .bus_prot_mask = 0x0002,
 115 +               .active_wakeup = true,
 116 +       },
 117 +       [MT2701_POWER_DOMAIN_VDEC] = {
 118 +               .name = "vdec",
 119 +               .sta_mask = PWR_STATUS_VDEC,
 120 +               .ctl_offs = SPM_VDE_PWR_CON,
 121 +               .sram_pdn_bits = GENMASK(11, 8),
 122 +               .sram_pdn_ack_bits = GENMASK(12, 12),
 123 +               .clk_id = {CLK_MM},
 124 +               .active_wakeup = true,
 125 +       },
 126 +       [MT2701_POWER_DOMAIN_ISP] = {
 127 +               .name = "isp",
 128 +               .sta_mask = PWR_STATUS_ISP,
 129 +               .ctl_offs = SPM_ISP_PWR_CON,
 130 +               .sram_pdn_bits = GENMASK(11, 8),
 131 +               .sram_pdn_ack_bits = GENMASK(13, 12),
 132 +               .clk_id = {CLK_MM},
 133 +               .active_wakeup = true,
 134 +       },
 135 +       [MT2701_POWER_DOMAIN_BDP] = {
 136 +               .name = "bdp",
 137 +               .sta_mask = PWR_STATUS_BDP,
 138 +               .ctl_offs = SPM_BDP_PWR_CON,
 139 +               .sram_pdn_bits = GENMASK(11, 8),
 140 +               .clk_id = {CLK_NONE},
 141 +               .active_wakeup = true,
 142 +       },
 143 +       [MT2701_POWER_DOMAIN_ETH] = {
 144 +               .name = "eth",
 145 +               .sta_mask = PWR_STATUS_ETH,
 146 +               .ctl_offs = SPM_ETH_PWR_CON,
 147 +               .sram_pdn_bits = GENMASK(11, 8),
 148 +               .sram_pdn_ack_bits = GENMASK(15, 12),
 149 +               .clk_id = {CLK_ETHIF},
 150 +               .active_wakeup = true,
 151 +       },
 152 +       [MT2701_POWER_DOMAIN_HIF] = {
 153 +               .name = "hif",
 154 +               .sta_mask = PWR_STATUS_HIF,
 155 +               .ctl_offs = SPM_HIF_PWR_CON,
 156 +               .sram_pdn_bits = GENMASK(11, 8),
 157 +               .sram_pdn_ack_bits = GENMASK(15, 12),
 158 +               .clk_id = {CLK_ETHIF},
 159 +               .active_wakeup = true,
 160 +       },
 161 +       [MT2701_POWER_DOMAIN_IFR_MSC] = {
 162 +               .name = "ifr_msc",
 163 +               .sta_mask = PWR_STATUS_IFR_MSC,
 164 +               .ctl_offs = SPM_IFR_MSC_PWR_CON,
 165 +               .clk_id = {CLK_NONE},
 166 +               .active_wakeup = true,
 167 +       },
 168 +};
 169 +
 170 +#define NUM_DOMAINS_MT2701     ARRAY_SIZE(scp_domain_data_mt2701)
 171 +
 172 +static int __init scpsys_probe_mt2701(struct platform_device *pdev)
 173 +{
 174 +       struct scp *scp;
 175 +
 176 +       scp = init_scp(pdev, scp_domain_data_mt2701, NUM_DOMAINS_MT2701);
 177 +       if (IS_ERR(scp))
 178 +               return PTR_ERR(scp);
 179 +
 180 +       mtk_register_power_domains(pdev, scp, NUM_DOMAINS_MT2701);
 181 +
 182 +       return 0;
 183 +}
 184 +
 185 +/*
 186   * MT8173 power domain support
 187   */
 188
 189 @@ -583,6 +686,9 @@ static int __init scpsys_probe_mt8173(st
 190
 191  static const struct of_device_id of_scpsys_match_tbl[] = {
 192         {
 193 +               .compatible = "mediatek,mt2701-scpsys",
 194 +               .data = scpsys_probe_mt2701,
 195 +       }, {
 196                 .compatible = "mediatek,mt8173-scpsys",
 197                 .data = scpsys_probe_mt8173,
 198         }, {