target/linux/mediatek/patches-5.15/100-dts-update-mt7622-rfb1.patch

   1 --- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
   2 +++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
   3 @@ -1,7 +1,6 @@
   4  /*
   5 - * Copyright (c) 2017 MediaTek Inc.
   6 - * Author: Ming Huang <ming.huang@mediatek.com>
   7 - *        Sean Wang <sean.wang@mediatek.com>
   8 + * Copyright (c) 2018 MediaTek Inc.
   9 + * Author: Ryder Lee <ryder.lee@mediatek.com>
  10   *
  11   * SPDX-License-Identifier: (GPL-2.0 OR MIT)
  12   */
  13 @@ -23,7 +22,7 @@
  14
  15         chosen {
  16                 stdout-path = "serial0:115200n8";
  17 -               bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512";
  18 +               bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512";
  19         };
  20
  21         cpus {
  22 @@ -40,23 +39,22 @@
  23
  24         gpio-keys {
  25                 compatible = "gpio-keys";
  26 -               poll-interval = <100>;
  27
  28                 factory {
  29                         label = "factory";
  30                         linux,code = <BTN_0>;
  31 -                       gpios = <&pio 0 0>;
  32 +                       gpios = <&pio 0 GPIO_ACTIVE_LOW>;
  33                 };
  34
  35                 wps {
  36                         label = "wps";
  37                         linux,code = <KEY_WPS_BUTTON>;
  38 -                       gpios = <&pio 102 0>;
  39 +                       gpios = <&pio 102 GPIO_ACTIVE_LOW>;
  40                 };
  41         };
  42
  43         memory@40000000 {
  44 -               reg = <0 0x40000000 0 0x20000000>;
  45 +               reg = <0 0x40000000 0 0x40000000>;
  46         };
  47
  48         reg_1p8v: regulator-1p8v {
  49 @@ -132,22 +130,22 @@
  50
  51                                 port@0 {
  52                                         reg = <0>;
  53 -                                       label = "lan0";
  54 +                                       label = "lan1";
  55                                 };
  56
  57                                 port@1 {
  58                                         reg = <1>;
  59 -                                       label = "lan1";
  60 +                                       label = "lan2";
  61                                 };
  62
  63                                 port@2 {
  64                                         reg = <2>;
  65 -                                       label = "lan2";
  66 +                                       label = "lan3";
  67                                 };
  68
  69                                 port@3 {
  70                                         reg = <3>;
  71 -                                       label = "lan3";
  72 +                                       label = "lan4";
  73                                 };
  74
  75                                 port@4 {
  76 @@ -236,15 +234,28 @@
  77
  78  &pcie {
  79         pinctrl-names = "default";
  80 -       pinctrl-0 = <&pcie0_pins>;
  81 +       pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>;
  82         status = "okay";
  83
  84         pcie@0,0 {
  85                 status = "okay";
  86         };
  87 +
  88 +       pcie@1,0 {
  89 +               status = "okay";
  90 +       };
  91  };
  92
  93  &pio {
  94 +       /* Attention: GPIO 90 is used to switch between PCIe@1,0 and
  95 +        * SATA functions. i.e. output-high: PCIe, output-low: SATA
  96 +        */
  97 +       asm_sel {
  98 +               gpio-hog;
  99 +               gpios = <90 GPIO_ACTIVE_HIGH>;
 100 +               output-high;
 101 +       };
 102 +
 103         /* eMMC is shared pin with parallel NAND */
 104         emmc_pins_default: emmc-pins-default {
 105                 mux {
 106 @@ -521,11 +532,11 @@
 107  };
 108
 109  &sata {
 110 -       status = "okay";
 111 +       status = "disabled";
 112  };
 113
 114  &sata_phy {
 115 -       status = "okay";
 116 +       status = "disabled";
 117  };
 118
 119  &spi0 {