target/linux/mediatek/patches/0024-ARM64-dts-mt8173-Add-thermal-auxadc-device-nodes.patch

   1 From 720e25e5c821336f7fa0c5fb564475c791c00340 Mon Sep 17 00:00:00 2001
   2 From: Sascha Hauer <s.hauer@pengutronix.de>
   3 Date: Wed, 13 May 2015 10:52:43 +0200
   4 Subject: [PATCH 24/76] ARM64: dts: mt8173: Add thermal/auxadc device nodes
   5
   6 Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
   7 ---
   8  arch/arm64/boot/dts/mediatek/mt8173.dtsi |   18 ++++++++++++++++++
   9  1 file changed, 18 insertions(+)
  10
  11 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
  12 +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
  13 @@ -147,6 +147,11 @@
  14                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  15                 };
  16
  17 +               auxadc: auxadc@11001000 {
  18 +                       compatible = "mediatek,mt8173-auxadc";
  19 +                       reg = <0 0x11001000 0 0x1000>;
  20 +               };
  21 +
  22                 uart0: serial@11002000 {
  23                         compatible = "mediatek,mt8173-uart",
  24                                         "mediatek,mt6577-uart";
  25 @@ -182,6 +187,19 @@
  26                         clocks = <&uart_clk>;
  27                         status = "disabled";
  28                 };
  29 +
  30 +               thermal: thermal@1100b000 {
  31 +                       #thermal-sensor-cells = <1>;
  32 +                       compatible = "mediatek,mt8173-thermal";
  33 +                       reg = <0 0x1100b000 0 0x1000>;
  34 +                       interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>;
  35 +                       clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>;
  36 +                       clock-names = "therm", "auxadc";
  37 +                       resets = <&pericfg MT8173_PERI_THERM_SW_RST>;
  38 +                       reset-names = "therm";
  39 +                       auxadc = <&auxadc>;
  40 +                       apmixedsys = <&apmixedsys>;
  41 +               };
  42         };
  43
  44  };