target/linux/mediatek/patches/0067-arm-mediatek-add-mt7623-support.patch

   1 From 89556b1a4d98fbfe498c8f26e988cbb8266f7dfe Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Sat, 27 Jun 2015 13:17:35 +0200
   4 Subject: [PATCH 67/76] arm: mediatek: add mt7623 support
   5
   6 Signed-off-by: John Crispin <blogic@openwrt.org>
   7 ---
   8  arch/arm/mach-mediatek/Kconfig                     |    6 ++
   9  arch/arm/mach-mediatek/mediatek.c                  |    2 +
  10  .../dt-bindings/reset-controller/mt7623-resets.h   |   59 ++++++++++++++++++++
  11  3 files changed, 67 insertions(+)
  12  create mode 100644 include/dt-bindings/reset-controller/mt7623-resets.h
  13
  14 --- a/arch/arm/mach-mediatek/Kconfig
  15 +++ b/arch/arm/mach-mediatek/Kconfig
  16 @@ -17,6 +17,12 @@ config MACH_MT6592
  17         bool "MediaTek MT6592 SoCs support"
  18         default ARCH_MEDIATEK
  19
  20 +config MACH_MT7623
  21 +       bool "MediaTek MT7623 SoCs support"
  22 +       default ARCH_MEDIATEK
  23 +       select ARCH_HAS_PCI
  24 +       select PCI
  25 +
  26  config MACH_MT8127
  27         bool "MediaTek MT8127 SoCs support"
  28         default ARCH_MEDIATEK
  29 --- a/arch/arm/mach-mediatek/mediatek.c
  30 +++ b/arch/arm/mach-mediatek/mediatek.c
  31 @@ -29,6 +29,7 @@ static void __init mediatek_timer_init(v
  32         void __iomem *gpt_base = 0;
  33
  34         if (of_machine_is_compatible("mediatek,mt6589") ||
  35 +           of_machine_is_compatible("mediatek,mt7623") ||
  36             of_machine_is_compatible("mediatek,mt8135") ||
  37             of_machine_is_compatible("mediatek,mt8127")) {
  38                 /* turn on GPT6 which ungates arch timer clocks */
  39 @@ -48,6 +49,7 @@ static void __init mediatek_timer_init(v
  40  static const char * const mediatek_board_dt_compat[] = {
  41         "mediatek,mt6589",
  42         "mediatek,mt6592",
  43 +       "mediatek,mt7623",
  44         "mediatek,mt8127",
  45         "mediatek,mt8135",
  46         NULL,
  47 --- /dev/null
  48 +++ b/include/dt-bindings/reset-controller/mt7623-resets.h
  49 @@ -0,0 +1,59 @@
  50 +/*
  51 + * Copyright (c) 2015 OpenWrt
  52 + * Author: John Crispin
  53 + *
  54 + * This program is free software; you can redistribute it and/or modify
  55 + * it under the terms of the GNU General Public License version 2 as
  56 + * published by the Free Software Foundation.
  57 + *
  58 + * This program is distributed in the hope that it will be useful,
  59 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  60 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  61 + * GNU General Public License for more details.
  62 + */
  63 +
  64 +#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT7623
  65 +#define _DT_BINDINGS_RESET_CONTROLLER_MT7623
  66 +
  67 +/* INFRACFG resets */
  68 +#define MT7623_INFRA_EMI_REG_RST       0
  69 +#define MT7623_INFRA_DRAMC0_A0_RST     1
  70 +#define MT7623_INFRA_FHCTL_RST         2
  71 +#define MT7623_INFRA_APCIRQ_EINT_RST   3
  72 +#define MT7623_INFRA_APXGPT_RST                4
  73 +#define MT7623_INFRA_SCPSYS_RST                5
  74 +#define MT7623_INFRA_KP_RST            6
  75 +#define MT7623_INFRA_PMIC_WRAP_RST     7
  76 +#define MT7623_INFRA_MIPI_RST          8
  77 +#define MT7623_INFRA_IRRX_RST          9
  78 +#define MT7623_INFRA_CEC_RST           10
  79 +#define MT7623_INFRA_EMI_RST           32
  80 +#define MT7623_INFRA_DRAMC0_RST                34
  81 +#define MT7623_INFRA_SMI_RST           37
  82 +#define MT7623_INFRA_M4U_RST           38
  83 +
  84 +/* PERICFG resets */
  85 +#define MT7623_PERI_UART0_SW_RST       0
  86 +#define MT7623_PERI_UART1_SW_RST       1
  87 +#define MT7623_PERI_UART2_SW_RST       2
  88 +#define MT7623_PERI_UART3_SW_RST       3
  89 +#define MT7623_PERI_GCPU_SW_RST                5
  90 +#define MT7623_PERI_BTIF_SW_RST                6
  91 +#define MT7623_PERI_PWM_SW_RST         8
  92 +#define MT7623_PERI_AUXADC_SW_RST      10
  93 +#define MT7623_PERI_DMA_SW_RST         11
  94 +#define MT7623_PERI_NFI_SW_RST         14
  95 +#define MT7623_PERI_NLI_SW_RST         15
  96 +#define MT7623_PERI_THERM_SW_RST       16
  97 +#define MT7623_PERI_MSDC0_SW_RST       17
  98 +#define MT7623_PERI_MSDC1_SW_RST       19
  99 +#define MT7623_PERI_MSDC2_SW_RST       20
 100 +#define MT7623_PERI_I2C0_SW_RST                22
 101 +#define MT7623_PERI_I2C1_SW_RST                23
 102 +#define MT7623_PERI_I2C2_SW_RST                24
 103 +#define MT7623_PERI_I2C3_SW_RST                25
 104 +#define MT7623_PERI_USB_SW_RST         28
 105 +#define MT7623_PERI_ETH_SW_RST         29
 106 +#define MT7623_PERI_SPI0_SW_RST                33
 107 +
 108 +#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT7623 */