target/linux/mvebu/patches-5.4/006-v5.5-arm64-dts-marvell-Externalize-PCIe-macros-from-CP11x.patch

   1 From 5f07b26e85dc86f017833ea745ff4e5b420280cd Mon Sep 17 00:00:00 2001
   2 From: Miquel Raynal <miquel.raynal@bootlin.com>
   3 Date: Fri, 4 Oct 2019 16:27:31 +0200
   4 Subject: [PATCH] arm64: dts: marvell: Externalize PCIe macros from CP11x file
   5
   6 PCIe macros are specific to CP110 and will not fit CP115
   7 constraints. To keep the same way the files are organized, just move
   8 some macros out of the CP11x generic file and define them directly in
   9 SoC DTSI, instead of defining single addresses in the SoC DTSI and
  10 reusing them in macros.
  11
  12 In the end:
  13 * CP11X_PCIE_MEM_BASE SoC define is dropped
  14 * CP11X_PCIEx_MEM_BASE is moved out of the generic DT to be put in the
  15   SoC files as it replaces the above definition.
  16 * As the CP11X_PCIEx_MEM_SIZE macro is also subject to change with
  17   newer SoCs, we put it in the SoC files as well.
  18
  19 Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
  20 Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
  21 ---
  22  arch/arm64/boot/dts/marvell/armada-70x0.dtsi  |  6 ++++--
  23  arch/arm64/boot/dts/marvell/armada-80x0.dtsi  | 12 ++++++++----
  24  arch/arm64/boot/dts/marvell/armada-cp11x.dtsi |  9 ++++-----
  25  3 files changed, 16 insertions(+), 11 deletions(-)
  26
  27 --- a/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
  28 +++ b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
  29 @@ -19,7 +19,8 @@
  30   */
  31  #define CP11X_NAME             cp0
  32  #define CP11X_BASE             f2000000
  33 -#define CP11X_PCIE_MEM_BASE    0xf6000000
  34 +#define CP11X_PCIEx_MEM_BASE(iface) (0xf6000000 + (iface * 0x1000000))
  35 +#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
  36  #define CP11X_PCIE0_BASE       f2600000
  37  #define CP11X_PCIE1_BASE       f2620000
  38  #define CP11X_PCIE2_BASE       f2640000
  39 @@ -28,7 +29,8 @@
  40
  41  #undef CP11X_NAME
  42  #undef CP11X_BASE
  43 -#undef CP11X_PCIE_MEM_BASE
  44 +#undef CP11X_PCIEx_MEM_BASE
  45 +#undef CP11X_PCIEx_MEM_SIZE
  46  #undef CP11X_PCIE0_BASE
  47  #undef CP11X_PCIE1_BASE
  48  #undef CP11X_PCIE2_BASE
  49 --- a/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
  50 +++ b/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
  51 @@ -21,7 +21,8 @@
  52   */
  53  #define CP11X_NAME             cp0
  54  #define CP11X_BASE             f2000000
  55 -#define CP11X_PCIE_MEM_BASE    0xf6000000
  56 +#define CP11X_PCIEx_MEM_BASE(iface) (0xf6000000 + (iface * 0x1000000))
  57 +#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
  58  #define CP11X_PCIE0_BASE       f2600000
  59  #define CP11X_PCIE1_BASE       f2620000
  60  #define CP11X_PCIE2_BASE       f2640000
  61 @@ -30,7 +31,8 @@
  62
  63  #undef CP11X_NAME
  64  #undef CP11X_BASE
  65 -#undef CP11X_PCIE_MEM_BASE
  66 +#undef CP11X_PCIEx_MEM_BASE
  67 +#undef CP11X_PCIEx_MEM_SIZE
  68  #undef CP11X_PCIE0_BASE
  69  #undef CP11X_PCIE1_BASE
  70  #undef CP11X_PCIE2_BASE
  71 @@ -40,7 +42,8 @@
  72   */
  73  #define CP11X_NAME             cp1
  74  #define CP11X_BASE             f4000000
  75 -#define CP11X_PCIE_MEM_BASE    0xfa000000
  76 +#define CP11X_PCIEx_MEM_BASE(iface) (0xfa000000 + (iface * 0x1000000))
  77 +#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
  78  #define CP11X_PCIE0_BASE       f4600000
  79  #define CP11X_PCIE1_BASE       f4620000
  80  #define CP11X_PCIE2_BASE       f4640000
  81 @@ -49,7 +52,8 @@
  82
  83  #undef CP11X_NAME
  84  #undef CP11X_BASE
  85 -#undef CP11X_PCIE_MEM_BASE
  86 +#undef CP11X_PCIEx_MEM_BASE
  87 +#undef CP11X_PCIEx_MEM_SIZE
  88  #undef CP11X_PCIE0_BASE
  89  #undef CP11X_PCIE1_BASE
  90  #undef CP11X_PCIE2_BASE
  91 --- a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
  92 +++ b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
  93 @@ -10,8 +10,7 @@
  94
  95  #include "armada-common.dtsi"
  96
  97 -#define CP11X_PCIEx_MEM_BASE(iface)    (CP11X_PCIE_MEM_BASE + (iface *  0x1000000))
  98 -#define CP11X_PCIEx_CONF_BASE(iface)   (CP11X_PCIEx_MEM_BASE(iface) + 0xf00000)
  99 +#define CP11X_PCIEx_CONF_BASE(iface)   (CP11X_PCIEx_MEM_BASE(iface) + CP11X_PCIEx_MEM_SIZE(iface))
 100
 101  / {
 102         /*
 103 @@ -507,7 +506,7 @@
 104
 105                 bus-range = <0 0xff>;
 106                 /* non-prefetchable memory */
 107 -               ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(0) 0  CP11X_PCIEx_MEM_BASE(0) 0 0xf00000>;
 108 +               ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(0) 0  CP11X_PCIEx_MEM_BASE(0) 0 CP11X_PCIEx_MEM_SIZE(0)>;
 109                 interrupt-map-mask = <0 0 0 0>;
 110                 interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 22 IRQ_TYPE_LEVEL_HIGH>;
 111                 interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
 112 @@ -531,7 +530,7 @@
 113
 114                 bus-range = <0 0xff>;
 115                 /* non-prefetchable memory */
 116 -               ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(1) 0  CP11X_PCIEx_MEM_BASE(1) 0 0xf00000>;
 117 +               ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(1) 0  CP11X_PCIEx_MEM_BASE(1) 0 CP11X_PCIEx_MEM_SIZE(1)>;
 118                 interrupt-map-mask = <0 0 0 0>;
 119                 interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 24 IRQ_TYPE_LEVEL_HIGH>;
 120                 interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
 121 @@ -556,7 +555,7 @@
 122
 123                 bus-range = <0 0xff>;
 124                 /* non-prefetchable memory */
 125 -               ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(2) 0  CP11X_PCIEx_MEM_BASE(2) 0 0xf00000>;
 126 +               ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(2) 0  CP11X_PCIEx_MEM_BASE(2) 0 CP11X_PCIEx_MEM_SIZE(2)>;
 127                 interrupt-map-mask = <0 0 0 0>;
 128                 interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 23 IRQ_TYPE_LEVEL_HIGH>;
 129                 interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;