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remove 2.6.32 support
[openwrt/openwrt.git] / target / linux / omap24xx / patches-2.6.35 / 200-omap-platform.patch
1 Index: linux-2.6.35/arch/arm/plat-omap/bootreason.c
2 ===================================================================
3 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
4 +++ linux-2.6.35/arch/arm/plat-omap/bootreason.c 2010-08-08 12:56:34.000000000 +0200
5 @@ -0,0 +1,79 @@
6 +/*
7 + * linux/arch/arm/plat-omap/bootreason.c
8 + *
9 + * OMAP Bootreason passing
10 + *
11 + * Copyright (c) 2004 Nokia
12 + *
13 + * Written by David Weinehall <david.weinehall@nokia.com>
14 + *
15 + * This program is free software; you can redistribute it and/or modify it
16 + * under the terms of the GNU General Public License as published by the
17 + * Free Software Foundation; either version 2 of the License, or (at your
18 + * option) any later version.
19 + *
20 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
21 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
22 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
23 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
24 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
26 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
27 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
29 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 + *
31 + * You should have received a copy of the GNU General Public License along
32 + * with this program; if not, write to the Free Software Foundation, Inc.,
33 + * 675 Mass Ave, Cambridge, MA 02139, USA.
34 + */
35 +#include <linux/proc_fs.h>
36 +#include <linux/errno.h>
37 +#include <plat/board.h>
38 +
39 +static char boot_reason[16];
40 +
41 +static int omap_bootreason_read_proc(char *page, char **start, off_t off,
42 + int count, int *eof, void *data)
43 +{
44 + int len = 0;
45 +
46 + len += sprintf(page + len, "%s\n", boot_reason);
47 +
48 + *start = page + off;
49 +
50 + if (len > off)
51 + len -= off;
52 + else
53 + len = 0;
54 +
55 + return len < count ? len : count;
56 +}
57 +
58 +static int __init bootreason_init(void)
59 +{
60 + const struct omap_boot_reason_config *cfg;
61 + int reason_valid = 0;
62 +
63 + cfg = omap_get_config(OMAP_TAG_BOOT_REASON, struct omap_boot_reason_config);
64 + if (cfg != NULL) {
65 + strncpy(boot_reason, cfg->reason_str, sizeof(cfg->reason_str));
66 + boot_reason[sizeof(cfg->reason_str)] = 0;
67 + reason_valid = 1;
68 + } else {
69 + /* Read the boot reason from the OMAP registers */
70 + }
71 +
72 + if (!reason_valid)
73 + return -ENOENT;
74 +
75 + printk(KERN_INFO "Bootup reason: %s\n", boot_reason);
76 +
77 + if (!create_proc_read_entry("bootreason", S_IRUGO, NULL,
78 + omap_bootreason_read_proc, NULL))
79 + return -ENOMEM;
80 +
81 + return 0;
82 +}
83 +
84 +late_initcall(bootreason_init);
85 Index: linux-2.6.35/arch/arm/plat-omap/common.c
86 ===================================================================
87 --- linux-2.6.35.orig/arch/arm/plat-omap/common.c 2010-08-08 12:56:15.000000000 +0200
88 +++ linux-2.6.35/arch/arm/plat-omap/common.c 2010-08-08 12:56:35.000000000 +0200
89 @@ -47,11 +47,81 @@
90 struct omap_board_config_kernel *omap_board_config;
91 int omap_board_config_size;
92
93 +unsigned char omap_bootloader_tag[1024];
94 +int omap_bootloader_tag_len;
95 +
96 +/* used by omap-smp.c and board-4430sdp.c */
97 +void __iomem *gic_cpu_base_addr;
98 +
99 +#ifdef CONFIG_OMAP_BOOT_TAG
100 +
101 +static int __init parse_tag_omap(const struct tag *tag)
102 +{
103 + u32 size = tag->hdr.size - (sizeof(tag->hdr) >> 2);
104 +
105 + size <<= 2;
106 + if (size > sizeof(omap_bootloader_tag))
107 + return -1;
108 +
109 + memcpy(omap_bootloader_tag, tag->u.omap.data, size);
110 + omap_bootloader_tag_len = size;
111 +
112 + return 0;
113 +}
114 +
115 +__tagtable(ATAG_BOARD, parse_tag_omap);
116 +
117 +#endif
118 +
119 static const void *get_config(u16 tag, size_t len, int skip, size_t *len_out)
120 {
121 struct omap_board_config_kernel *kinfo = NULL;
122 int i;
123
124 +#ifdef CONFIG_OMAP_BOOT_TAG
125 + struct omap_board_config_entry *info = NULL;
126 +
127 + if (omap_bootloader_tag_len > 4)
128 + info = (struct omap_board_config_entry *) omap_bootloader_tag;
129 + while (info != NULL) {
130 + u8 *next;
131 +
132 + if (info->tag == tag) {
133 + if (skip == 0)
134 + break;
135 + skip--;
136 + }
137 +
138 + if ((info->len & 0x03) != 0) {
139 + /* We bail out to avoid an alignment fault */
140 + printk(KERN_ERR "OMAP peripheral config: Length (%d) not word-aligned (tag %04x)\n",
141 + info->len, info->tag);
142 + return NULL;
143 + }
144 + next = (u8 *) info + sizeof(*info) + info->len;
145 + if (next >= omap_bootloader_tag + omap_bootloader_tag_len)
146 + info = NULL;
147 + else
148 + info = (struct omap_board_config_entry *) next;
149 + }
150 + if (info != NULL) {
151 + /* Check the length as a lame attempt to check for
152 + * binary inconsistency. */
153 + if (len != NO_LENGTH_CHECK) {
154 + /* Word-align len */
155 + if (len & 0x03)
156 + len = (len + 3) & ~0x03;
157 + if (info->len != len) {
158 + printk(KERN_ERR "OMAP peripheral config: Length mismatch with tag %x (want %d, got %d)\n",
159 + tag, len, info->len);
160 + return NULL;
161 + }
162 + }
163 + if (len_out != NULL)
164 + *len_out = info->len;
165 + return info->data;
166 + }
167 +#endif
168 /* Try to find the config from the board-specific structures
169 * in the kernel. */
170 for (i = 0; i < omap_board_config_size; i++) {
171 Index: linux-2.6.35/arch/arm/plat-omap/component-version.c
172 ===================================================================
173 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
174 +++ linux-2.6.35/arch/arm/plat-omap/component-version.c 2010-08-08 12:56:36.000000000 +0200
175 @@ -0,0 +1,64 @@
176 +/*
177 + * linux/arch/arm/plat-omap/component-version.c
178 + *
179 + * Copyright (C) 2005 Nokia Corporation
180 + * Written by Juha Yrjölä <juha.yrjola@nokia.com>
181 + *
182 + * This program is free software; you can redistribute it and/or modify
183 + * it under the terms of the GNU General Public License version 2 as
184 + * published by the Free Software Foundation.
185 + */
186 +
187 +#include <linux/init.h>
188 +#include <linux/module.h>
189 +#include <linux/err.h>
190 +#include <linux/proc_fs.h>
191 +#include <plat/board.h>
192 +
193 +static int component_version_read_proc(char *page, char **start, off_t off,
194 + int count, int *eof, void *data)
195 +{
196 + int len, i;
197 + const struct omap_version_config *ver;
198 + char *p;
199 +
200 + i = 0;
201 + p = page;
202 + while ((ver = omap_get_nr_config(OMAP_TAG_VERSION_STR,
203 + struct omap_version_config, i)) != NULL) {
204 + p += sprintf(p, "%-12s%s\n", ver->component, ver->version);
205 + i++;
206 + }
207 +
208 + len = (p - page) - off;
209 + if (len < 0)
210 + len = 0;
211 +
212 + *eof = (len <= count) ? 1 : 0;
213 + *start = page + off;
214 +
215 + return len;
216 +}
217 +
218 +static int __init component_version_init(void)
219 +{
220 + if (omap_get_config(OMAP_TAG_VERSION_STR, struct omap_version_config) == NULL)
221 + return -ENODEV;
222 + if (!create_proc_read_entry("component_version", S_IRUGO, NULL,
223 + component_version_read_proc, NULL))
224 + return -ENOMEM;
225 +
226 + return 0;
227 +}
228 +
229 +static void __exit component_version_exit(void)
230 +{
231 + remove_proc_entry("component_version", NULL);
232 +}
233 +
234 +late_initcall(component_version_init);
235 +module_exit(component_version_exit);
236 +
237 +MODULE_AUTHOR("Juha Yrjölä <juha.yrjola@nokia.com>");
238 +MODULE_DESCRIPTION("Component version driver");
239 +MODULE_LICENSE("GPL");
240 Index: linux-2.6.35/arch/arm/plat-omap/include/mach/blizzard.h
241 ===================================================================
242 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
243 +++ linux-2.6.35/arch/arm/plat-omap/include/mach/blizzard.h 2010-08-08 12:56:36.000000000 +0200
244 @@ -0,0 +1,12 @@
245 +#ifndef _BLIZZARD_H
246 +#define _BLIZZARD_H
247 +
248 +struct blizzard_platform_data {
249 + void (*power_up)(struct device *dev);
250 + void (*power_down)(struct device *dev);
251 + unsigned long (*get_clock_rate)(struct device *dev);
252 +
253 + unsigned te_connected : 1;
254 +};
255 +
256 +#endif
257 Index: linux-2.6.35/arch/arm/plat-omap/include/mach/board-ams-delta.h
258 ===================================================================
259 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
260 +++ linux-2.6.35/arch/arm/plat-omap/include/mach/board-ams-delta.h 2010-08-08 12:56:37.000000000 +0200
261 @@ -0,0 +1,76 @@
262 +/*
263 + * arch/arm/plat-omap/include/mach/board-ams-delta.h
264 + *
265 + * Copyright (C) 2006 Jonathan McDowell <noodles@earth.li>
266 + *
267 + * This program is free software; you can redistribute it and/or modify it
268 + * under the terms of the GNU General Public License as published by the
269 + * Free Software Foundation; either version 2 of the License, or (at your
270 + * option) any later version.
271 + *
272 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
273 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
274 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
275 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
276 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
277 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
278 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
279 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
280 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
281 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
282 + *
283 + * You should have received a copy of the GNU General Public License along
284 + * with this program; if not, write to the Free Software Foundation, Inc.,
285 + * 675 Mass Ave, Cambridge, MA 02139, USA.
286 + */
287 +#ifndef __ASM_ARCH_OMAP_AMS_DELTA_H
288 +#define __ASM_ARCH_OMAP_AMS_DELTA_H
289 +
290 +#if defined (CONFIG_MACH_AMS_DELTA)
291 +
292 +#define AMS_DELTA_LATCH1_PHYS 0x01000000
293 +#define AMS_DELTA_LATCH1_VIRT 0xEA000000
294 +#define AMS_DELTA_MODEM_PHYS 0x04000000
295 +#define AMS_DELTA_MODEM_VIRT 0xEB000000
296 +#define AMS_DELTA_LATCH2_PHYS 0x08000000
297 +#define AMS_DELTA_LATCH2_VIRT 0xEC000000
298 +
299 +#define AMS_DELTA_LATCH1_LED_CAMERA 0x01
300 +#define AMS_DELTA_LATCH1_LED_ADVERT 0x02
301 +#define AMS_DELTA_LATCH1_LED_EMAIL 0x04
302 +#define AMS_DELTA_LATCH1_LED_HANDSFREE 0x08
303 +#define AMS_DELTA_LATCH1_LED_VOICEMAIL 0x10
304 +#define AMS_DELTA_LATCH1_LED_VOICE 0x20
305 +
306 +#define AMS_DELTA_LATCH2_LCD_VBLEN 0x0001
307 +#define AMS_DELTA_LATCH2_LCD_NDISP 0x0002
308 +#define AMS_DELTA_LATCH2_NAND_NCE 0x0004
309 +#define AMS_DELTA_LATCH2_NAND_NRE 0x0008
310 +#define AMS_DELTA_LATCH2_NAND_NWP 0x0010
311 +#define AMS_DELTA_LATCH2_NAND_NWE 0x0020
312 +#define AMS_DELTA_LATCH2_NAND_ALE 0x0040
313 +#define AMS_DELTA_LATCH2_NAND_CLE 0x0080
314 +#define AMD_DELTA_LATCH2_KEYBRD_PWR 0x0100
315 +#define AMD_DELTA_LATCH2_KEYBRD_DATA 0x0200
316 +#define AMD_DELTA_LATCH2_SCARD_RSTIN 0x0400
317 +#define AMD_DELTA_LATCH2_SCARD_CMDVCC 0x0800
318 +#define AMS_DELTA_LATCH2_MODEM_NRESET 0x1000
319 +#define AMS_DELTA_LATCH2_MODEM_CODEC 0x2000
320 +
321 +#define AMS_DELTA_GPIO_PIN_KEYBRD_DATA 0
322 +#define AMS_DELTA_GPIO_PIN_KEYBRD_CLK 1
323 +#define AMS_DELTA_GPIO_PIN_MODEM_IRQ 2
324 +#define AMS_DELTA_GPIO_PIN_HOOK_SWITCH 4
325 +#define AMS_DELTA_GPIO_PIN_SCARD_NOFF 6
326 +#define AMS_DELTA_GPIO_PIN_SCARD_IO 7
327 +#define AMS_DELTA_GPIO_PIN_CONFIG 11
328 +#define AMS_DELTA_GPIO_PIN_NAND_RB 12
329 +
330 +#ifndef __ASSEMBLY__
331 +void ams_delta_latch1_write(u8 mask, u8 value);
332 +void ams_delta_latch2_write(u16 mask, u16 value);
333 +#endif
334 +
335 +#endif /* CONFIG_MACH_AMS_DELTA */
336 +
337 +#endif /* __ASM_ARCH_OMAP_AMS_DELTA_H */
338 Index: linux-2.6.35/arch/arm/plat-omap/include/mach/board.h
339 ===================================================================
340 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
341 +++ linux-2.6.35/arch/arm/plat-omap/include/mach/board.h 2010-08-08 12:56:37.000000000 +0200
342 @@ -0,0 +1,169 @@
343 +/*
344 + * arch/arm/plat-omap/include/mach/board.h
345 + *
346 + * Information structures for board-specific data
347 + *
348 + * Copyright (C) 2004 Nokia Corporation
349 + * Written by Juha Yrjölä <juha.yrjola@nokia.com>
350 + */
351 +
352 +#ifndef _OMAP_BOARD_H
353 +#define _OMAP_BOARD_H
354 +
355 +#include <linux/types.h>
356 +
357 +#include <plat/gpio-switch.h>
358 +
359 +/*
360 + * OMAP35x EVM revision
361 + * Run time detection of EVM revision is done by reading Ethernet
362 + * PHY ID -
363 + * GEN_1 = 0x01150000
364 + * GEN_2 = 0x92200000
365 + */
366 +enum {
367 + OMAP3EVM_BOARD_GEN_1 = 0, /* EVM Rev between A - D */
368 + OMAP3EVM_BOARD_GEN_2, /* EVM Rev >= Rev E */
369 +};
370 +
371 +/* Different peripheral ids */
372 +#define OMAP_TAG_CLOCK 0x4f01
373 +#define OMAP_TAG_LCD 0x4f05
374 +#define OMAP_TAG_GPIO_SWITCH 0x4f06
375 +#define OMAP_TAG_FBMEM 0x4f08
376 +#define OMAP_TAG_STI_CONSOLE 0x4f09
377 +#define OMAP_TAG_CAMERA_SENSOR 0x4f0a
378 +
379 +#define OMAP_TAG_BOOT_REASON 0x4f80
380 +#define OMAP_TAG_FLASH_PART 0x4f81
381 +#define OMAP_TAG_VERSION_STR 0x4f82
382 +
383 +struct omap_clock_config {
384 + /* 0 for 12 MHz, 1 for 13 MHz and 2 for 19.2 MHz */
385 + u8 system_clock_type;
386 +};
387 +
388 +struct omap_serial_console_config {
389 + u8 console_uart;
390 + u32 console_speed;
391 +};
392 +
393 +struct omap_sti_console_config {
394 + unsigned enable:1;
395 + u8 channel;
396 +};
397 +
398 +struct omap_camera_sensor_config {
399 + u16 reset_gpio;
400 + int (*power_on)(void * data);
401 + int (*power_off)(void * data);
402 +};
403 +
404 +struct omap_usb_config {
405 + /* Configure drivers according to the connectors on your board:
406 + * - "A" connector (rectagular)
407 + * ... for host/OHCI use, set "register_host".
408 + * - "B" connector (squarish) or "Mini-B"
409 + * ... for device/gadget use, set "register_dev".
410 + * - "Mini-AB" connector (very similar to Mini-B)
411 + * ... for OTG use as device OR host, initialize "otg"
412 + */
413 + unsigned register_host:1;
414 + unsigned register_dev:1;
415 + u8 otg; /* port number, 1-based: usb1 == 2 */
416 +
417 + u8 hmc_mode;
418 +
419 + /* implicitly true if otg: host supports remote wakeup? */
420 + u8 rwc;
421 +
422 + /* signaling pins used to talk to transceiver on usbN:
423 + * 0 == usbN unused
424 + * 2 == usb0-only, using internal transceiver
425 + * 3 == 3 wire bidirectional
426 + * 4 == 4 wire bidirectional
427 + * 6 == 6 wire unidirectional (or TLL)
428 + */
429 + u8 pins[3];
430 +};
431 +
432 +struct omap_lcd_config {
433 + char panel_name[16];
434 + char ctrl_name[16];
435 + s16 nreset_gpio;
436 + u8 data_lines;
437 +};
438 +
439 +struct device;
440 +struct fb_info;
441 +struct omap_backlight_config {
442 + int default_intensity;
443 + int (*set_power)(struct device *dev, int state);
444 + int (*check_fb)(struct fb_info *fb);
445 +};
446 +
447 +struct omap_fbmem_config {
448 + u32 start;
449 + u32 size;
450 +};
451 +
452 +struct omap_pwm_led_platform_data {
453 + const char *name;
454 + int intensity_timer;
455 + int blink_timer;
456 + void (*set_power)(struct omap_pwm_led_platform_data *self, int on_off);
457 +};
458 +
459 +struct omap_uart_config {
460 + /* Bit field of UARTs present; bit 0 --> UART1 */
461 + unsigned int enabled_uarts;
462 +};
463 +
464 +
465 +struct omap_flash_part_config {
466 + char part_table[0];
467 +};
468 +
469 +struct omap_boot_reason_config {
470 + char reason_str[12];
471 +};
472 +
473 +struct omap_version_config {
474 + char component[12];
475 + char version[12];
476 +};
477 +
478 +struct omap_board_config_entry {
479 + u16 tag;
480 + u16 len;
481 + u8 data[0];
482 +};
483 +
484 +struct omap_board_config_kernel {
485 + u16 tag;
486 + const void *data;
487 +};
488 +
489 +extern const void *__omap_get_config(u16 tag, size_t len, int nr);
490 +
491 +#define omap_get_config(tag, type) \
492 + ((const type *) __omap_get_config((tag), sizeof(type), 0))
493 +#define omap_get_nr_config(tag, type, nr) \
494 + ((const type *) __omap_get_config((tag), sizeof(type), (nr)))
495 +
496 +extern const void *omap_get_var_config(u16 tag, size_t *len);
497 +
498 +extern struct omap_board_config_kernel *omap_board_config;
499 +extern int omap_board_config_size;
500 +
501 +
502 +/* for TI reference platforms sharing the same debug card */
503 +extern int debug_card_init(u32 addr, unsigned gpio);
504 +
505 +/* OMAP3EVM revision */
506 +#if defined(CONFIG_MACH_OMAP3EVM)
507 +u8 get_omap3_evm_rev(void);
508 +#else
509 +#define get_omap3_evm_rev() (-EINVAL)
510 +#endif
511 +#endif
512 Index: linux-2.6.35/arch/arm/plat-omap/include/mach/board-sx1.h
513 ===================================================================
514 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
515 +++ linux-2.6.35/arch/arm/plat-omap/include/mach/board-sx1.h 2010-08-08 12:56:38.000000000 +0200
516 @@ -0,0 +1,52 @@
517 +/*
518 + * Siemens SX1 board definitions
519 + *
520 + * Copyright: Vovan888 at gmail com
521 + *
522 + * This package is free software; you can redistribute it and/or modify
523 + * it under the terms of the GNU General Public License version 2 as
524 + * published by the Free Software Foundation.
525 + *
526 + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
527 + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
528 + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
529 + */
530 +
531 +#ifndef __ASM_ARCH_SX1_I2C_CHIPS_H
532 +#define __ASM_ARCH_SX1_I2C_CHIPS_H
533 +
534 +#define SOFIA_MAX_LIGHT_VAL 0x2B
535 +
536 +#define SOFIA_I2C_ADDR 0x32
537 +/* Sofia reg 3 bits masks */
538 +#define SOFIA_POWER1_REG 0x03
539 +
540 +#define SOFIA_USB_POWER 0x01
541 +#define SOFIA_MMC_POWER 0x04
542 +#define SOFIA_BLUETOOTH_POWER 0x08
543 +#define SOFIA_MMILIGHT_POWER 0x20
544 +
545 +#define SOFIA_POWER2_REG 0x04
546 +#define SOFIA_BACKLIGHT_REG 0x06
547 +#define SOFIA_KEYLIGHT_REG 0x07
548 +#define SOFIA_DIMMING_REG 0x09
549 +
550 +
551 +/* Function Prototypes for SX1 devices control on I2C bus */
552 +
553 +int sx1_setbacklight(u8 backlight);
554 +int sx1_getbacklight(u8 *backlight);
555 +int sx1_setkeylight(u8 keylight);
556 +int sx1_getkeylight(u8 *keylight);
557 +
558 +int sx1_setmmipower(u8 onoff);
559 +int sx1_setusbpower(u8 onoff);
560 +int sx1_i2c_read_byte(u8 devaddr, u8 regoffset, u8 *value);
561 +int sx1_i2c_write_byte(u8 devaddr, u8 regoffset, u8 value);
562 +
563 +/* MMC prototypes */
564 +
565 +extern void sx1_mmc_init(void);
566 +extern void sx1_mmc_slot_cover_handler(void *arg, int state);
567 +
568 +#endif /* __ASM_ARCH_SX1_I2C_CHIPS_H */
569 Index: linux-2.6.35/arch/arm/plat-omap/include/mach/board-voiceblue.h
570 ===================================================================
571 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
572 +++ linux-2.6.35/arch/arm/plat-omap/include/mach/board-voiceblue.h 2010-08-08 12:56:39.000000000 +0200
573 @@ -0,0 +1,19 @@
574 +/*
575 + * Copyright (C) 2004 2N Telekomunikace, Ladislav Michl <michl@2n.cz>
576 + *
577 + * Hardware definitions for OMAP5910 based VoiceBlue board.
578 + *
579 + * This program is free software; you can redistribute it and/or modify
580 + * it under the terms of the GNU General Public License version 2 as
581 + * published by the Free Software Foundation.
582 + */
583 +
584 +#ifndef __ASM_ARCH_VOICEBLUE_H
585 +#define __ASM_ARCH_VOICEBLUE_H
586 +
587 +extern void voiceblue_wdt_enable(void);
588 +extern void voiceblue_wdt_disable(void);
589 +extern void voiceblue_wdt_ping(void);
590 +
591 +#endif /* __ASM_ARCH_VOICEBLUE_H */
592 +
593 Index: linux-2.6.35/arch/arm/plat-omap/include/mach/cbus.h
594 ===================================================================
595 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
596 +++ linux-2.6.35/arch/arm/plat-omap/include/mach/cbus.h 2010-08-08 12:56:39.000000000 +0200
597 @@ -0,0 +1,31 @@
598 +/*
599 + * cbus.h - CBUS platform_data definition
600 + *
601 + * Copyright (C) 2004 - 2009 Nokia Corporation
602 + *
603 + * Written by Felipe Balbi <felipe.balbi@nokia.com>
604 + *
605 + * This file is subject to the terms and conditions of the GNU General
606 + * Public License. See the file "COPYING" in the main directory of this
607 + * archive for more details.
608 + *
609 + * This program is distributed in the hope that it will be useful,
610 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
611 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
612 + * GNU General Public License for more details.
613 + *
614 + * You should have received a copy of the GNU General Public License
615 + * along with this program; if not, write to the Free Software
616 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
617 + */
618 +
619 +#ifndef __PLAT_CBUS_H
620 +#define __PLAT_CBUS_H
621 +
622 +struct cbus_host_platform_data {
623 + int dat_gpio;
624 + int clk_gpio;
625 + int sel_gpio;
626 +};
627 +
628 +#endif /* __PLAT_CBUS_H */
629 Index: linux-2.6.35/arch/arm/plat-omap/include/mach/clkdev.h
630 ===================================================================
631 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
632 +++ linux-2.6.35/arch/arm/plat-omap/include/mach/clkdev.h 2010-08-08 12:56:40.000000000 +0200
633 @@ -0,0 +1,13 @@
634 +#ifndef __MACH_CLKDEV_H
635 +#define __MACH_CLKDEV_H
636 +
637 +static inline int __clk_get(struct clk *clk)
638 +{
639 + return 1;
640 +}
641 +
642 +static inline void __clk_put(struct clk *clk)
643 +{
644 +}
645 +
646 +#endif
647 Index: linux-2.6.35/arch/arm/plat-omap/include/mach/clkdev_omap.h
648 ===================================================================
649 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
650 +++ linux-2.6.35/arch/arm/plat-omap/include/mach/clkdev_omap.h 2010-08-08 12:56:40.000000000 +0200
651 @@ -0,0 +1,41 @@
652 +/*
653 + * clkdev <-> OMAP integration
654 + *
655 + * Russell King <linux@arm.linux.org.uk>
656 + *
657 + */
658 +
659 +#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_CLKDEV_OMAP_H
660 +#define __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_CLKDEV_OMAP_H
661 +
662 +#include <asm/clkdev.h>
663 +
664 +struct omap_clk {
665 + u16 cpu;
666 + struct clk_lookup lk;
667 +};
668 +
669 +#define CLK(dev, con, ck, cp) \
670 + { \
671 + .cpu = cp, \
672 + .lk = { \
673 + .dev_id = dev, \
674 + .con_id = con, \
675 + .clk = ck, \
676 + }, \
677 + }
678 +
679 +
680 +#define CK_310 (1 << 0)
681 +#define CK_7XX (1 << 1)
682 +#define CK_1510 (1 << 2)
683 +#define CK_16XX (1 << 3)
684 +#define CK_243X (1 << 4)
685 +#define CK_242X (1 << 5)
686 +#define CK_343X (1 << 6)
687 +#define CK_3430ES1 (1 << 7)
688 +#define CK_3430ES2 (1 << 8)
689 +#define CK_443X (1 << 9)
690 +
691 +#endif
692 +
693 Index: linux-2.6.35/arch/arm/plat-omap/include/mach/clockdomain.h
694 ===================================================================
695 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
696 +++ linux-2.6.35/arch/arm/plat-omap/include/mach/clockdomain.h 2010-08-08 12:56:41.000000000 +0200
697 @@ -0,0 +1,111 @@
698 +/*
699 + * arch/arm/plat-omap/include/mach/clockdomain.h
700 + *
701 + * OMAP2/3 clockdomain framework functions
702 + *
703 + * Copyright (C) 2008 Texas Instruments, Inc.
704 + * Copyright (C) 2008 Nokia Corporation
705 + *
706 + * Written by Paul Walmsley
707 + *
708 + * This program is free software; you can redistribute it and/or modify
709 + * it under the terms of the GNU General Public License version 2 as
710 + * published by the Free Software Foundation.
711 + */
712 +
713 +#ifndef __ASM_ARM_ARCH_OMAP_CLOCKDOMAIN_H
714 +#define __ASM_ARM_ARCH_OMAP_CLOCKDOMAIN_H
715 +
716 +#include <plat/powerdomain.h>
717 +#include <plat/clock.h>
718 +#include <plat/cpu.h>
719 +
720 +/* Clockdomain capability flags */
721 +#define CLKDM_CAN_FORCE_SLEEP (1 << 0)
722 +#define CLKDM_CAN_FORCE_WAKEUP (1 << 1)
723 +#define CLKDM_CAN_ENABLE_AUTO (1 << 2)
724 +#define CLKDM_CAN_DISABLE_AUTO (1 << 3)
725 +
726 +#define CLKDM_CAN_HWSUP (CLKDM_CAN_ENABLE_AUTO | CLKDM_CAN_DISABLE_AUTO)
727 +#define CLKDM_CAN_SWSUP (CLKDM_CAN_FORCE_SLEEP | CLKDM_CAN_FORCE_WAKEUP)
728 +#define CLKDM_CAN_HWSUP_SWSUP (CLKDM_CAN_SWSUP | CLKDM_CAN_HWSUP)
729 +
730 +/* OMAP24XX CM_CLKSTCTRL_*.AUTOSTATE_* register bit values */
731 +#define OMAP24XX_CLKSTCTRL_DISABLE_AUTO 0x0
732 +#define OMAP24XX_CLKSTCTRL_ENABLE_AUTO 0x1
733 +
734 +/* OMAP3XXX CM_CLKSTCTRL_*.CLKTRCTRL_* register bit values */
735 +#define OMAP34XX_CLKSTCTRL_DISABLE_AUTO 0x0
736 +#define OMAP34XX_CLKSTCTRL_FORCE_SLEEP 0x1
737 +#define OMAP34XX_CLKSTCTRL_FORCE_WAKEUP 0x2
738 +#define OMAP34XX_CLKSTCTRL_ENABLE_AUTO 0x3
739 +
740 +/*
741 + * struct clkdm_pwrdm_autodep - a powerdomain that should have wkdeps
742 + * and sleepdeps added when a powerdomain should stay active in hwsup mode;
743 + * and conversely, removed when the powerdomain should be allowed to go
744 + * inactive in hwsup mode.
745 + */
746 +struct clkdm_pwrdm_autodep {
747 +
748 + union {
749 + /* Name of the powerdomain to add a wkdep/sleepdep on */
750 + const char *name;
751 +
752 + /* Powerdomain pointer (looked up at clkdm_init() time) */
753 + struct powerdomain *ptr;
754 + } pwrdm;
755 +
756 + /* OMAP chip types that this clockdomain dep is valid on */
757 + const struct omap_chip_id omap_chip;
758 +
759 +};
760 +
761 +struct clockdomain {
762 +
763 + /* Clockdomain name */
764 + const char *name;
765 +
766 + union {
767 + /* Powerdomain enclosing this clockdomain */
768 + const char *name;
769 +
770 + /* Powerdomain pointer assigned at clkdm_register() */
771 + struct powerdomain *ptr;
772 + } pwrdm;
773 +
774 + /* CLKTRCTRL/AUTOSTATE field mask in CM_CLKSTCTRL reg */
775 + const u16 clktrctrl_mask;
776 +
777 + /* Clockdomain capability flags */
778 + const u8 flags;
779 +
780 + /* OMAP chip types that this clockdomain is valid on */
781 + const struct omap_chip_id omap_chip;
782 +
783 + /* Usecount tracking */
784 + atomic_t usecount;
785 +
786 + struct list_head node;
787 +
788 +};
789 +
790 +void clkdm_init(struct clockdomain **clkdms, struct clkdm_pwrdm_autodep *autodeps);
791 +int clkdm_register(struct clockdomain *clkdm);
792 +int clkdm_unregister(struct clockdomain *clkdm);
793 +struct clockdomain *clkdm_lookup(const char *name);
794 +
795 +int clkdm_for_each(int (*fn)(struct clockdomain *clkdm, void *user),
796 + void *user);
797 +struct powerdomain *clkdm_get_pwrdm(struct clockdomain *clkdm);
798 +
799 +void omap2_clkdm_allow_idle(struct clockdomain *clkdm);
800 +void omap2_clkdm_deny_idle(struct clockdomain *clkdm);
801 +
802 +int omap2_clkdm_wakeup(struct clockdomain *clkdm);
803 +int omap2_clkdm_sleep(struct clockdomain *clkdm);
804 +
805 +int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk);
806 +int omap2_clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk);
807 +
808 +#endif
809 Index: linux-2.6.35/arch/arm/plat-omap/include/mach/clock.h
810 ===================================================================
811 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
812 +++ linux-2.6.35/arch/arm/plat-omap/include/mach/clock.h 2010-08-08 12:56:42.000000000 +0200
813 @@ -0,0 +1,168 @@
814 +/*
815 + * arch/arm/plat-omap/include/mach/clock.h
816 + *
817 + * Copyright (C) 2004 - 2005 Nokia corporation
818 + * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
819 + * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
820 + *
821 + * This program is free software; you can redistribute it and/or modify
822 + * it under the terms of the GNU General Public License version 2 as
823 + * published by the Free Software Foundation.
824 + */
825 +
826 +#ifndef __ARCH_ARM_OMAP_CLOCK_H
827 +#define __ARCH_ARM_OMAP_CLOCK_H
828 +
829 +#include <linux/list.h>
830 +
831 +struct module;
832 +struct clk;
833 +struct clockdomain;
834 +
835 +struct clkops {
836 + int (*enable)(struct clk *);
837 + void (*disable)(struct clk *);
838 + void (*find_idlest)(struct clk *, void __iomem **, u8 *);
839 + void (*find_companion)(struct clk *, void __iomem **, u8 *);
840 +};
841 +
842 +#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
843 + defined(CONFIG_ARCH_OMAP4)
844 +
845 +struct clksel_rate {
846 + u32 val;
847 + u8 div;
848 + u8 flags;
849 +};
850 +
851 +struct clksel {
852 + struct clk *parent;
853 + const struct clksel_rate *rates;
854 +};
855 +
856 +struct dpll_data {
857 + void __iomem *mult_div1_reg;
858 + u32 mult_mask;
859 + u32 div1_mask;
860 + struct clk *clk_bypass;
861 + struct clk *clk_ref;
862 + void __iomem *control_reg;
863 + u32 enable_mask;
864 + unsigned int rate_tolerance;
865 + unsigned long last_rounded_rate;
866 + u16 last_rounded_m;
867 + u8 last_rounded_n;
868 + u8 min_divider;
869 + u8 max_divider;
870 + u32 max_tolerance;
871 + u16 max_multiplier;
872 +#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
873 + u8 modes;
874 + void __iomem *autoidle_reg;
875 + void __iomem *idlest_reg;
876 + u32 autoidle_mask;
877 + u32 freqsel_mask;
878 + u32 idlest_mask;
879 + u8 auto_recal_bit;
880 + u8 recal_en_bit;
881 + u8 recal_st_bit;
882 +# endif
883 +};
884 +
885 +#endif
886 +
887 +struct clk {
888 + struct list_head node;
889 + const struct clkops *ops;
890 + const char *name;
891 + int id;
892 + struct clk *parent;
893 + struct list_head children;
894 + struct list_head sibling; /* node for children */
895 + unsigned long rate;
896 + __u32 flags;
897 + void __iomem *enable_reg;
898 + unsigned long (*recalc)(struct clk *);
899 + int (*set_rate)(struct clk *, unsigned long);
900 + long (*round_rate)(struct clk *, unsigned long);
901 + void (*init)(struct clk *);
902 + __u8 enable_bit;
903 + __s8 usecount;
904 +#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
905 + defined(CONFIG_ARCH_OMAP4)
906 + u8 fixed_div;
907 + void __iomem *clksel_reg;
908 + u32 clksel_mask;
909 + const struct clksel *clksel;
910 + struct dpll_data *dpll_data;
911 + const char *clkdm_name;
912 + struct clockdomain *clkdm;
913 +#else
914 + __u8 rate_offset;
915 + __u8 src_offset;
916 +#endif
917 +#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
918 + struct dentry *dent; /* For visible tree hierarchy */
919 +#endif
920 +};
921 +
922 +struct cpufreq_frequency_table;
923 +
924 +struct clk_functions {
925 + int (*clk_enable)(struct clk *clk);
926 + void (*clk_disable)(struct clk *clk);
927 + long (*clk_round_rate)(struct clk *clk, unsigned long rate);
928 + int (*clk_set_rate)(struct clk *clk, unsigned long rate);
929 + int (*clk_set_parent)(struct clk *clk, struct clk *parent);
930 + void (*clk_allow_idle)(struct clk *clk);
931 + void (*clk_deny_idle)(struct clk *clk);
932 + void (*clk_disable_unused)(struct clk *clk);
933 +#ifdef CONFIG_CPU_FREQ
934 + void (*clk_init_cpufreq_table)(struct cpufreq_frequency_table **);
935 +#endif
936 +};
937 +
938 +extern unsigned int mpurate;
939 +
940 +extern int clk_init(struct clk_functions *custom_clocks);
941 +extern void clk_preinit(struct clk *clk);
942 +extern int clk_register(struct clk *clk);
943 +extern void clk_reparent(struct clk *child, struct clk *parent);
944 +extern void clk_unregister(struct clk *clk);
945 +extern void propagate_rate(struct clk *clk);
946 +extern void recalculate_root_clocks(void);
947 +extern unsigned long followparent_recalc(struct clk *clk);
948 +extern void clk_enable_init_clocks(void);
949 +#ifdef CONFIG_CPU_FREQ
950 +extern void clk_init_cpufreq_table(struct cpufreq_frequency_table **table);
951 +#endif
952 +
953 +extern const struct clkops clkops_null;
954 +
955 +/* Clock flags */
956 +/* bit 0 is free */
957 +#define RATE_FIXED (1 << 1) /* Fixed clock rate */
958 +/* bits 2-4 are free */
959 +#define ENABLE_REG_32BIT (1 << 5) /* Use 32-bit access */
960 +#define CLOCK_IDLE_CONTROL (1 << 7)
961 +#define CLOCK_NO_IDLE_PARENT (1 << 8)
962 +#define DELAYED_APP (1 << 9) /* Delay application of clock */
963 +#define CONFIG_PARTICIPANT (1 << 10) /* Fundamental clock */
964 +#define ENABLE_ON_INIT (1 << 11) /* Enable upon framework init */
965 +#define INVERT_ENABLE (1 << 12) /* 0 enables, 1 disables */
966 +#define CLOCK_IN_OMAP4430 (1 << 13)
967 +#define ALWAYS_ENABLED (1 << 14)
968 +/* bits 13-31 are currently free */
969 +
970 +/* Clksel_rate flags */
971 +#define DEFAULT_RATE (1 << 0)
972 +#define RATE_IN_242X (1 << 1)
973 +#define RATE_IN_243X (1 << 2)
974 +#define RATE_IN_343X (1 << 3) /* rates common to all 343X */
975 +#define RATE_IN_3430ES2 (1 << 4) /* 3430ES2 rates only */
976 +#define RATE_IN_4430 (1 << 5)
977 +
978 +#define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X)
979 +
980 +
981 +#endif
982 Index: linux-2.6.35/arch/arm/plat-omap/include/mach/common.h
983 ===================================================================
984 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
985 +++ linux-2.6.35/arch/arm/plat-omap/include/mach/common.h 2010-08-08 12:56:43.000000000 +0200
986 @@ -0,0 +1,83 @@
987 +/*
988 + * arch/arm/plat-omap/include/mach/common.h
989 + *
990 + * Header for code common to all OMAP machines.
991 + *
992 + * This program is free software; you can redistribute it and/or modify it
993 + * under the terms of the GNU General Public License as published by the
994 + * Free Software Foundation; either version 2 of the License, or (at your
995 + * option) any later version.
996 + *
997 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
998 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
999 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
1000 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
1001 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
1002 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
1003 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
1004 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
1005 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
1006 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
1007 + *
1008 + * You should have received a copy of the GNU General Public License along
1009 + * with this program; if not, write to the Free Software Foundation, Inc.,
1010 + * 675 Mass Ave, Cambridge, MA 02139, USA.
1011 + */
1012 +
1013 +#ifndef __ARCH_ARM_MACH_OMAP_COMMON_H
1014 +#define __ARCH_ARM_MACH_OMAP_COMMON_H
1015 +
1016 +#include <plat/i2c.h>
1017 +
1018 +struct sys_timer;
1019 +
1020 +/* used by omap-smp.c and board-4430sdp.c */
1021 +extern void __iomem *gic_cpu_base_addr;
1022 +
1023 +extern void omap_map_common_io(void);
1024 +extern struct sys_timer omap_timer;
1025 +
1026 +/* IO bases for various OMAP processors */
1027 +struct omap_globals {
1028 + u32 class; /* OMAP class to detect */
1029 + void __iomem *tap; /* Control module ID code */
1030 + void __iomem *sdrc; /* SDRAM Controller */
1031 + void __iomem *sms; /* SDRAM Memory Scheduler */
1032 + void __iomem *ctrl; /* System Control Module */
1033 + void __iomem *prm; /* Power and Reset Management */
1034 + void __iomem *cm; /* Clock Management */
1035 + void __iomem *cm2;
1036 +};
1037 +
1038 +void omap2_set_globals_242x(void);
1039 +void omap2_set_globals_243x(void);
1040 +void omap2_set_globals_343x(void);
1041 +void omap2_set_globals_443x(void);
1042 +
1043 +/* These get called from omap2_set_globals_xxxx(), do not call these */
1044 +void omap2_set_globals_tap(struct omap_globals *);
1045 +void omap2_set_globals_sdrc(struct omap_globals *);
1046 +void omap2_set_globals_control(struct omap_globals *);
1047 +void omap2_set_globals_prcm(struct omap_globals *);
1048 +
1049 +/**
1050 + * omap_test_timeout - busy-loop, testing a condition
1051 + * @cond: condition to test until it evaluates to true
1052 + * @timeout: maximum number of microseconds in the timeout
1053 + * @index: loop index (integer)
1054 + *
1055 + * Loop waiting for @cond to become true or until at least @timeout
1056 + * microseconds have passed. To use, define some integer @index in the
1057 + * calling code. After running, if @index == @timeout, then the loop has
1058 + * timed out.
1059 + */
1060 +#define omap_test_timeout(cond, timeout, index) \
1061 +({ \
1062 + for (index = 0; index < timeout; index++) { \
1063 + if (cond) \
1064 + break; \
1065 + udelay(1); \
1066 + } \
1067 +})
1068 +
1069 +#endif /* __ARCH_ARM_MACH_OMAP_COMMON_H */
1070 Index: linux-2.6.35/arch/arm/plat-omap/include/mach/control.h
1071 ===================================================================
1072 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
1073 +++ linux-2.6.35/arch/arm/plat-omap/include/mach/control.h 2010-08-08 12:56:44.000000000 +0200
1074 @@ -0,0 +1,325 @@
1075 +/*
1076 + * arch/arm/plat-omap/include/mach/control.h
1077 + *
1078 + * OMAP2/3/4 System Control Module definitions
1079 + *
1080 + * Copyright (C) 2007-2009 Texas Instruments, Inc.
1081 + * Copyright (C) 2007-2008 Nokia Corporation
1082 + *
1083 + * Written by Paul Walmsley
1084 + *
1085 + * This program is free software; you can redistribute it and/or modify
1086 + * it under the terms of the GNU General Public License as published by
1087 + * the Free Software Foundation.
1088 + */
1089 +
1090 +#ifndef __ASM_ARCH_CONTROL_H
1091 +#define __ASM_ARCH_CONTROL_H
1092 +
1093 +#include <mach/io.h>
1094 +
1095 +#ifndef __ASSEMBLY__
1096 +#define OMAP242X_CTRL_REGADDR(reg) \
1097 + OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
1098 +#define OMAP243X_CTRL_REGADDR(reg) \
1099 + OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
1100 +#define OMAP343X_CTRL_REGADDR(reg) \
1101 + OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
1102 +#else
1103 +#define OMAP242X_CTRL_REGADDR(reg) \
1104 + OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
1105 +#define OMAP243X_CTRL_REGADDR(reg) \
1106 + OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
1107 +#define OMAP343X_CTRL_REGADDR(reg) \
1108 + OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
1109 +#endif /* __ASSEMBLY__ */
1110 +
1111 +/*
1112 + * As elsewhere, the "OMAP2_" prefix indicates that the macro is valid for
1113 + * OMAP24XX and OMAP34XX.
1114 + */
1115 +
1116 +/* Control submodule offsets */
1117 +
1118 +#define OMAP2_CONTROL_INTERFACE 0x000
1119 +#define OMAP2_CONTROL_PADCONFS 0x030
1120 +#define OMAP2_CONTROL_GENERAL 0x270
1121 +#define OMAP343X_CONTROL_MEM_WKUP 0x600
1122 +#define OMAP343X_CONTROL_PADCONFS_WKUP 0xa00
1123 +#define OMAP343X_CONTROL_GENERAL_WKUP 0xa60
1124 +
1125 +/* Control register offsets - read/write with omap_ctrl_{read,write}{bwl}() */
1126 +
1127 +#define OMAP2_CONTROL_SYSCONFIG (OMAP2_CONTROL_INTERFACE + 0x10)
1128 +
1129 +/* CONTROL_GENERAL register offsets common to OMAP2 & 3 */
1130 +#define OMAP2_CONTROL_DEVCONF0 (OMAP2_CONTROL_GENERAL + 0x0004)
1131 +#define OMAP2_CONTROL_MSUSPENDMUX_0 (OMAP2_CONTROL_GENERAL + 0x0020)
1132 +#define OMAP2_CONTROL_MSUSPENDMUX_1 (OMAP2_CONTROL_GENERAL + 0x0024)
1133 +#define OMAP2_CONTROL_MSUSPENDMUX_2 (OMAP2_CONTROL_GENERAL + 0x0028)
1134 +#define OMAP2_CONTROL_MSUSPENDMUX_3 (OMAP2_CONTROL_GENERAL + 0x002c)
1135 +#define OMAP2_CONTROL_MSUSPENDMUX_4 (OMAP2_CONTROL_GENERAL + 0x0030)
1136 +#define OMAP2_CONTROL_MSUSPENDMUX_5 (OMAP2_CONTROL_GENERAL + 0x0034)
1137 +#define OMAP2_CONTROL_SEC_CTRL (OMAP2_CONTROL_GENERAL + 0x0040)
1138 +#define OMAP2_CONTROL_RPUB_KEY_H_0 (OMAP2_CONTROL_GENERAL + 0x0090)
1139 +#define OMAP2_CONTROL_RPUB_KEY_H_1 (OMAP2_CONTROL_GENERAL + 0x0094)
1140 +#define OMAP2_CONTROL_RPUB_KEY_H_2 (OMAP2_CONTROL_GENERAL + 0x0098)
1141 +#define OMAP2_CONTROL_RPUB_KEY_H_3 (OMAP2_CONTROL_GENERAL + 0x009c)
1142 +
1143 +/* 242x-only CONTROL_GENERAL register offsets */
1144 +#define OMAP242X_CONTROL_DEVCONF OMAP2_CONTROL_DEVCONF0 /* match TRM */
1145 +#define OMAP242X_CONTROL_OCM_RAM_PERM (OMAP2_CONTROL_GENERAL + 0x0068)
1146 +
1147 +/* 243x-only CONTROL_GENERAL register offsets */
1148 +/* CONTROL_IVA2_BOOT{ADDR,MOD} are at the same place on 343x - noted below */
1149 +#define OMAP243X_CONTROL_DEVCONF1 (OMAP2_CONTROL_GENERAL + 0x0078)
1150 +#define OMAP243X_CONTROL_CSIRXFE (OMAP2_CONTROL_GENERAL + 0x007c)
1151 +#define OMAP243X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190)
1152 +#define OMAP243X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194)
1153 +#define OMAP243X_CONTROL_IVA2_GEMCFG (OMAP2_CONTROL_GENERAL + 0x0198)
1154 +#define OMAP243X_CONTROL_PBIAS_LITE (OMAP2_CONTROL_GENERAL + 0x0230)
1155 +
1156 +/* 24xx-only CONTROL_GENERAL register offsets */
1157 +#define OMAP24XX_CONTROL_DEBOBS (OMAP2_CONTROL_GENERAL + 0x0000)
1158 +#define OMAP24XX_CONTROL_EMU_SUPPORT (OMAP2_CONTROL_GENERAL + 0x0008)
1159 +#define OMAP24XX_CONTROL_SEC_TEST (OMAP2_CONTROL_GENERAL + 0x0044)
1160 +#define OMAP24XX_CONTROL_PSA_CTRL (OMAP2_CONTROL_GENERAL + 0x0048)
1161 +#define OMAP24XX_CONTROL_PSA_CMD (OMAP2_CONTROL_GENERAL + 0x004c)
1162 +#define OMAP24XX_CONTROL_PSA_VALUE (OMAP2_CONTROL_GENERAL + 0x0050)
1163 +#define OMAP24XX_CONTROL_SEC_EMU (OMAP2_CONTROL_GENERAL + 0x0060)
1164 +#define OMAP24XX_CONTROL_SEC_TAP (OMAP2_CONTROL_GENERAL + 0x0064)
1165 +#define OMAP24XX_CONTROL_OCM_PUB_RAM_ADD (OMAP2_CONTROL_GENERAL + 0x006c)
1166 +#define OMAP24XX_CONTROL_EXT_SEC_RAM_START_ADD (OMAP2_CONTROL_GENERAL + 0x0070)
1167 +#define OMAP24XX_CONTROL_EXT_SEC_RAM_STOP_ADD (OMAP2_CONTROL_GENERAL + 0x0074)
1168 +#define OMAP24XX_CONTROL_SEC_STATUS (OMAP2_CONTROL_GENERAL + 0x0080)
1169 +#define OMAP24XX_CONTROL_SEC_ERR_STATUS (OMAP2_CONTROL_GENERAL + 0x0084)
1170 +#define OMAP24XX_CONTROL_STATUS (OMAP2_CONTROL_GENERAL + 0x0088)
1171 +#define OMAP24XX_CONTROL_GENERAL_PURPOSE_STATUS (OMAP2_CONTROL_GENERAL + 0x008c)
1172 +#define OMAP24XX_CONTROL_RAND_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00a0)
1173 +#define OMAP24XX_CONTROL_RAND_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00a4)
1174 +#define OMAP24XX_CONTROL_RAND_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00a8)
1175 +#define OMAP24XX_CONTROL_RAND_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00ac)
1176 +#define OMAP24XX_CONTROL_CUST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00b0)
1177 +#define OMAP24XX_CONTROL_CUST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00b4)
1178 +#define OMAP24XX_CONTROL_TEST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00c0)
1179 +#define OMAP24XX_CONTROL_TEST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00c4)
1180 +#define OMAP24XX_CONTROL_TEST_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00c8)
1181 +#define OMAP24XX_CONTROL_TEST_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00cc)
1182 +#define OMAP24XX_CONTROL_TEST_KEY_4 (OMAP2_CONTROL_GENERAL + 0x00d0)
1183 +#define OMAP24XX_CONTROL_TEST_KEY_5 (OMAP2_CONTROL_GENERAL + 0x00d4)
1184 +#define OMAP24XX_CONTROL_TEST_KEY_6 (OMAP2_CONTROL_GENERAL + 0x00d8)
1185 +#define OMAP24XX_CONTROL_TEST_KEY_7 (OMAP2_CONTROL_GENERAL + 0x00dc)
1186 +#define OMAP24XX_CONTROL_TEST_KEY_8 (OMAP2_CONTROL_GENERAL + 0x00e0)
1187 +#define OMAP24XX_CONTROL_TEST_KEY_9 (OMAP2_CONTROL_GENERAL + 0x00e4)
1188 +
1189 +#define OMAP343X_CONTROL_PADCONF_SYSNIRQ (OMAP2_CONTROL_INTERFACE + 0x01b0)
1190 +
1191 +/* 34xx-only CONTROL_GENERAL register offsets */
1192 +#define OMAP343X_CONTROL_PADCONF_OFF (OMAP2_CONTROL_GENERAL + 0x0000)
1193 +#define OMAP343X_CONTROL_MEM_DFTRW0 (OMAP2_CONTROL_GENERAL + 0x0008)
1194 +#define OMAP343X_CONTROL_MEM_DFTRW1 (OMAP2_CONTROL_GENERAL + 0x000c)
1195 +#define OMAP343X_CONTROL_DEVCONF1 (OMAP2_CONTROL_GENERAL + 0x0068)
1196 +#define OMAP343X_CONTROL_CSIRXFE (OMAP2_CONTROL_GENERAL + 0x006c)
1197 +#define OMAP343X_CONTROL_SEC_STATUS (OMAP2_CONTROL_GENERAL + 0x0070)
1198 +#define OMAP343X_CONTROL_SEC_ERR_STATUS (OMAP2_CONTROL_GENERAL + 0x0074)
1199 +#define OMAP343X_CONTROL_SEC_ERR_STATUS_DEBUG (OMAP2_CONTROL_GENERAL + 0x0078)
1200 +#define OMAP343X_CONTROL_STATUS (OMAP2_CONTROL_GENERAL + 0x0080)
1201 +#define OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS (OMAP2_CONTROL_GENERAL + 0x0084)
1202 +#define OMAP343X_CONTROL_RPUB_KEY_H_4 (OMAP2_CONTROL_GENERAL + 0x00a0)
1203 +#define OMAP343X_CONTROL_RAND_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00a8)
1204 +#define OMAP343X_CONTROL_RAND_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00ac)
1205 +#define OMAP343X_CONTROL_RAND_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00b0)
1206 +#define OMAP343X_CONTROL_RAND_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00b4)
1207 +#define OMAP343X_CONTROL_TEST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00c8)
1208 +#define OMAP343X_CONTROL_TEST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00cc)
1209 +#define OMAP343X_CONTROL_TEST_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00d0)
1210 +#define OMAP343X_CONTROL_TEST_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00d4)
1211 +#define OMAP343X_CONTROL_TEST_KEY_4 (OMAP2_CONTROL_GENERAL + 0x00d8)
1212 +#define OMAP343X_CONTROL_TEST_KEY_5 (OMAP2_CONTROL_GENERAL + 0x00dc)
1213 +#define OMAP343X_CONTROL_TEST_KEY_6 (OMAP2_CONTROL_GENERAL + 0x00e0)
1214 +#define OMAP343X_CONTROL_TEST_KEY_7 (OMAP2_CONTROL_GENERAL + 0x00e4)
1215 +#define OMAP343X_CONTROL_TEST_KEY_8 (OMAP2_CONTROL_GENERAL + 0x00e8)
1216 +#define OMAP343X_CONTROL_TEST_KEY_9 (OMAP2_CONTROL_GENERAL + 0x00ec)
1217 +#define OMAP343X_CONTROL_TEST_KEY_10 (OMAP2_CONTROL_GENERAL + 0x00f0)
1218 +#define OMAP343X_CONTROL_TEST_KEY_11 (OMAP2_CONTROL_GENERAL + 0x00f4)
1219 +#define OMAP343X_CONTROL_TEST_KEY_12 (OMAP2_CONTROL_GENERAL + 0x00f8)
1220 +#define OMAP343X_CONTROL_TEST_KEY_13 (OMAP2_CONTROL_GENERAL + 0x00fc)
1221 +#define OMAP343X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190)
1222 +#define OMAP343X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194)
1223 +#define OMAP343X_CONTROL_DEBOBS(i) (OMAP2_CONTROL_GENERAL + 0x01B0 \
1224 + + ((i) >> 1) * 4 + (!(i) & 1) * 2)
1225 +#define OMAP343X_CONTROL_PROG_IO0 (OMAP2_CONTROL_GENERAL + 0x01D4)
1226 +#define OMAP343X_CONTROL_PROG_IO1 (OMAP2_CONTROL_GENERAL + 0x01D8)
1227 +#define OMAP343X_CONTROL_DSS_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01E0)
1228 +#define OMAP343X_CONTROL_CORE_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01E4)
1229 +#define OMAP343X_CONTROL_PER_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01E8)
1230 +#define OMAP343X_CONTROL_USBHOST_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01EC)
1231 +#define OMAP343X_CONTROL_PBIAS_LITE (OMAP2_CONTROL_GENERAL + 0x02B0)
1232 +#define OMAP343X_CONTROL_TEMP_SENSOR (OMAP2_CONTROL_GENERAL + 0x02B4)
1233 +#define OMAP343X_CONTROL_SRAMLDO4 (OMAP2_CONTROL_GENERAL + 0x02B8)
1234 +#define OMAP343X_CONTROL_SRAMLDO5 (OMAP2_CONTROL_GENERAL + 0x02C0)
1235 +#define OMAP343X_CONTROL_CSI (OMAP2_CONTROL_GENERAL + 0x02C4)
1236 +
1237 +
1238 +/* 34xx PADCONF register offsets */
1239 +#define OMAP343X_PADCONF_ETK(i) (OMAP2_CONTROL_PADCONFS + 0x5a8 + \
1240 + (i)*2)
1241 +#define OMAP343X_PADCONF_ETK_CLK OMAP343X_PADCONF_ETK(0)
1242 +#define OMAP343X_PADCONF_ETK_CTL OMAP343X_PADCONF_ETK(1)
1243 +#define OMAP343X_PADCONF_ETK_D0 OMAP343X_PADCONF_ETK(2)
1244 +#define OMAP343X_PADCONF_ETK_D1 OMAP343X_PADCONF_ETK(3)
1245 +#define OMAP343X_PADCONF_ETK_D2 OMAP343X_PADCONF_ETK(4)
1246 +#define OMAP343X_PADCONF_ETK_D3 OMAP343X_PADCONF_ETK(5)
1247 +#define OMAP343X_PADCONF_ETK_D4 OMAP343X_PADCONF_ETK(6)
1248 +#define OMAP343X_PADCONF_ETK_D5 OMAP343X_PADCONF_ETK(7)
1249 +#define OMAP343X_PADCONF_ETK_D6 OMAP343X_PADCONF_ETK(8)
1250 +#define OMAP343X_PADCONF_ETK_D7 OMAP343X_PADCONF_ETK(9)
1251 +#define OMAP343X_PADCONF_ETK_D8 OMAP343X_PADCONF_ETK(10)
1252 +#define OMAP343X_PADCONF_ETK_D9 OMAP343X_PADCONF_ETK(11)
1253 +#define OMAP343X_PADCONF_ETK_D10 OMAP343X_PADCONF_ETK(12)
1254 +#define OMAP343X_PADCONF_ETK_D11 OMAP343X_PADCONF_ETK(13)
1255 +#define OMAP343X_PADCONF_ETK_D12 OMAP343X_PADCONF_ETK(14)
1256 +#define OMAP343X_PADCONF_ETK_D13 OMAP343X_PADCONF_ETK(15)
1257 +#define OMAP343X_PADCONF_ETK_D14 OMAP343X_PADCONF_ETK(16)
1258 +#define OMAP343X_PADCONF_ETK_D15 OMAP343X_PADCONF_ETK(17)
1259 +
1260 +/* 34xx GENERAL_WKUP regist offsets */
1261 +#define OMAP343X_CONTROL_WKUP_DEBOBSMUX(i) (OMAP343X_CONTROL_GENERAL_WKUP + \
1262 + 0x008 + (i))
1263 +#define OMAP343X_CONTROL_WKUP_DEBOBS0 (OMAP343X_CONTROL_GENERAL_WKUP + 0x008)
1264 +#define OMAP343X_CONTROL_WKUP_DEBOBS1 (OMAP343X_CONTROL_GENERAL_WKUP + 0x00C)
1265 +#define OMAP343X_CONTROL_WKUP_DEBOBS2 (OMAP343X_CONTROL_GENERAL_WKUP + 0x010)
1266 +#define OMAP343X_CONTROL_WKUP_DEBOBS3 (OMAP343X_CONTROL_GENERAL_WKUP + 0x014)
1267 +#define OMAP343X_CONTROL_WKUP_DEBOBS4 (OMAP343X_CONTROL_GENERAL_WKUP + 0x018)
1268 +
1269 +/* 34xx D2D idle-related pins, handled by PM core */
1270 +#define OMAP3_PADCONF_SAD2D_MSTANDBY 0x250
1271 +#define OMAP3_PADCONF_SAD2D_IDLEACK 0x254
1272 +
1273 +/*
1274 + * REVISIT: This list of registers is not comprehensive - there are more
1275 + * that should be added.
1276 + */
1277 +
1278 +/*
1279 + * Control module register bit defines - these should eventually go into
1280 + * their own regbits file. Some of these will be complicated, depending
1281 + * on the device type (general-purpose, emulator, test, secure, bad, other)
1282 + * and the security mode (secure, non-secure, don't care)
1283 + */
1284 +/* CONTROL_DEVCONF0 bits */
1285 +#define OMAP2_MMCSDIO1ADPCLKISEL (1 << 24) /* MMC1 loop back clock */
1286 +#define OMAP24XX_USBSTANDBYCTRL (1 << 15)
1287 +#define OMAP2_MCBSP2_CLKS_MASK (1 << 6)
1288 +#define OMAP2_MCBSP1_CLKS_MASK (1 << 2)
1289 +
1290 +/* CONTROL_DEVCONF1 bits */
1291 +#define OMAP243X_MMC1_ACTIVE_OVERWRITE (1 << 31)
1292 +#define OMAP2_MMCSDIO2ADPCLKISEL (1 << 6) /* MMC2 loop back clock */
1293 +#define OMAP2_MCBSP5_CLKS_MASK (1 << 4) /* > 242x */
1294 +#define OMAP2_MCBSP4_CLKS_MASK (1 << 2) /* > 242x */
1295 +#define OMAP2_MCBSP3_CLKS_MASK (1 << 0) /* > 242x */
1296 +
1297 +/* CONTROL_STATUS bits */
1298 +#define OMAP2_DEVICETYPE_MASK (0x7 << 8)
1299 +#define OMAP2_SYSBOOT_5_MASK (1 << 5)
1300 +#define OMAP2_SYSBOOT_4_MASK (1 << 4)
1301 +#define OMAP2_SYSBOOT_3_MASK (1 << 3)
1302 +#define OMAP2_SYSBOOT_2_MASK (1 << 2)
1303 +#define OMAP2_SYSBOOT_1_MASK (1 << 1)
1304 +#define OMAP2_SYSBOOT_0_MASK (1 << 0)
1305 +
1306 +/* CONTROL_PBIAS_LITE bits */
1307 +#define OMAP343X_PBIASLITESUPPLY_HIGH1 (1 << 15)
1308 +#define OMAP343X_PBIASLITEVMODEERROR1 (1 << 11)
1309 +#define OMAP343X_PBIASSPEEDCTRL1 (1 << 10)
1310 +#define OMAP343X_PBIASLITEPWRDNZ1 (1 << 9)
1311 +#define OMAP343X_PBIASLITEVMODE1 (1 << 8)
1312 +#define OMAP343X_PBIASLITESUPPLY_HIGH0 (1 << 7)
1313 +#define OMAP343X_PBIASLITEVMODEERROR0 (1 << 3)
1314 +#define OMAP2_PBIASSPEEDCTRL0 (1 << 2)
1315 +#define OMAP2_PBIASLITEPWRDNZ0 (1 << 1)
1316 +#define OMAP2_PBIASLITEVMODE0 (1 << 0)
1317 +
1318 +/* CONTROL_PROG_IO1 bits */
1319 +#define OMAP3630_PRG_SDMMC1_SPEEDCTRL (1 << 20)
1320 +
1321 +/* CONTROL_IVA2_BOOTMOD bits */
1322 +#define OMAP3_IVA2_BOOTMOD_SHIFT 0
1323 +#define OMAP3_IVA2_BOOTMOD_MASK (0xf << 0)
1324 +#define OMAP3_IVA2_BOOTMOD_IDLE (0x1 << 0)
1325 +
1326 +/* CONTROL_PADCONF_X bits */
1327 +#define OMAP3_PADCONF_WAKEUPEVENT0 (1 << 15)
1328 +#define OMAP3_PADCONF_WAKEUPENABLE0 (1 << 14)
1329 +
1330 +#define OMAP343X_SCRATCHPAD_ROM (OMAP343X_CTRL_BASE + 0x860)
1331 +#define OMAP343X_SCRATCHPAD (OMAP343X_CTRL_BASE + 0x910)
1332 +#define OMAP343X_SCRATCHPAD_ROM_OFFSET 0x19C
1333 +
1334 +/*
1335 + * CONTROL OMAP STATUS register to identify OMAP3 features
1336 + */
1337 +#define OMAP3_CONTROL_OMAP_STATUS 0x044c
1338 +
1339 +#define OMAP3_SGX_SHIFT 13
1340 +#define OMAP3_SGX_MASK (3 << OMAP3_SGX_SHIFT)
1341 +#define FEAT_SGX_FULL 0
1342 +#define FEAT_SGX_HALF 1
1343 +#define FEAT_SGX_NONE 2
1344 +
1345 +#define OMAP3_IVA_SHIFT 12
1346 +#define OMAP3_IVA_MASK (1 << OMAP3_SGX_SHIFT)
1347 +#define FEAT_IVA 0
1348 +#define FEAT_IVA_NONE 1
1349 +
1350 +#define OMAP3_L2CACHE_SHIFT 10
1351 +#define OMAP3_L2CACHE_MASK (3 << OMAP3_L2CACHE_SHIFT)
1352 +#define FEAT_L2CACHE_NONE 0
1353 +#define FEAT_L2CACHE_64KB 1
1354 +#define FEAT_L2CACHE_128KB 2
1355 +#define FEAT_L2CACHE_256KB 3
1356 +
1357 +#define OMAP3_ISP_SHIFT 5
1358 +#define OMAP3_ISP_MASK (1<< OMAP3_ISP_SHIFT)
1359 +#define FEAT_ISP 0
1360 +#define FEAT_ISP_NONE 1
1361 +
1362 +#define OMAP3_NEON_SHIFT 4
1363 +#define OMAP3_NEON_MASK (1<< OMAP3_NEON_SHIFT)
1364 +#define FEAT_NEON 0
1365 +#define FEAT_NEON_NONE 1
1366 +
1367 +
1368 +#ifndef __ASSEMBLY__
1369 +#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
1370 + defined(CONFIG_ARCH_OMAP4)
1371 +extern void __iomem *omap_ctrl_base_get(void);
1372 +extern u8 omap_ctrl_readb(u16 offset);
1373 +extern u16 omap_ctrl_readw(u16 offset);
1374 +extern u32 omap_ctrl_readl(u16 offset);
1375 +extern void omap_ctrl_writeb(u8 val, u16 offset);
1376 +extern void omap_ctrl_writew(u16 val, u16 offset);
1377 +extern void omap_ctrl_writel(u32 val, u16 offset);
1378 +
1379 +extern void omap3_save_scratchpad_contents(void);
1380 +extern void omap3_clear_scratchpad_contents(void);
1381 +extern u32 *get_restore_pointer(void);
1382 +extern u32 *get_es3_restore_pointer(void);
1383 +extern u32 omap3_arm_context[128];
1384 +extern void omap3_control_save_context(void);
1385 +extern void omap3_control_restore_context(void);
1386 +
1387 +#else
1388 +#define omap_ctrl_base_get() 0
1389 +#define omap_ctrl_readb(x) 0
1390 +#define omap_ctrl_readw(x) 0
1391 +#define omap_ctrl_readl(x) 0
1392 +#define omap_ctrl_writeb(x, y) WARN_ON(1)
1393 +#define omap_ctrl_writew(x, y) WARN_ON(1)
1394 +#define omap_ctrl_writel(x, y) WARN_ON(1)
1395 +#endif
1396 +#endif /* __ASSEMBLY__ */
1397 +
1398 +#endif /* __ASM_ARCH_CONTROL_H */
1399 +
1400 Index: linux-2.6.35/arch/arm/plat-omap/include/mach/cpu.h
1401 ===================================================================
1402 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
1403 +++ linux-2.6.35/arch/arm/plat-omap/include/mach/cpu.h 2010-08-08 12:56:44.000000000 +0200
1404 @@ -0,0 +1,516 @@
1405 +/*
1406 + * arch/arm/plat-omap/include/mach/cpu.h
1407 + *
1408 + * OMAP cpu type detection
1409 + *
1410 + * Copyright (C) 2004, 2008 Nokia Corporation
1411 + *
1412 + * Copyright (C) 2009 Texas Instruments.
1413 + *
1414 + * Written by Tony Lindgren <tony.lindgren@nokia.com>
1415 + *
1416 + * Added OMAP4 specific defines - Santosh Shilimkar<santosh.shilimkar@ti.com>
1417 + *
1418 + * This program is free software; you can redistribute it and/or modify
1419 + * it under the terms of the GNU General Public License as published by
1420 + * the Free Software Foundation; either version 2 of the License, or
1421 + * (at your option) any later version.
1422 + *
1423 + * This program is distributed in the hope that it will be useful,
1424 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1425 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1426 + * GNU General Public License for more details.
1427 + *
1428 + * You should have received a copy of the GNU General Public License
1429 + * along with this program; if not, write to the Free Software
1430 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
1431 + *
1432 + */
1433 +
1434 +#ifndef __ASM_ARCH_OMAP_CPU_H
1435 +#define __ASM_ARCH_OMAP_CPU_H
1436 +
1437 +#include <linux/bitops.h>
1438 +
1439 +/*
1440 + * Omap device type i.e. EMU/HS/TST/GP/BAD
1441 + */
1442 +#define OMAP2_DEVICE_TYPE_TEST 0
1443 +#define OMAP2_DEVICE_TYPE_EMU 1
1444 +#define OMAP2_DEVICE_TYPE_SEC 2
1445 +#define OMAP2_DEVICE_TYPE_GP 3
1446 +#define OMAP2_DEVICE_TYPE_BAD 4
1447 +
1448 +int omap_type(void);
1449 +
1450 +struct omap_chip_id {
1451 + u8 oc;
1452 + u8 type;
1453 +};
1454 +
1455 +#define OMAP_CHIP_INIT(x) { .oc = x }
1456 +
1457 +/*
1458 + * omap_rev bits:
1459 + * CPU id bits (0730, 1510, 1710, 2422...) [31:16]
1460 + * CPU revision (See _REV_ defined in cpu.h) [15:08]
1461 + * CPU class bits (15xx, 16xx, 24xx, 34xx...) [07:00]
1462 + */
1463 +unsigned int omap_rev(void);
1464 +
1465 +/*
1466 + * Define CPU revision bits
1467 + *
1468 + * Verbose meaning of the revision bits may be different for a silicon
1469 + * family. This difference can be handled separately.
1470 + */
1471 +#define OMAP_REVBITS_00 0x00
1472 +#define OMAP_REVBITS_10 0x10
1473 +#define OMAP_REVBITS_20 0x20
1474 +#define OMAP_REVBITS_30 0x30
1475 +#define OMAP_REVBITS_40 0x40
1476 +
1477 +/*
1478 + * Get the CPU revision for OMAP devices
1479 + */
1480 +#define GET_OMAP_REVISION() ((omap_rev() >> 8) & 0xff)
1481 +
1482 +/*
1483 + * Test if multicore OMAP support is needed
1484 + */
1485 +#undef MULTI_OMAP1
1486 +#undef MULTI_OMAP2
1487 +#undef OMAP_NAME
1488 +
1489 +#ifdef CONFIG_ARCH_OMAP730
1490 +# ifdef OMAP_NAME
1491 +# undef MULTI_OMAP1
1492 +# define MULTI_OMAP1
1493 +# else
1494 +# define OMAP_NAME omap730
1495 +# endif
1496 +#endif
1497 +#ifdef CONFIG_ARCH_OMAP850
1498 +# ifdef OMAP_NAME
1499 +# undef MULTI_OMAP1
1500 +# define MULTI_OMAP1
1501 +# else
1502 +# define OMAP_NAME omap850
1503 +# endif
1504 +#endif
1505 +#ifdef CONFIG_ARCH_OMAP15XX
1506 +# ifdef OMAP_NAME
1507 +# undef MULTI_OMAP1
1508 +# define MULTI_OMAP1
1509 +# else
1510 +# define OMAP_NAME omap1510
1511 +# endif
1512 +#endif
1513 +#ifdef CONFIG_ARCH_OMAP16XX
1514 +# ifdef OMAP_NAME
1515 +# undef MULTI_OMAP1
1516 +# define MULTI_OMAP1
1517 +# else
1518 +# define OMAP_NAME omap16xx
1519 +# endif
1520 +#endif
1521 +#if (defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX))
1522 +# if (defined(OMAP_NAME) || defined(MULTI_OMAP1))
1523 +# error "OMAP1 and OMAP2 can't be selected at the same time"
1524 +# endif
1525 +#endif
1526 +#ifdef CONFIG_ARCH_OMAP2420
1527 +# ifdef OMAP_NAME
1528 +# undef MULTI_OMAP2
1529 +# define MULTI_OMAP2
1530 +# else
1531 +# define OMAP_NAME omap2420
1532 +# endif
1533 +#endif
1534 +#ifdef CONFIG_ARCH_OMAP2430
1535 +# ifdef OMAP_NAME
1536 +# undef MULTI_OMAP2
1537 +# define MULTI_OMAP2
1538 +# else
1539 +# define OMAP_NAME omap2430
1540 +# endif
1541 +#endif
1542 +#ifdef CONFIG_ARCH_OMAP3430
1543 +# ifdef OMAP_NAME
1544 +# undef MULTI_OMAP2
1545 +# define MULTI_OMAP2
1546 +# else
1547 +# define OMAP_NAME omap3430
1548 +# endif
1549 +#endif
1550 +
1551 +/*
1552 + * Macros to group OMAP into cpu classes.
1553 + * These can be used in most places.
1554 + * cpu_is_omap7xx(): True for OMAP730, OMAP850
1555 + * cpu_is_omap15xx(): True for OMAP1510, OMAP5910 and OMAP310
1556 + * cpu_is_omap16xx(): True for OMAP1610, OMAP5912 and OMAP1710
1557 + * cpu_is_omap24xx(): True for OMAP2420, OMAP2422, OMAP2423, OMAP2430
1558 + * cpu_is_omap242x(): True for OMAP2420, OMAP2422, OMAP2423
1559 + * cpu_is_omap243x(): True for OMAP2430
1560 + * cpu_is_omap343x(): True for OMAP3430
1561 + */
1562 +#define GET_OMAP_CLASS (omap_rev() & 0xff)
1563 +
1564 +#define IS_OMAP_CLASS(class, id) \
1565 +static inline int is_omap ##class (void) \
1566 +{ \
1567 + return (GET_OMAP_CLASS == (id)) ? 1 : 0; \
1568 +}
1569 +
1570 +#define GET_OMAP_SUBCLASS ((omap_rev() >> 20) & 0x0fff)
1571 +
1572 +#define IS_OMAP_SUBCLASS(subclass, id) \
1573 +static inline int is_omap ##subclass (void) \
1574 +{ \
1575 + return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0; \
1576 +}
1577 +
1578 +IS_OMAP_CLASS(7xx, 0x07)
1579 +IS_OMAP_CLASS(15xx, 0x15)
1580 +IS_OMAP_CLASS(16xx, 0x16)
1581 +IS_OMAP_CLASS(24xx, 0x24)
1582 +IS_OMAP_CLASS(34xx, 0x34)
1583 +IS_OMAP_CLASS(44xx, 0x44)
1584 +
1585 +IS_OMAP_SUBCLASS(242x, 0x242)
1586 +IS_OMAP_SUBCLASS(243x, 0x243)
1587 +IS_OMAP_SUBCLASS(343x, 0x343)
1588 +IS_OMAP_SUBCLASS(363x, 0x363)
1589 +IS_OMAP_SUBCLASS(443x, 0x443)
1590 +
1591 +#define cpu_is_omap7xx() 0
1592 +#define cpu_is_omap15xx() 0
1593 +#define cpu_is_omap16xx() 0
1594 +#define cpu_is_omap24xx() 0
1595 +#define cpu_is_omap242x() 0
1596 +#define cpu_is_omap243x() 0
1597 +#define cpu_is_omap34xx() 0
1598 +#define cpu_is_omap343x() 0
1599 +#define cpu_is_omap44xx() 0
1600 +#define cpu_is_omap443x() 0
1601 +
1602 +#if defined(MULTI_OMAP1)
1603 +# if defined(CONFIG_ARCH_OMAP730)
1604 +# undef cpu_is_omap7xx
1605 +# define cpu_is_omap7xx() is_omap7xx()
1606 +# endif
1607 +# if defined(CONFIG_ARCH_OMAP850)
1608 +# undef cpu_is_omap7xx
1609 +# define cpu_is_omap7xx() is_omap7xx()
1610 +# endif
1611 +# if defined(CONFIG_ARCH_OMAP15XX)
1612 +# undef cpu_is_omap15xx
1613 +# define cpu_is_omap15xx() is_omap15xx()
1614 +# endif
1615 +# if defined(CONFIG_ARCH_OMAP16XX)
1616 +# undef cpu_is_omap16xx
1617 +# define cpu_is_omap16xx() is_omap16xx()
1618 +# endif
1619 +#else
1620 +# if defined(CONFIG_ARCH_OMAP730)
1621 +# undef cpu_is_omap7xx
1622 +# define cpu_is_omap7xx() 1
1623 +# endif
1624 +# if defined(CONFIG_ARCH_OMAP850)
1625 +# undef cpu_is_omap7xx
1626 +# define cpu_is_omap7xx() 1
1627 +# endif
1628 +# if defined(CONFIG_ARCH_OMAP15XX)
1629 +# undef cpu_is_omap15xx
1630 +# define cpu_is_omap15xx() 1
1631 +# endif
1632 +# if defined(CONFIG_ARCH_OMAP16XX)
1633 +# undef cpu_is_omap16xx
1634 +# define cpu_is_omap16xx() 1
1635 +# endif
1636 +#endif
1637 +
1638 +#if defined(MULTI_OMAP2)
1639 +# if defined(CONFIG_ARCH_OMAP24XX)
1640 +# undef cpu_is_omap24xx
1641 +# undef cpu_is_omap242x
1642 +# undef cpu_is_omap243x
1643 +# define cpu_is_omap24xx() is_omap24xx()
1644 +# define cpu_is_omap242x() is_omap242x()
1645 +# define cpu_is_omap243x() is_omap243x()
1646 +# endif
1647 +# if defined(CONFIG_ARCH_OMAP34XX)
1648 +# undef cpu_is_omap34xx
1649 +# undef cpu_is_omap343x
1650 +# define cpu_is_omap34xx() is_omap34xx()
1651 +# define cpu_is_omap343x() is_omap343x()
1652 +# endif
1653 +#else
1654 +# if defined(CONFIG_ARCH_OMAP24XX)
1655 +# undef cpu_is_omap24xx
1656 +# define cpu_is_omap24xx() 1
1657 +# endif
1658 +# if defined(CONFIG_ARCH_OMAP2420)
1659 +# undef cpu_is_omap242x
1660 +# define cpu_is_omap242x() 1
1661 +# endif
1662 +# if defined(CONFIG_ARCH_OMAP2430)
1663 +# undef cpu_is_omap243x
1664 +# define cpu_is_omap243x() 1
1665 +# endif
1666 +# if defined(CONFIG_ARCH_OMAP34XX)
1667 +# undef cpu_is_omap34xx
1668 +# define cpu_is_omap34xx() 1
1669 +# endif
1670 +# if defined(CONFIG_ARCH_OMAP3430)
1671 +# undef cpu_is_omap343x
1672 +# define cpu_is_omap343x() 1
1673 +# endif
1674 +#endif
1675 +
1676 +/*
1677 + * Macros to detect individual cpu types.
1678 + * These are only rarely needed.
1679 + * cpu_is_omap330(): True for OMAP330
1680 + * cpu_is_omap730(): True for OMAP730
1681 + * cpu_is_omap850(): True for OMAP850
1682 + * cpu_is_omap1510(): True for OMAP1510
1683 + * cpu_is_omap1610(): True for OMAP1610
1684 + * cpu_is_omap1611(): True for OMAP1611
1685 + * cpu_is_omap5912(): True for OMAP5912
1686 + * cpu_is_omap1621(): True for OMAP1621
1687 + * cpu_is_omap1710(): True for OMAP1710
1688 + * cpu_is_omap2420(): True for OMAP2420
1689 + * cpu_is_omap2422(): True for OMAP2422
1690 + * cpu_is_omap2423(): True for OMAP2423
1691 + * cpu_is_omap2430(): True for OMAP2430
1692 + * cpu_is_omap3430(): True for OMAP3430
1693 + * cpu_is_omap3505(): True for OMAP3505
1694 + * cpu_is_omap3517(): True for OMAP3517
1695 + */
1696 +#define GET_OMAP_TYPE ((omap_rev() >> 16) & 0xffff)
1697 +
1698 +#define IS_OMAP_TYPE(type, id) \
1699 +static inline int is_omap ##type (void) \
1700 +{ \
1701 + return (GET_OMAP_TYPE == (id)) ? 1 : 0; \
1702 +}
1703 +
1704 +IS_OMAP_TYPE(310, 0x0310)
1705 +IS_OMAP_TYPE(730, 0x0730)
1706 +IS_OMAP_TYPE(850, 0x0850)
1707 +IS_OMAP_TYPE(1510, 0x1510)
1708 +IS_OMAP_TYPE(1610, 0x1610)
1709 +IS_OMAP_TYPE(1611, 0x1611)
1710 +IS_OMAP_TYPE(5912, 0x1611)
1711 +IS_OMAP_TYPE(1621, 0x1621)
1712 +IS_OMAP_TYPE(1710, 0x1710)
1713 +IS_OMAP_TYPE(2420, 0x2420)
1714 +IS_OMAP_TYPE(2422, 0x2422)
1715 +IS_OMAP_TYPE(2423, 0x2423)
1716 +IS_OMAP_TYPE(2430, 0x2430)
1717 +IS_OMAP_TYPE(3430, 0x3430)
1718 +IS_OMAP_TYPE(3505, 0x3505)
1719 +IS_OMAP_TYPE(3517, 0x3517)
1720 +
1721 +#define cpu_is_omap310() 0
1722 +#define cpu_is_omap730() 0
1723 +#define cpu_is_omap850() 0
1724 +#define cpu_is_omap1510() 0
1725 +#define cpu_is_omap1610() 0
1726 +#define cpu_is_omap5912() 0
1727 +#define cpu_is_omap1611() 0
1728 +#define cpu_is_omap1621() 0
1729 +#define cpu_is_omap1710() 0
1730 +#define cpu_is_omap2420() 0
1731 +#define cpu_is_omap2422() 0
1732 +#define cpu_is_omap2423() 0
1733 +#define cpu_is_omap2430() 0
1734 +#define cpu_is_omap3503() 0
1735 +#define cpu_is_omap3515() 0
1736 +#define cpu_is_omap3525() 0
1737 +#define cpu_is_omap3530() 0
1738 +#define cpu_is_omap3505() 0
1739 +#define cpu_is_omap3517() 0
1740 +#define cpu_is_omap3430() 0
1741 +#define cpu_is_omap3630() 0
1742 +
1743 +/*
1744 + * Whether we have MULTI_OMAP1 or not, we still need to distinguish
1745 + * between 730 vs 850, 330 vs. 1510 and 1611B/5912 vs. 1710.
1746 + */
1747 +
1748 +#if defined(CONFIG_ARCH_OMAP730)
1749 +# undef cpu_is_omap730
1750 +# define cpu_is_omap730() is_omap730()
1751 +#endif
1752 +
1753 +#if defined(CONFIG_ARCH_OMAP850)
1754 +# undef cpu_is_omap850
1755 +# define cpu_is_omap850() is_omap850()
1756 +#endif
1757 +
1758 +#if defined(CONFIG_ARCH_OMAP15XX)
1759 +# undef cpu_is_omap310
1760 +# undef cpu_is_omap1510
1761 +# define cpu_is_omap310() is_omap310()
1762 +# define cpu_is_omap1510() is_omap1510()
1763 +#endif
1764 +
1765 +#if defined(CONFIG_ARCH_OMAP16XX)
1766 +# undef cpu_is_omap1610
1767 +# undef cpu_is_omap1611
1768 +# undef cpu_is_omap5912
1769 +# undef cpu_is_omap1621
1770 +# undef cpu_is_omap1710
1771 +# define cpu_is_omap1610() is_omap1610()
1772 +# define cpu_is_omap1611() is_omap1611()
1773 +# define cpu_is_omap5912() is_omap5912()
1774 +# define cpu_is_omap1621() is_omap1621()
1775 +# define cpu_is_omap1710() is_omap1710()
1776 +#endif
1777 +
1778 +#if defined(CONFIG_ARCH_OMAP24XX)
1779 +# undef cpu_is_omap2420
1780 +# undef cpu_is_omap2422
1781 +# undef cpu_is_omap2423
1782 +# undef cpu_is_omap2430
1783 +# define cpu_is_omap2420() is_omap2420()
1784 +# define cpu_is_omap2422() is_omap2422()
1785 +# define cpu_is_omap2423() is_omap2423()
1786 +# define cpu_is_omap2430() is_omap2430()
1787 +#endif
1788 +
1789 +#if defined(CONFIG_ARCH_OMAP34XX)
1790 +# undef cpu_is_omap3430
1791 +# undef cpu_is_omap3503
1792 +# undef cpu_is_omap3515
1793 +# undef cpu_is_omap3525
1794 +# undef cpu_is_omap3530
1795 +# undef cpu_is_omap3505
1796 +# undef cpu_is_omap3517
1797 +# define cpu_is_omap3430() is_omap3430()
1798 +# define cpu_is_omap3503() (cpu_is_omap3430() && \
1799 + (!omap3_has_iva()) && \
1800 + (!omap3_has_sgx()))
1801 +# define cpu_is_omap3515() (cpu_is_omap3430() && \
1802 + (!omap3_has_iva()) && \
1803 + (omap3_has_sgx()))
1804 +# define cpu_is_omap3525() (cpu_is_omap3430() && \
1805 + (!omap3_has_sgx()) && \
1806 + (omap3_has_iva()))
1807 +# define cpu_is_omap3530() (cpu_is_omap3430())
1808 +# define cpu_is_omap3505() is_omap3505()
1809 +# define cpu_is_omap3517() is_omap3517()
1810 +# undef cpu_is_omap3630
1811 +# define cpu_is_omap3630() is_omap363x()
1812 +#endif
1813 +
1814 +# if defined(CONFIG_ARCH_OMAP4)
1815 +# undef cpu_is_omap44xx
1816 +# undef cpu_is_omap443x
1817 +# define cpu_is_omap44xx() is_omap44xx()
1818 +# define cpu_is_omap443x() is_omap443x()
1819 +# endif
1820 +
1821 +/* Macros to detect if we have OMAP1 or OMAP2 */
1822 +#define cpu_class_is_omap1() (cpu_is_omap7xx() || cpu_is_omap15xx() || \
1823 + cpu_is_omap16xx())
1824 +#define cpu_class_is_omap2() (cpu_is_omap24xx() || cpu_is_omap34xx() || \
1825 + cpu_is_omap44xx())
1826 +
1827 +/* Various silicon revisions for omap2 */
1828 +#define OMAP242X_CLASS 0x24200024
1829 +#define OMAP2420_REV_ES1_0 0x24200024
1830 +#define OMAP2420_REV_ES2_0 0x24201024
1831 +
1832 +#define OMAP243X_CLASS 0x24300024
1833 +#define OMAP2430_REV_ES1_0 0x24300024
1834 +
1835 +#define OMAP343X_CLASS 0x34300034
1836 +#define OMAP3430_REV_ES1_0 0x34300034
1837 +#define OMAP3430_REV_ES2_0 0x34301034
1838 +#define OMAP3430_REV_ES2_1 0x34302034
1839 +#define OMAP3430_REV_ES3_0 0x34303034
1840 +#define OMAP3430_REV_ES3_1 0x34304034
1841 +
1842 +#define OMAP3630_REV_ES1_0 0x36300034
1843 +
1844 +#define OMAP35XX_CLASS 0x35000034
1845 +#define OMAP3503_REV(v) (OMAP35XX_CLASS | (0x3503 << 16) | (v << 8))
1846 +#define OMAP3515_REV(v) (OMAP35XX_CLASS | (0x3515 << 16) | (v << 8))
1847 +#define OMAP3525_REV(v) (OMAP35XX_CLASS | (0x3525 << 16) | (v << 8))
1848 +#define OMAP3530_REV(v) (OMAP35XX_CLASS | (0x3530 << 16) | (v << 8))
1849 +#define OMAP3505_REV(v) (OMAP35XX_CLASS | (0x3505 << 16) | (v << 8))
1850 +#define OMAP3517_REV(v) (OMAP35XX_CLASS | (0x3517 << 16) | (v << 8))
1851 +
1852 +#define OMAP443X_CLASS 0x44300044
1853 +#define OMAP4430_REV_ES1_0 0x44300044
1854 +
1855 +/*
1856 + * omap_chip bits
1857 + *
1858 + * CHIP_IS_OMAP{2420,2430,3430} indicate that a particular structure is
1859 + * valid on all chips of that type. CHIP_IS_OMAP3430ES{1,2} indicates
1860 + * something that is only valid on that particular ES revision.
1861 + *
1862 + * These bits may be ORed together to indicate structures that are
1863 + * available on multiple chip types.
1864 + *
1865 + * To test whether a particular structure matches the current OMAP chip type,
1866 + * use omap_chip_is().
1867 + *
1868 + */
1869 +#define CHIP_IS_OMAP2420 (1 << 0)
1870 +#define CHIP_IS_OMAP2430 (1 << 1)
1871 +#define CHIP_IS_OMAP3430 (1 << 2)
1872 +#define CHIP_IS_OMAP3430ES1 (1 << 3)
1873 +#define CHIP_IS_OMAP3430ES2 (1 << 4)
1874 +#define CHIP_IS_OMAP3430ES3_0 (1 << 5)
1875 +#define CHIP_IS_OMAP3430ES3_1 (1 << 6)
1876 +#define CHIP_IS_OMAP3630ES1 (1 << 7)
1877 +
1878 +#define CHIP_IS_OMAP24XX (CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430)
1879 +
1880 +/*
1881 + * "GE" here represents "greater than or equal to" in terms of ES
1882 + * levels. So CHIP_GE_OMAP3430ES2 is intended to match all OMAP3430
1883 + * chips at ES2 and beyond, but not, for example, any OMAP lines after
1884 + * OMAP3.
1885 + */
1886 +#define CHIP_GE_OMAP3430ES2 (CHIP_IS_OMAP3430ES2 | \
1887 + CHIP_IS_OMAP3430ES3_0 | \
1888 + CHIP_IS_OMAP3430ES3_1 | \
1889 + CHIP_IS_OMAP3630ES1)
1890 +#define CHIP_GE_OMAP3430ES3_1 (CHIP_IS_OMAP3430ES3_1 | \
1891 + CHIP_IS_OMAP3630ES1)
1892 +
1893 +
1894 +int omap_chip_is(struct omap_chip_id oci);
1895 +void omap2_check_revision(void);
1896 +
1897 +/*
1898 + * Runtime detection of OMAP3 features
1899 + */
1900 +extern u32 omap3_features;
1901 +
1902 +#define OMAP3_HAS_L2CACHE BIT(0)
1903 +#define OMAP3_HAS_IVA BIT(1)
1904 +#define OMAP3_HAS_SGX BIT(2)
1905 +#define OMAP3_HAS_NEON BIT(3)
1906 +#define OMAP3_HAS_ISP BIT(4)
1907 +
1908 +#define OMAP3_HAS_FEATURE(feat,flag) \
1909 +static inline unsigned int omap3_has_ ##feat(void) \
1910 +{ \
1911 + return (omap3_features & OMAP3_HAS_ ##flag); \
1912 +} \
1913 +
1914 +OMAP3_HAS_FEATURE(l2cache, L2CACHE)
1915 +OMAP3_HAS_FEATURE(sgx, SGX)
1916 +OMAP3_HAS_FEATURE(iva, IVA)
1917 +OMAP3_HAS_FEATURE(neon, NEON)
1918 +OMAP3_HAS_FEATURE(isp, ISP)
1919 +
1920 +#endif
1921 Index: linux-2.6.35/arch/arm/plat-omap/include/mach/display.h
1922 ===================================================================
1923 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
1924 +++ linux-2.6.35/arch/arm/plat-omap/include/mach/display.h 2010-08-08 12:56:45.000000000 +0200
1925 @@ -0,0 +1,575 @@
1926 +/*
1927 + * linux/include/asm-arm/arch-omap/display.h
1928 + *
1929 + * Copyright (C) 2008 Nokia Corporation
1930 + * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
1931 + *
1932 + * This program is free software; you can redistribute it and/or modify it
1933 + * under the terms of the GNU General Public License version 2 as published by
1934 + * the Free Software Foundation.
1935 + *
1936 + * This program is distributed in the hope that it will be useful, but WITHOUT
1937 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1938 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
1939 + * more details.
1940 + *
1941 + * You should have received a copy of the GNU General Public License along with
1942 + * this program. If not, see <http://www.gnu.org/licenses/>.
1943 + */
1944 +
1945 +#ifndef __ASM_ARCH_OMAP_DISPLAY_H
1946 +#define __ASM_ARCH_OMAP_DISPLAY_H
1947 +
1948 +#include <linux/list.h>
1949 +#include <linux/kobject.h>
1950 +#include <linux/device.h>
1951 +#include <asm/atomic.h>
1952 +
1953 +#define DISPC_IRQ_FRAMEDONE (1 << 0)
1954 +#define DISPC_IRQ_VSYNC (1 << 1)
1955 +#define DISPC_IRQ_EVSYNC_EVEN (1 << 2)
1956 +#define DISPC_IRQ_EVSYNC_ODD (1 << 3)
1957 +#define DISPC_IRQ_ACBIAS_COUNT_STAT (1 << 4)
1958 +#define DISPC_IRQ_PROG_LINE_NUM (1 << 5)
1959 +#define DISPC_IRQ_GFX_FIFO_UNDERFLOW (1 << 6)
1960 +#define DISPC_IRQ_GFX_END_WIN (1 << 7)
1961 +#define DISPC_IRQ_PAL_GAMMA_MASK (1 << 8)
1962 +#define DISPC_IRQ_OCP_ERR (1 << 9)
1963 +#define DISPC_IRQ_VID1_FIFO_UNDERFLOW (1 << 10)
1964 +#define DISPC_IRQ_VID1_END_WIN (1 << 11)
1965 +#define DISPC_IRQ_VID2_FIFO_UNDERFLOW (1 << 12)
1966 +#define DISPC_IRQ_VID2_END_WIN (1 << 13)
1967 +#define DISPC_IRQ_SYNC_LOST (1 << 14)
1968 +#define DISPC_IRQ_SYNC_LOST_DIGIT (1 << 15)
1969 +#define DISPC_IRQ_WAKEUP (1 << 16)
1970 +
1971 +struct omap_dss_device;
1972 +struct omap_overlay_manager;
1973 +
1974 +enum omap_display_type {
1975 + OMAP_DISPLAY_TYPE_NONE = 0,
1976 + OMAP_DISPLAY_TYPE_DPI = 1 << 0,
1977 + OMAP_DISPLAY_TYPE_DBI = 1 << 1,
1978 + OMAP_DISPLAY_TYPE_SDI = 1 << 2,
1979 + OMAP_DISPLAY_TYPE_DSI = 1 << 3,
1980 + OMAP_DISPLAY_TYPE_VENC = 1 << 4,
1981 +};
1982 +
1983 +enum omap_plane {
1984 + OMAP_DSS_GFX = 0,
1985 + OMAP_DSS_VIDEO1 = 1,
1986 + OMAP_DSS_VIDEO2 = 2
1987 +};
1988 +
1989 +enum omap_channel {
1990 + OMAP_DSS_CHANNEL_LCD = 0,
1991 + OMAP_DSS_CHANNEL_DIGIT = 1,
1992 +};
1993 +
1994 +enum omap_color_mode {
1995 + OMAP_DSS_COLOR_CLUT1 = 1 << 0, /* BITMAP 1 */
1996 + OMAP_DSS_COLOR_CLUT2 = 1 << 1, /* BITMAP 2 */
1997 + OMAP_DSS_COLOR_CLUT4 = 1 << 2, /* BITMAP 4 */
1998 + OMAP_DSS_COLOR_CLUT8 = 1 << 3, /* BITMAP 8 */
1999 + OMAP_DSS_COLOR_RGB12U = 1 << 4, /* RGB12, 16-bit container */
2000 + OMAP_DSS_COLOR_ARGB16 = 1 << 5, /* ARGB16 */
2001 + OMAP_DSS_COLOR_RGB16 = 1 << 6, /* RGB16 */
2002 + OMAP_DSS_COLOR_RGB24U = 1 << 7, /* RGB24, 32-bit container */
2003 + OMAP_DSS_COLOR_RGB24P = 1 << 8, /* RGB24, 24-bit container */
2004 + OMAP_DSS_COLOR_YUV2 = 1 << 9, /* YUV2 4:2:2 co-sited */
2005 + OMAP_DSS_COLOR_UYVY = 1 << 10, /* UYVY 4:2:2 co-sited */
2006 + OMAP_DSS_COLOR_ARGB32 = 1 << 11, /* ARGB32 */
2007 + OMAP_DSS_COLOR_RGBA32 = 1 << 12, /* RGBA32 */
2008 + OMAP_DSS_COLOR_RGBX32 = 1 << 13, /* RGBx32 */
2009 +
2010 + OMAP_DSS_COLOR_GFX_OMAP2 =
2011 + OMAP_DSS_COLOR_CLUT1 | OMAP_DSS_COLOR_CLUT2 |
2012 + OMAP_DSS_COLOR_CLUT4 | OMAP_DSS_COLOR_CLUT8 |
2013 + OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_RGB16 |
2014 + OMAP_DSS_COLOR_RGB24U | OMAP_DSS_COLOR_RGB24P,
2015 +
2016 + OMAP_DSS_COLOR_VID_OMAP2 =
2017 + OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
2018 + OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_YUV2 |
2019 + OMAP_DSS_COLOR_UYVY,
2020 +
2021 + OMAP_DSS_COLOR_GFX_OMAP3 =
2022 + OMAP_DSS_COLOR_CLUT1 | OMAP_DSS_COLOR_CLUT2 |
2023 + OMAP_DSS_COLOR_CLUT4 | OMAP_DSS_COLOR_CLUT8 |
2024 + OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_ARGB16 |
2025 + OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
2026 + OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_ARGB32 |
2027 + OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32,
2028 +
2029 + OMAP_DSS_COLOR_VID1_OMAP3 =
2030 + OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_RGB16 |
2031 + OMAP_DSS_COLOR_RGB24U | OMAP_DSS_COLOR_RGB24P |
2032 + OMAP_DSS_COLOR_YUV2 | OMAP_DSS_COLOR_UYVY,
2033 +
2034 + OMAP_DSS_COLOR_VID2_OMAP3 =
2035 + OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_ARGB16 |
2036 + OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
2037 + OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_YUV2 |
2038 + OMAP_DSS_COLOR_UYVY | OMAP_DSS_COLOR_ARGB32 |
2039 + OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32,
2040 +};
2041 +
2042 +enum omap_lcd_display_type {
2043 + OMAP_DSS_LCD_DISPLAY_STN,
2044 + OMAP_DSS_LCD_DISPLAY_TFT,
2045 +};
2046 +
2047 +enum omap_dss_load_mode {
2048 + OMAP_DSS_LOAD_CLUT_AND_FRAME = 0,
2049 + OMAP_DSS_LOAD_CLUT_ONLY = 1,
2050 + OMAP_DSS_LOAD_FRAME_ONLY = 2,
2051 + OMAP_DSS_LOAD_CLUT_ONCE_FRAME = 3,
2052 +};
2053 +
2054 +enum omap_dss_trans_key_type {
2055 + OMAP_DSS_COLOR_KEY_GFX_DST = 0,
2056 + OMAP_DSS_COLOR_KEY_VID_SRC = 1,
2057 +};
2058 +
2059 +enum omap_rfbi_te_mode {
2060 + OMAP_DSS_RFBI_TE_MODE_1 = 1,
2061 + OMAP_DSS_RFBI_TE_MODE_2 = 2,
2062 +};
2063 +
2064 +enum omap_panel_config {
2065 + OMAP_DSS_LCD_IVS = 1<<0,
2066 + OMAP_DSS_LCD_IHS = 1<<1,
2067 + OMAP_DSS_LCD_IPC = 1<<2,
2068 + OMAP_DSS_LCD_IEO = 1<<3,
2069 + OMAP_DSS_LCD_RF = 1<<4,
2070 + OMAP_DSS_LCD_ONOFF = 1<<5,
2071 +
2072 + OMAP_DSS_LCD_TFT = 1<<20,
2073 +};
2074 +
2075 +enum omap_dss_venc_type {
2076 + OMAP_DSS_VENC_TYPE_COMPOSITE,
2077 + OMAP_DSS_VENC_TYPE_SVIDEO,
2078 +};
2079 +
2080 +enum omap_display_caps {
2081 + OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE = 1 << 0,
2082 + OMAP_DSS_DISPLAY_CAP_TEAR_ELIM = 1 << 1,
2083 +};
2084 +
2085 +enum omap_dss_update_mode {
2086 + OMAP_DSS_UPDATE_DISABLED = 0,
2087 + OMAP_DSS_UPDATE_AUTO,
2088 + OMAP_DSS_UPDATE_MANUAL,
2089 +};
2090 +
2091 +enum omap_dss_display_state {
2092 + OMAP_DSS_DISPLAY_DISABLED = 0,
2093 + OMAP_DSS_DISPLAY_ACTIVE,
2094 + OMAP_DSS_DISPLAY_SUSPENDED,
2095 +};
2096 +
2097 +/* XXX perhaps this should be removed */
2098 +enum omap_dss_overlay_managers {
2099 + OMAP_DSS_OVL_MGR_LCD,
2100 + OMAP_DSS_OVL_MGR_TV,
2101 +};
2102 +
2103 +enum omap_dss_rotation_type {
2104 + OMAP_DSS_ROT_DMA = 0,
2105 + OMAP_DSS_ROT_VRFB = 1,
2106 +};
2107 +
2108 +/* clockwise rotation angle */
2109 +enum omap_dss_rotation_angle {
2110 + OMAP_DSS_ROT_0 = 0,
2111 + OMAP_DSS_ROT_90 = 1,
2112 + OMAP_DSS_ROT_180 = 2,
2113 + OMAP_DSS_ROT_270 = 3,
2114 +};
2115 +
2116 +enum omap_overlay_caps {
2117 + OMAP_DSS_OVL_CAP_SCALE = 1 << 0,
2118 + OMAP_DSS_OVL_CAP_DISPC = 1 << 1,
2119 +};
2120 +
2121 +enum omap_overlay_manager_caps {
2122 + OMAP_DSS_OVL_MGR_CAP_DISPC = 1 << 0,
2123 +};
2124 +
2125 +/* RFBI */
2126 +
2127 +struct rfbi_timings {
2128 + int cs_on_time;
2129 + int cs_off_time;
2130 + int we_on_time;
2131 + int we_off_time;
2132 + int re_on_time;
2133 + int re_off_time;
2134 + int we_cycle_time;
2135 + int re_cycle_time;
2136 + int cs_pulse_width;
2137 + int access_time;
2138 +
2139 + int clk_div;
2140 +
2141 + u32 tim[5]; /* set by rfbi_convert_timings() */
2142 +
2143 + int converted;
2144 +};
2145 +
2146 +void omap_rfbi_write_command(const void *buf, u32 len);
2147 +void omap_rfbi_read_data(void *buf, u32 len);
2148 +void omap_rfbi_write_data(const void *buf, u32 len);
2149 +void omap_rfbi_write_pixels(const void __iomem *buf, int scr_width,
2150 + u16 x, u16 y,
2151 + u16 w, u16 h);
2152 +int omap_rfbi_enable_te(bool enable, unsigned line);
2153 +int omap_rfbi_setup_te(enum omap_rfbi_te_mode mode,
2154 + unsigned hs_pulse_time, unsigned vs_pulse_time,
2155 + int hs_pol_inv, int vs_pol_inv, int extif_div);
2156 +
2157 +/* DSI */
2158 +void dsi_bus_lock(void);
2159 +void dsi_bus_unlock(void);
2160 +int dsi_vc_dcs_write(int channel, u8 *data, int len);
2161 +int dsi_vc_dcs_write_nosync(int channel, u8 *data, int len);
2162 +int dsi_vc_dcs_read(int channel, u8 dcs_cmd, u8 *buf, int buflen);
2163 +int dsi_vc_set_max_rx_packet_size(int channel, u16 len);
2164 +int dsi_vc_send_null(int channel);
2165 +int dsi_vc_send_bta_sync(int channel);
2166 +
2167 +/* Board specific data */
2168 +struct omap_dss_board_info {
2169 + int (*get_last_off_on_transaction_id)(struct device *dev);
2170 + int num_devices;
2171 + struct omap_dss_device **devices;
2172 + struct omap_dss_device *default_device;
2173 +};
2174 +
2175 +struct omap_video_timings {
2176 + /* Unit: pixels */
2177 + u16 x_res;
2178 + /* Unit: pixels */
2179 + u16 y_res;
2180 + /* Unit: KHz */
2181 + u32 pixel_clock;
2182 + /* Unit: pixel clocks */
2183 + u16 hsw; /* Horizontal synchronization pulse width */
2184 + /* Unit: pixel clocks */
2185 + u16 hfp; /* Horizontal front porch */
2186 + /* Unit: pixel clocks */
2187 + u16 hbp; /* Horizontal back porch */
2188 + /* Unit: line clocks */
2189 + u16 vsw; /* Vertical synchronization pulse width */
2190 + /* Unit: line clocks */
2191 + u16 vfp; /* Vertical front porch */
2192 + /* Unit: line clocks */
2193 + u16 vbp; /* Vertical back porch */
2194 +};
2195 +
2196 +#ifdef CONFIG_OMAP2_DSS_VENC
2197 +/* Hardcoded timings for tv modes. Venc only uses these to
2198 + * identify the mode, and does not actually use the configs
2199 + * itself. However, the configs should be something that
2200 + * a normal monitor can also show */
2201 +const extern struct omap_video_timings omap_dss_pal_timings;
2202 +const extern struct omap_video_timings omap_dss_ntsc_timings;
2203 +#endif
2204 +
2205 +struct omap_overlay_info {
2206 + bool enabled;
2207 +
2208 + u32 paddr;
2209 + void __iomem *vaddr;
2210 + u16 screen_width;
2211 + u16 width;
2212 + u16 height;
2213 + enum omap_color_mode color_mode;
2214 + u8 rotation;
2215 + enum omap_dss_rotation_type rotation_type;
2216 + bool mirror;
2217 +
2218 + u16 pos_x;
2219 + u16 pos_y;
2220 + u16 out_width; /* if 0, out_width == width */
2221 + u16 out_height; /* if 0, out_height == height */
2222 + u8 global_alpha;
2223 +};
2224 +
2225 +struct omap_overlay {
2226 + struct kobject kobj;
2227 + struct list_head list;
2228 +
2229 + /* static fields */
2230 + const char *name;
2231 + int id;
2232 + enum omap_color_mode supported_modes;
2233 + enum omap_overlay_caps caps;
2234 +
2235 + /* dynamic fields */
2236 + struct omap_overlay_manager *manager;
2237 + struct omap_overlay_info info;
2238 +
2239 + /* if true, info has been changed, but not applied() yet */
2240 + bool info_dirty;
2241 +
2242 + int (*set_manager)(struct omap_overlay *ovl,
2243 + struct omap_overlay_manager *mgr);
2244 + int (*unset_manager)(struct omap_overlay *ovl);
2245 +
2246 + int (*set_overlay_info)(struct omap_overlay *ovl,
2247 + struct omap_overlay_info *info);
2248 + void (*get_overlay_info)(struct omap_overlay *ovl,
2249 + struct omap_overlay_info *info);
2250 +
2251 + int (*wait_for_go)(struct omap_overlay *ovl);
2252 +};
2253 +
2254 +struct omap_overlay_manager_info {
2255 + u32 default_color;
2256 +
2257 + enum omap_dss_trans_key_type trans_key_type;
2258 + u32 trans_key;
2259 + bool trans_enabled;
2260 +
2261 + bool alpha_enabled;
2262 +};
2263 +
2264 +struct omap_overlay_manager {
2265 + struct kobject kobj;
2266 + struct list_head list;
2267 +
2268 + /* static fields */
2269 + const char *name;
2270 + int id;
2271 + enum omap_overlay_manager_caps caps;
2272 + int num_overlays;
2273 + struct omap_overlay **overlays;
2274 + enum omap_display_type supported_displays;
2275 +
2276 + /* dynamic fields */
2277 + struct omap_dss_device *device;
2278 + struct omap_overlay_manager_info info;
2279 +
2280 + bool device_changed;
2281 + /* if true, info has been changed but not applied() yet */
2282 + bool info_dirty;
2283 +
2284 + int (*set_device)(struct omap_overlay_manager *mgr,
2285 + struct omap_dss_device *dssdev);
2286 + int (*unset_device)(struct omap_overlay_manager *mgr);
2287 +
2288 + int (*set_manager_info)(struct omap_overlay_manager *mgr,
2289 + struct omap_overlay_manager_info *info);
2290 + void (*get_manager_info)(struct omap_overlay_manager *mgr,
2291 + struct omap_overlay_manager_info *info);
2292 +
2293 + int (*apply)(struct omap_overlay_manager *mgr);
2294 + int (*wait_for_go)(struct omap_overlay_manager *mgr);
2295 +};
2296 +
2297 +struct omap_dss_device {
2298 + struct device dev;
2299 +
2300 + enum omap_display_type type;
2301 +
2302 + union {
2303 + struct {
2304 + u8 data_lines;
2305 + } dpi;
2306 +
2307 + struct {
2308 + u8 channel;
2309 + u8 data_lines;
2310 + } rfbi;
2311 +
2312 + struct {
2313 + u8 datapairs;
2314 + } sdi;
2315 +
2316 + struct {
2317 + u8 clk_lane;
2318 + u8 clk_pol;
2319 + u8 data1_lane;
2320 + u8 data1_pol;
2321 + u8 data2_lane;
2322 + u8 data2_pol;
2323 +
2324 + struct {
2325 + u16 regn;
2326 + u16 regm;
2327 + u16 regm3;
2328 + u16 regm4;
2329 +
2330 + u16 lp_clk_div;
2331 +
2332 + u16 lck_div;
2333 + u16 pck_div;
2334 + } div;
2335 +
2336 + bool ext_te;
2337 + u8 ext_te_gpio;
2338 + } dsi;
2339 +
2340 + struct {
2341 + enum omap_dss_venc_type type;
2342 + bool invert_polarity;
2343 + } venc;
2344 + } phy;
2345 +
2346 + struct {
2347 + struct omap_video_timings timings;
2348 +
2349 + int acbi; /* ac-bias pin transitions per interrupt */
2350 + /* Unit: line clocks */
2351 + int acb; /* ac-bias pin frequency */
2352 +
2353 + enum omap_panel_config config;
2354 +
2355 + u8 recommended_bpp;
2356 +
2357 + struct omap_dss_device *ctrl;
2358 + } panel;
2359 +
2360 + struct {
2361 + u8 pixel_size;
2362 + struct rfbi_timings rfbi_timings;
2363 + struct omap_dss_device *panel;
2364 + } ctrl;
2365 +
2366 + int reset_gpio;
2367 +
2368 + int max_backlight_level;
2369 +
2370 + const char *name;
2371 +
2372 + /* used to match device to driver */
2373 + const char *driver_name;
2374 +
2375 + void *data;
2376 +
2377 + struct omap_dss_driver *driver;
2378 +
2379 + /* helper variable for driver suspend/resume */
2380 + bool activate_after_resume;
2381 +
2382 + enum omap_display_caps caps;
2383 +
2384 + struct omap_overlay_manager *manager;
2385 +
2386 + enum omap_dss_display_state state;
2387 +
2388 + int (*enable)(struct omap_dss_device *dssdev);
2389 + void (*disable)(struct omap_dss_device *dssdev);
2390 +
2391 + int (*suspend)(struct omap_dss_device *dssdev);
2392 + int (*resume)(struct omap_dss_device *dssdev);
2393 +
2394 + void (*get_resolution)(struct omap_dss_device *dssdev,
2395 + u16 *xres, u16 *yres);
2396 + int (*get_recommended_bpp)(struct omap_dss_device *dssdev);
2397 +
2398 + int (*check_timings)(struct omap_dss_device *dssdev,
2399 + struct omap_video_timings *timings);
2400 + void (*set_timings)(struct omap_dss_device *dssdev,
2401 + struct omap_video_timings *timings);
2402 + void (*get_timings)(struct omap_dss_device *dssdev,
2403 + struct omap_video_timings *timings);
2404 + int (*update)(struct omap_dss_device *dssdev,
2405 + u16 x, u16 y, u16 w, u16 h);
2406 + int (*sync)(struct omap_dss_device *dssdev);
2407 + int (*wait_vsync)(struct omap_dss_device *dssdev);
2408 +
2409 + int (*set_update_mode)(struct omap_dss_device *dssdev,
2410 + enum omap_dss_update_mode);
2411 + enum omap_dss_update_mode (*get_update_mode)
2412 + (struct omap_dss_device *dssdev);
2413 +
2414 + int (*enable_te)(struct omap_dss_device *dssdev, bool enable);
2415 + int (*get_te)(struct omap_dss_device *dssdev);
2416 +
2417 + u8 (*get_rotate)(struct omap_dss_device *dssdev);
2418 + int (*set_rotate)(struct omap_dss_device *dssdev, u8 rotate);
2419 +
2420 + bool (*get_mirror)(struct omap_dss_device *dssdev);
2421 + int (*set_mirror)(struct omap_dss_device *dssdev, bool enable);
2422 +
2423 + int (*run_test)(struct omap_dss_device *dssdev, int test);
2424 + int (*memory_read)(struct omap_dss_device *dssdev,
2425 + void *buf, size_t size,
2426 + u16 x, u16 y, u16 w, u16 h);
2427 +
2428 + int (*set_wss)(struct omap_dss_device *dssdev, u32 wss);
2429 + u32 (*get_wss)(struct omap_dss_device *dssdev);
2430 +
2431 + /* platform specific */
2432 + int (*platform_enable)(struct omap_dss_device *dssdev);
2433 + void (*platform_disable)(struct omap_dss_device *dssdev);
2434 + int (*set_backlight)(struct omap_dss_device *dssdev, int level);
2435 + int (*get_backlight)(struct omap_dss_device *dssdev);
2436 +};
2437 +
2438 +struct omap_dss_driver {
2439 + struct device_driver driver;
2440 +
2441 + int (*probe)(struct omap_dss_device *);
2442 + void (*remove)(struct omap_dss_device *);
2443 +
2444 + int (*enable)(struct omap_dss_device *display);
2445 + void (*disable)(struct omap_dss_device *display);
2446 + int (*suspend)(struct omap_dss_device *display);
2447 + int (*resume)(struct omap_dss_device *display);
2448 + int (*run_test)(struct omap_dss_device *display, int test);
2449 +
2450 + void (*setup_update)(struct omap_dss_device *dssdev,
2451 + u16 x, u16 y, u16 w, u16 h);
2452 +
2453 + int (*enable_te)(struct omap_dss_device *dssdev, bool enable);
2454 + int (*wait_for_te)(struct omap_dss_device *dssdev);
2455 +
2456 + u8 (*get_rotate)(struct omap_dss_device *dssdev);
2457 + int (*set_rotate)(struct omap_dss_device *dssdev, u8 rotate);
2458 +
2459 + bool (*get_mirror)(struct omap_dss_device *dssdev);
2460 + int (*set_mirror)(struct omap_dss_device *dssdev, bool enable);
2461 +
2462 + int (*memory_read)(struct omap_dss_device *dssdev,
2463 + void *buf, size_t size,
2464 + u16 x, u16 y, u16 w, u16 h);
2465 +};
2466 +
2467 +int omap_dss_register_driver(struct omap_dss_driver *);
2468 +void omap_dss_unregister_driver(struct omap_dss_driver *);
2469 +
2470 +int omap_dss_register_device(struct omap_dss_device *);
2471 +void omap_dss_unregister_device(struct omap_dss_device *);
2472 +
2473 +void omap_dss_get_device(struct omap_dss_device *dssdev);
2474 +void omap_dss_put_device(struct omap_dss_device *dssdev);
2475 +#define for_each_dss_dev(d) while ((d = omap_dss_get_next_device(d)) != NULL)
2476 +struct omap_dss_device *omap_dss_get_next_device(struct omap_dss_device *from);
2477 +struct omap_dss_device *omap_dss_find_device(void *data,
2478 + int (*match)(struct omap_dss_device *dssdev, void *data));
2479 +
2480 +int omap_dss_start_device(struct omap_dss_device *dssdev);
2481 +void omap_dss_stop_device(struct omap_dss_device *dssdev);
2482 +
2483 +int omap_dss_get_num_overlay_managers(void);
2484 +struct omap_overlay_manager *omap_dss_get_overlay_manager(int num);
2485 +
2486 +int omap_dss_get_num_overlays(void);
2487 +struct omap_overlay *omap_dss_get_overlay(int num);
2488 +
2489 +typedef void (*omap_dispc_isr_t) (void *arg, u32 mask);
2490 +int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
2491 +int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
2492 +
2493 +int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout);
2494 +int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
2495 + unsigned long timeout);
2496 +
2497 +#define to_dss_driver(x) container_of((x), struct omap_dss_driver, driver)
2498 +#define to_dss_device(x) container_of((x), struct omap_dss_device, dev)
2499 +
2500 +#endif
2501 Index: linux-2.6.35/arch/arm/plat-omap/include/mach/dma.h
2502 ===================================================================
2503 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
2504 +++ linux-2.6.35/arch/arm/plat-omap/include/mach/dma.h 2010-08-08 12:56:46.000000000 +0200
2505 @@ -0,0 +1,640 @@
2506 +/*
2507 + * arch/arm/plat-omap/include/mach/dma.h
2508 + *
2509 + * Copyright (C) 2003 Nokia Corporation
2510 + * Author: Juha Yrjölä <juha.yrjola@nokia.com>
2511 + *
2512 + * This program is free software; you can redistribute it and/or modify
2513 + * it under the terms of the GNU General Public License as published by
2514 + * the Free Software Foundation; either version 2 of the License, or
2515 + * (at your option) any later version.
2516 + *
2517 + * This program is distributed in the hope that it will be useful,
2518 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2519 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2520 + * GNU General Public License for more details.
2521 + *
2522 + * You should have received a copy of the GNU General Public License
2523 + * along with this program; if not, write to the Free Software
2524 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
2525 + */
2526 +#ifndef __ASM_ARCH_DMA_H
2527 +#define __ASM_ARCH_DMA_H
2528 +
2529 +/* Hardware registers for omap1 */
2530 +#define OMAP1_DMA_BASE (0xfffed800)
2531 +
2532 +#define OMAP1_DMA_GCR 0x400
2533 +#define OMAP1_DMA_GSCR 0x404
2534 +#define OMAP1_DMA_GRST 0x408
2535 +#define OMAP1_DMA_HW_ID 0x442
2536 +#define OMAP1_DMA_PCH2_ID 0x444
2537 +#define OMAP1_DMA_PCH0_ID 0x446
2538 +#define OMAP1_DMA_PCH1_ID 0x448
2539 +#define OMAP1_DMA_PCHG_ID 0x44a
2540 +#define OMAP1_DMA_PCHD_ID 0x44c
2541 +#define OMAP1_DMA_CAPS_0_U 0x44e
2542 +#define OMAP1_DMA_CAPS_0_L 0x450
2543 +#define OMAP1_DMA_CAPS_1_U 0x452
2544 +#define OMAP1_DMA_CAPS_1_L 0x454
2545 +#define OMAP1_DMA_CAPS_2 0x456
2546 +#define OMAP1_DMA_CAPS_3 0x458
2547 +#define OMAP1_DMA_CAPS_4 0x45a
2548 +#define OMAP1_DMA_PCH2_SR 0x460
2549 +#define OMAP1_DMA_PCH0_SR 0x480
2550 +#define OMAP1_DMA_PCH1_SR 0x482
2551 +#define OMAP1_DMA_PCHD_SR 0x4c0
2552 +
2553 +/* Hardware registers for omap2 and omap3 */
2554 +#define OMAP24XX_DMA4_BASE (L4_24XX_BASE + 0x56000)
2555 +#define OMAP34XX_DMA4_BASE (L4_34XX_BASE + 0x56000)
2556 +#define OMAP44XX_DMA4_BASE (L4_44XX_BASE + 0x56000)
2557 +
2558 +#define OMAP_DMA4_REVISION 0x00
2559 +#define OMAP_DMA4_GCR 0x78
2560 +#define OMAP_DMA4_IRQSTATUS_L0 0x08
2561 +#define OMAP_DMA4_IRQSTATUS_L1 0x0c
2562 +#define OMAP_DMA4_IRQSTATUS_L2 0x10
2563 +#define OMAP_DMA4_IRQSTATUS_L3 0x14
2564 +#define OMAP_DMA4_IRQENABLE_L0 0x18
2565 +#define OMAP_DMA4_IRQENABLE_L1 0x1c
2566 +#define OMAP_DMA4_IRQENABLE_L2 0x20
2567 +#define OMAP_DMA4_IRQENABLE_L3 0x24
2568 +#define OMAP_DMA4_SYSSTATUS 0x28
2569 +#define OMAP_DMA4_OCP_SYSCONFIG 0x2c
2570 +#define OMAP_DMA4_CAPS_0 0x64
2571 +#define OMAP_DMA4_CAPS_2 0x6c
2572 +#define OMAP_DMA4_CAPS_3 0x70
2573 +#define OMAP_DMA4_CAPS_4 0x74
2574 +
2575 +#define OMAP1_LOGICAL_DMA_CH_COUNT 17
2576 +#define OMAP_DMA4_LOGICAL_DMA_CH_COUNT 32 /* REVISIT: Is this 32 + 2? */
2577 +
2578 +/* Common channel specific registers for omap1 */
2579 +#define OMAP1_DMA_CH_BASE(n) (0x40 * (n) + 0x00)
2580 +#define OMAP1_DMA_CSDP(n) (0x40 * (n) + 0x00)
2581 +#define OMAP1_DMA_CCR(n) (0x40 * (n) + 0x02)
2582 +#define OMAP1_DMA_CICR(n) (0x40 * (n) + 0x04)
2583 +#define OMAP1_DMA_CSR(n) (0x40 * (n) + 0x06)
2584 +#define OMAP1_DMA_CEN(n) (0x40 * (n) + 0x10)
2585 +#define OMAP1_DMA_CFN(n) (0x40 * (n) + 0x12)
2586 +#define OMAP1_DMA_CSFI(n) (0x40 * (n) + 0x14)
2587 +#define OMAP1_DMA_CSEI(n) (0x40 * (n) + 0x16)
2588 +#define OMAP1_DMA_CPC(n) (0x40 * (n) + 0x18) /* 15xx only */
2589 +#define OMAP1_DMA_CSAC(n) (0x40 * (n) + 0x18)
2590 +#define OMAP1_DMA_CDAC(n) (0x40 * (n) + 0x1a)
2591 +#define OMAP1_DMA_CDEI(n) (0x40 * (n) + 0x1c)
2592 +#define OMAP1_DMA_CDFI(n) (0x40 * (n) + 0x1e)
2593 +#define OMAP1_DMA_CLNK_CTRL(n) (0x40 * (n) + 0x28)
2594 +
2595 +/* Common channel specific registers for omap2 */
2596 +#define OMAP_DMA4_CH_BASE(n) (0x60 * (n) + 0x80)
2597 +#define OMAP_DMA4_CCR(n) (0x60 * (n) + 0x80)
2598 +#define OMAP_DMA4_CLNK_CTRL(n) (0x60 * (n) + 0x84)
2599 +#define OMAP_DMA4_CICR(n) (0x60 * (n) + 0x88)
2600 +#define OMAP_DMA4_CSR(n) (0x60 * (n) + 0x8c)
2601 +#define OMAP_DMA4_CSDP(n) (0x60 * (n) + 0x90)
2602 +#define OMAP_DMA4_CEN(n) (0x60 * (n) + 0x94)
2603 +#define OMAP_DMA4_CFN(n) (0x60 * (n) + 0x98)
2604 +#define OMAP_DMA4_CSEI(n) (0x60 * (n) + 0xa4)
2605 +#define OMAP_DMA4_CSFI(n) (0x60 * (n) + 0xa8)
2606 +#define OMAP_DMA4_CDEI(n) (0x60 * (n) + 0xac)
2607 +#define OMAP_DMA4_CDFI(n) (0x60 * (n) + 0xb0)
2608 +#define OMAP_DMA4_CSAC(n) (0x60 * (n) + 0xb4)
2609 +#define OMAP_DMA4_CDAC(n) (0x60 * (n) + 0xb8)
2610 +
2611 +/* Channel specific registers only on omap1 */
2612 +#define OMAP1_DMA_CSSA_L(n) (0x40 * (n) + 0x08)
2613 +#define OMAP1_DMA_CSSA_U(n) (0x40 * (n) + 0x0a)
2614 +#define OMAP1_DMA_CDSA_L(n) (0x40 * (n) + 0x0c)
2615 +#define OMAP1_DMA_CDSA_U(n) (0x40 * (n) + 0x0e)
2616 +#define OMAP1_DMA_COLOR_L(n) (0x40 * (n) + 0x20)
2617 +#define OMAP1_DMA_COLOR_U(n) (0x40 * (n) + 0x22)
2618 +#define OMAP1_DMA_CCR2(n) (0x40 * (n) + 0x24)
2619 +#define OMAP1_DMA_LCH_CTRL(n) (0x40 * (n) + 0x2a) /* not on 15xx */
2620 +#define OMAP1_DMA_CCEN(n) 0
2621 +#define OMAP1_DMA_CCFN(n) 0
2622 +
2623 +/* Channel specific registers only on omap2 */
2624 +#define OMAP_DMA4_CSSA(n) (0x60 * (n) + 0x9c)
2625 +#define OMAP_DMA4_CDSA(n) (0x60 * (n) + 0xa0)
2626 +#define OMAP_DMA4_CCEN(n) (0x60 * (n) + 0xbc)
2627 +#define OMAP_DMA4_CCFN(n) (0x60 * (n) + 0xc0)
2628 +#define OMAP_DMA4_COLOR(n) (0x60 * (n) + 0xc4)
2629 +
2630 +/* Additional registers available on OMAP4 */
2631 +#define OMAP_DMA4_CDP(n) (0x60 * (n) + 0xd0)
2632 +#define OMAP_DMA4_CNDP(n) (0x60 * (n) + 0xd4)
2633 +#define OMAP_DMA4_CCDN(n) (0x60 * (n) + 0xd8)
2634 +
2635 +/* Dummy defines to keep multi-omap compiles happy */
2636 +#define OMAP1_DMA_REVISION 0
2637 +#define OMAP1_DMA_IRQSTATUS_L0 0
2638 +#define OMAP1_DMA_IRQENABLE_L0 0
2639 +#define OMAP1_DMA_OCP_SYSCONFIG 0
2640 +#define OMAP_DMA4_HW_ID 0
2641 +#define OMAP_DMA4_CAPS_0_L 0
2642 +#define OMAP_DMA4_CAPS_0_U 0
2643 +#define OMAP_DMA4_CAPS_1_L 0
2644 +#define OMAP_DMA4_CAPS_1_U 0
2645 +#define OMAP_DMA4_GSCR 0
2646 +#define OMAP_DMA4_CPC(n) 0
2647 +
2648 +#define OMAP_DMA4_LCH_CTRL(n) 0
2649 +#define OMAP_DMA4_COLOR_L(n) 0
2650 +#define OMAP_DMA4_COLOR_U(n) 0
2651 +#define OMAP_DMA4_CCR2(n) 0
2652 +#define OMAP1_DMA_CSSA(n) 0
2653 +#define OMAP1_DMA_CDSA(n) 0
2654 +#define OMAP_DMA4_CSSA_L(n) 0
2655 +#define OMAP_DMA4_CSSA_U(n) 0
2656 +#define OMAP_DMA4_CDSA_L(n) 0
2657 +#define OMAP_DMA4_CDSA_U(n) 0
2658 +#define OMAP1_DMA_COLOR(n) 0
2659 +
2660 +/*----------------------------------------------------------------------------*/
2661 +
2662 +/* DMA channels for omap1 */
2663 +#define OMAP_DMA_NO_DEVICE 0
2664 +#define OMAP_DMA_MCSI1_TX 1
2665 +#define OMAP_DMA_MCSI1_RX 2
2666 +#define OMAP_DMA_I2C_RX 3
2667 +#define OMAP_DMA_I2C_TX 4
2668 +#define OMAP_DMA_EXT_NDMA_REQ 5
2669 +#define OMAP_DMA_EXT_NDMA_REQ2 6
2670 +#define OMAP_DMA_UWIRE_TX 7
2671 +#define OMAP_DMA_MCBSP1_TX 8
2672 +#define OMAP_DMA_MCBSP1_RX 9
2673 +#define OMAP_DMA_MCBSP3_TX 10
2674 +#define OMAP_DMA_MCBSP3_RX 11
2675 +#define OMAP_DMA_UART1_TX 12
2676 +#define OMAP_DMA_UART1_RX 13
2677 +#define OMAP_DMA_UART2_TX 14
2678 +#define OMAP_DMA_UART2_RX 15
2679 +#define OMAP_DMA_MCBSP2_TX 16
2680 +#define OMAP_DMA_MCBSP2_RX 17
2681 +#define OMAP_DMA_UART3_TX 18
2682 +#define OMAP_DMA_UART3_RX 19
2683 +#define OMAP_DMA_CAMERA_IF_RX 20
2684 +#define OMAP_DMA_MMC_TX 21
2685 +#define OMAP_DMA_MMC_RX 22
2686 +#define OMAP_DMA_NAND 23
2687 +#define OMAP_DMA_IRQ_LCD_LINE 24
2688 +#define OMAP_DMA_MEMORY_STICK 25
2689 +#define OMAP_DMA_USB_W2FC_RX0 26
2690 +#define OMAP_DMA_USB_W2FC_RX1 27
2691 +#define OMAP_DMA_USB_W2FC_RX2 28
2692 +#define OMAP_DMA_USB_W2FC_TX0 29
2693 +#define OMAP_DMA_USB_W2FC_TX1 30
2694 +#define OMAP_DMA_USB_W2FC_TX2 31
2695 +
2696 +/* These are only for 1610 */
2697 +#define OMAP_DMA_CRYPTO_DES_IN 32
2698 +#define OMAP_DMA_SPI_TX 33
2699 +#define OMAP_DMA_SPI_RX 34
2700 +#define OMAP_DMA_CRYPTO_HASH 35
2701 +#define OMAP_DMA_CCP_ATTN 36
2702 +#define OMAP_DMA_CCP_FIFO_NOT_EMPTY 37
2703 +#define OMAP_DMA_CMT_APE_TX_CHAN_0 38
2704 +#define OMAP_DMA_CMT_APE_RV_CHAN_0 39
2705 +#define OMAP_DMA_CMT_APE_TX_CHAN_1 40
2706 +#define OMAP_DMA_CMT_APE_RV_CHAN_1 41
2707 +#define OMAP_DMA_CMT_APE_TX_CHAN_2 42
2708 +#define OMAP_DMA_CMT_APE_RV_CHAN_2 43
2709 +#define OMAP_DMA_CMT_APE_TX_CHAN_3 44
2710 +#define OMAP_DMA_CMT_APE_RV_CHAN_3 45
2711 +#define OMAP_DMA_CMT_APE_TX_CHAN_4 46
2712 +#define OMAP_DMA_CMT_APE_RV_CHAN_4 47
2713 +#define OMAP_DMA_CMT_APE_TX_CHAN_5 48
2714 +#define OMAP_DMA_CMT_APE_RV_CHAN_5 49
2715 +#define OMAP_DMA_CMT_APE_TX_CHAN_6 50
2716 +#define OMAP_DMA_CMT_APE_RV_CHAN_6 51
2717 +#define OMAP_DMA_CMT_APE_TX_CHAN_7 52
2718 +#define OMAP_DMA_CMT_APE_RV_CHAN_7 53
2719 +#define OMAP_DMA_MMC2_TX 54
2720 +#define OMAP_DMA_MMC2_RX 55
2721 +#define OMAP_DMA_CRYPTO_DES_OUT 56
2722 +
2723 +/* DMA channels for 24xx */
2724 +#define OMAP24XX_DMA_NO_DEVICE 0
2725 +#define OMAP24XX_DMA_XTI_DMA 1 /* S_DMA_0 */
2726 +#define OMAP24XX_DMA_EXT_DMAREQ0 2 /* S_DMA_1 */
2727 +#define OMAP24XX_DMA_EXT_DMAREQ1 3 /* S_DMA_2 */
2728 +#define OMAP24XX_DMA_GPMC 4 /* S_DMA_3 */
2729 +#define OMAP24XX_DMA_GFX 5 /* S_DMA_4 */
2730 +#define OMAP24XX_DMA_DSS 6 /* S_DMA_5 */
2731 +#define OMAP242X_DMA_VLYNQ_TX 7 /* S_DMA_6 */
2732 +#define OMAP24XX_DMA_EXT_DMAREQ2 7 /* S_DMA_6 */
2733 +#define OMAP24XX_DMA_CWT 8 /* S_DMA_7 */
2734 +#define OMAP24XX_DMA_AES_TX 9 /* S_DMA_8 */
2735 +#define OMAP24XX_DMA_AES_RX 10 /* S_DMA_9 */
2736 +#define OMAP24XX_DMA_DES_TX 11 /* S_DMA_10 */
2737 +#define OMAP24XX_DMA_DES_RX 12 /* S_DMA_11 */
2738 +#define OMAP24XX_DMA_SHA1MD5_RX 13 /* S_DMA_12 */
2739 +#define OMAP34XX_DMA_SHA2MD5_RX 13 /* S_DMA_12 */
2740 +#define OMAP242X_DMA_EXT_DMAREQ2 14 /* S_DMA_13 */
2741 +#define OMAP242X_DMA_EXT_DMAREQ3 15 /* S_DMA_14 */
2742 +#define OMAP242X_DMA_EXT_DMAREQ4 16 /* S_DMA_15 */
2743 +#define OMAP242X_DMA_EAC_AC_RD 17 /* S_DMA_16 */
2744 +#define OMAP242X_DMA_EAC_AC_WR 18 /* S_DMA_17 */
2745 +#define OMAP242X_DMA_EAC_MD_UL_RD 19 /* S_DMA_18 */
2746 +#define OMAP242X_DMA_EAC_MD_UL_WR 20 /* S_DMA_19 */
2747 +#define OMAP242X_DMA_EAC_MD_DL_RD 21 /* S_DMA_20 */
2748 +#define OMAP242X_DMA_EAC_MD_DL_WR 22 /* S_DMA_21 */
2749 +#define OMAP242X_DMA_EAC_BT_UL_RD 23 /* S_DMA_22 */
2750 +#define OMAP242X_DMA_EAC_BT_UL_WR 24 /* S_DMA_23 */
2751 +#define OMAP242X_DMA_EAC_BT_DL_RD 25 /* S_DMA_24 */
2752 +#define OMAP242X_DMA_EAC_BT_DL_WR 26 /* S_DMA_25 */
2753 +#define OMAP243X_DMA_EXT_DMAREQ3 14 /* S_DMA_13 */
2754 +#define OMAP24XX_DMA_SPI3_TX0 15 /* S_DMA_14 */
2755 +#define OMAP24XX_DMA_SPI3_RX0 16 /* S_DMA_15 */
2756 +#define OMAP24XX_DMA_MCBSP3_TX 17 /* S_DMA_16 */
2757 +#define OMAP24XX_DMA_MCBSP3_RX 18 /* S_DMA_17 */
2758 +#define OMAP24XX_DMA_MCBSP4_TX 19 /* S_DMA_18 */
2759 +#define OMAP24XX_DMA_MCBSP4_RX 20 /* S_DMA_19 */
2760 +#define OMAP24XX_DMA_MCBSP5_TX 21 /* S_DMA_20 */
2761 +#define OMAP24XX_DMA_MCBSP5_RX 22 /* S_DMA_21 */
2762 +#define OMAP24XX_DMA_SPI3_TX1 23 /* S_DMA_22 */
2763 +#define OMAP24XX_DMA_SPI3_RX1 24 /* S_DMA_23 */
2764 +#define OMAP243X_DMA_EXT_DMAREQ4 25 /* S_DMA_24 */
2765 +#define OMAP243X_DMA_EXT_DMAREQ5 26 /* S_DMA_25 */
2766 +#define OMAP34XX_DMA_I2C3_TX 25 /* S_DMA_24 */
2767 +#define OMAP34XX_DMA_I2C3_RX 26 /* S_DMA_25 */
2768 +#define OMAP24XX_DMA_I2C1_TX 27 /* S_DMA_26 */
2769 +#define OMAP24XX_DMA_I2C1_RX 28 /* S_DMA_27 */
2770 +#define OMAP24XX_DMA_I2C2_TX 29 /* S_DMA_28 */
2771 +#define OMAP24XX_DMA_I2C2_RX 30 /* S_DMA_29 */
2772 +#define OMAP24XX_DMA_MCBSP1_TX 31 /* S_DMA_30 */
2773 +#define OMAP24XX_DMA_MCBSP1_RX 32 /* S_DMA_31 */
2774 +#define OMAP24XX_DMA_MCBSP2_TX 33 /* S_DMA_32 */
2775 +#define OMAP24XX_DMA_MCBSP2_RX 34 /* S_DMA_33 */
2776 +#define OMAP24XX_DMA_SPI1_TX0 35 /* S_DMA_34 */
2777 +#define OMAP24XX_DMA_SPI1_RX0 36 /* S_DMA_35 */
2778 +#define OMAP24XX_DMA_SPI1_TX1 37 /* S_DMA_36 */
2779 +#define OMAP24XX_DMA_SPI1_RX1 38 /* S_DMA_37 */
2780 +#define OMAP24XX_DMA_SPI1_TX2 39 /* S_DMA_38 */
2781 +#define OMAP24XX_DMA_SPI1_RX2 40 /* S_DMA_39 */
2782 +#define OMAP24XX_DMA_SPI1_TX3 41 /* S_DMA_40 */
2783 +#define OMAP24XX_DMA_SPI1_RX3 42 /* S_DMA_41 */
2784 +#define OMAP24XX_DMA_SPI2_TX0 43 /* S_DMA_42 */
2785 +#define OMAP24XX_DMA_SPI2_RX0 44 /* S_DMA_43 */
2786 +#define OMAP24XX_DMA_SPI2_TX1 45 /* S_DMA_44 */
2787 +#define OMAP24XX_DMA_SPI2_RX1 46 /* S_DMA_45 */
2788 +#define OMAP24XX_DMA_MMC2_TX 47 /* S_DMA_46 */
2789 +#define OMAP24XX_DMA_MMC2_RX 48 /* S_DMA_47 */
2790 +#define OMAP24XX_DMA_UART1_TX 49 /* S_DMA_48 */
2791 +#define OMAP24XX_DMA_UART1_RX 50 /* S_DMA_49 */
2792 +#define OMAP24XX_DMA_UART2_TX 51 /* S_DMA_50 */
2793 +#define OMAP24XX_DMA_UART2_RX 52 /* S_DMA_51 */
2794 +#define OMAP24XX_DMA_UART3_TX 53 /* S_DMA_52 */
2795 +#define OMAP24XX_DMA_UART3_RX 54 /* S_DMA_53 */
2796 +#define OMAP24XX_DMA_USB_W2FC_TX0 55 /* S_DMA_54 */
2797 +#define OMAP24XX_DMA_USB_W2FC_RX0 56 /* S_DMA_55 */
2798 +#define OMAP24XX_DMA_USB_W2FC_TX1 57 /* S_DMA_56 */
2799 +#define OMAP24XX_DMA_USB_W2FC_RX1 58 /* S_DMA_57 */
2800 +#define OMAP24XX_DMA_USB_W2FC_TX2 59 /* S_DMA_58 */
2801 +#define OMAP24XX_DMA_USB_W2FC_RX2 60 /* S_DMA_59 */
2802 +#define OMAP24XX_DMA_MMC1_TX 61 /* S_DMA_60 */
2803 +#define OMAP24XX_DMA_MMC1_RX 62 /* S_DMA_61 */
2804 +#define OMAP24XX_DMA_MS 63 /* S_DMA_62 */
2805 +#define OMAP242X_DMA_EXT_DMAREQ5 64 /* S_DMA_63 */
2806 +#define OMAP243X_DMA_EXT_DMAREQ6 64 /* S_DMA_63 */
2807 +#define OMAP34XX_DMA_EXT_DMAREQ3 64 /* S_DMA_63 */
2808 +#define OMAP34XX_DMA_AES2_TX 65 /* S_DMA_64 */
2809 +#define OMAP34XX_DMA_AES2_RX 66 /* S_DMA_65 */
2810 +#define OMAP34XX_DMA_DES2_TX 67 /* S_DMA_66 */
2811 +#define OMAP34XX_DMA_DES2_RX 68 /* S_DMA_67 */
2812 +#define OMAP34XX_DMA_SHA1MD5_RX 69 /* S_DMA_68 */
2813 +#define OMAP34XX_DMA_SPI4_TX0 70 /* S_DMA_69 */
2814 +#define OMAP34XX_DMA_SPI4_RX0 71 /* S_DMA_70 */
2815 +#define OMAP34XX_DSS_DMA0 72 /* S_DMA_71 */
2816 +#define OMAP34XX_DSS_DMA1 73 /* S_DMA_72 */
2817 +#define OMAP34XX_DSS_DMA2 74 /* S_DMA_73 */
2818 +#define OMAP34XX_DSS_DMA3 75 /* S_DMA_74 */
2819 +#define OMAP34XX_DMA_MMC3_TX 77 /* S_DMA_76 */
2820 +#define OMAP34XX_DMA_MMC3_RX 78 /* S_DMA_77 */
2821 +#define OMAP34XX_DMA_USIM_TX 79 /* S_DMA_78 */
2822 +#define OMAP34XX_DMA_USIM_RX 80 /* S_DMA_79 */
2823 +
2824 +/* DMA request lines for 44xx */
2825 +#define OMAP44XX_DMA_DSS_DISPC_REQ 6 /* S_DMA_5 */
2826 +#define OMAP44XX_DMA_SYS_REQ2 7 /* S_DMA_6 */
2827 +#define OMAP44XX_DMA_ISS_REQ1 9 /* S_DMA_8 */
2828 +#define OMAP44XX_DMA_ISS_REQ2 10 /* S_DMA_9 */
2829 +#define OMAP44XX_DMA_ISS_REQ3 12 /* S_DMA_11 */
2830 +#define OMAP44XX_DMA_ISS_REQ4 13 /* S_DMA_12 */
2831 +#define OMAP44XX_DMA_DSS_RFBI_REQ 14 /* S_DMA_13 */
2832 +#define OMAP44XX_DMA_SPI3_TX0 15 /* S_DMA_14 */
2833 +#define OMAP44XX_DMA_SPI3_RX0 16 /* S_DMA_15 */
2834 +#define OMAP44XX_DMA_MCBSP2_TX 17 /* S_DMA_16 */
2835 +#define OMAP44XX_DMA_MCBSP2_RX 18 /* S_DMA_17 */
2836 +#define OMAP44XX_DMA_MCBSP3_TX 19 /* S_DMA_18 */
2837 +#define OMAP44XX_DMA_MCBSP3_RX 20 /* S_DMA_19 */
2838 +#define OMAP44XX_DMA_SPI3_TX1 23 /* S_DMA_22 */
2839 +#define OMAP44XX_DMA_SPI3_RX1 24 /* S_DMA_23 */
2840 +#define OMAP44XX_DMA_I2C3_TX 25 /* S_DMA_24 */
2841 +#define OMAP44XX_DMA_I2C3_RX 26 /* S_DMA_25 */
2842 +#define OMAP44XX_DMA_I2C1_TX 27 /* S_DMA_26 */
2843 +#define OMAP44XX_DMA_I2C1_RX 28 /* S_DMA_27 */
2844 +#define OMAP44XX_DMA_I2C2_TX 29 /* S_DMA_28 */
2845 +#define OMAP44XX_DMA_I2C2_RX 30 /* S_DMA_29 */
2846 +#define OMAP44XX_DMA_MCBSP4_TX 31 /* S_DMA_30 */
2847 +#define OMAP44XX_DMA_MCBSP4_RX 32 /* S_DMA_31 */
2848 +#define OMAP44XX_DMA_MCBSP1_TX 33 /* S_DMA_32 */
2849 +#define OMAP44XX_DMA_MCBSP1_RX 34 /* S_DMA_33 */
2850 +#define OMAP44XX_DMA_SPI1_TX0 35 /* S_DMA_34 */
2851 +#define OMAP44XX_DMA_SPI1_RX0 36 /* S_DMA_35 */
2852 +#define OMAP44XX_DMA_SPI1_TX1 37 /* S_DMA_36 */
2853 +#define OMAP44XX_DMA_SPI1_RX1 38 /* S_DMA_37 */
2854 +#define OMAP44XX_DMA_SPI1_TX2 39 /* S_DMA_38 */
2855 +#define OMAP44XX_DMA_SPI1_RX2 40 /* S_DMA_39 */
2856 +#define OMAP44XX_DMA_SPI1_TX3 41 /* S_DMA_40 */
2857 +#define OMAP44XX_DMA_SPI1_RX3 42 /* S_DMA_41 */
2858 +#define OMAP44XX_DMA_SPI2_TX0 43 /* S_DMA_42 */
2859 +#define OMAP44XX_DMA_SPI2_RX0 44 /* S_DMA_43 */
2860 +#define OMAP44XX_DMA_SPI2_TX1 45 /* S_DMA_44 */
2861 +#define OMAP44XX_DMA_SPI2_RX1 46 /* S_DMA_45 */
2862 +#define OMAP44XX_DMA_MMC2_TX 47 /* S_DMA_46 */
2863 +#define OMAP44XX_DMA_MMC2_RX 48 /* S_DMA_47 */
2864 +#define OMAP44XX_DMA_UART1_TX 49 /* S_DMA_48 */
2865 +#define OMAP44XX_DMA_UART1_RX 50 /* S_DMA_49 */
2866 +#define OMAP44XX_DMA_UART2_TX 51 /* S_DMA_50 */
2867 +#define OMAP44XX_DMA_UART2_RX 52 /* S_DMA_51 */
2868 +#define OMAP44XX_DMA_UART3_TX 53 /* S_DMA_52 */
2869 +#define OMAP44XX_DMA_UART3_RX 54 /* S_DMA_53 */
2870 +#define OMAP44XX_DMA_UART4_TX 55 /* S_DMA_54 */
2871 +#define OMAP44XX_DMA_UART4_RX 56 /* S_DMA_55 */
2872 +#define OMAP44XX_DMA_MMC4_TX 57 /* S_DMA_56 */
2873 +#define OMAP44XX_DMA_MMC4_RX 58 /* S_DMA_57 */
2874 +#define OMAP44XX_DMA_MMC5_TX 59 /* S_DMA_58 */
2875 +#define OMAP44XX_DMA_MMC5_RX 60 /* S_DMA_59 */
2876 +#define OMAP44XX_DMA_MMC1_TX 61 /* S_DMA_60 */
2877 +#define OMAP44XX_DMA_MMC1_RX 62 /* S_DMA_61 */
2878 +#define OMAP44XX_DMA_SYS_REQ3 64 /* S_DMA_63 */
2879 +#define OMAP44XX_DMA_MCPDM_UP 65 /* S_DMA_64 */
2880 +#define OMAP44XX_DMA_MCPDM_DL 66 /* S_DMA_65 */
2881 +#define OMAP44XX_DMA_SPI4_TX0 70 /* S_DMA_69 */
2882 +#define OMAP44XX_DMA_SPI4_RX0 71 /* S_DMA_70 */
2883 +#define OMAP44XX_DMA_DSS_DSI1_REQ0 72 /* S_DMA_71 */
2884 +#define OMAP44XX_DMA_DSS_DSI1_REQ1 73 /* S_DMA_72 */
2885 +#define OMAP44XX_DMA_DSS_DSI1_REQ2 74 /* S_DMA_73 */
2886 +#define OMAP44XX_DMA_DSS_DSI1_REQ3 75 /* S_DMA_74 */
2887 +#define OMAP44XX_DMA_DSS_HDMI_REQ 76 /* S_DMA_75 */
2888 +#define OMAP44XX_DMA_MMC3_TX 77 /* S_DMA_76 */
2889 +#define OMAP44XX_DMA_MMC3_RX 78 /* S_DMA_77 */
2890 +#define OMAP44XX_DMA_USIM_TX 79 /* S_DMA_78 */
2891 +#define OMAP44XX_DMA_USIM_RX 80 /* S_DMA_79 */
2892 +#define OMAP44XX_DMA_DSS_DSI2_REQ0 81 /* S_DMA_80 */
2893 +#define OMAP44XX_DMA_DSS_DSI2_REQ1 82 /* S_DMA_81 */
2894 +#define OMAP44XX_DMA_DSS_DSI2_REQ2 83 /* S_DMA_82 */
2895 +#define OMAP44XX_DMA_DSS_DSI2_REQ3 84 /* S_DMA_83 */
2896 +#define OMAP44XX_DMA_ABE_REQ0 101 /* S_DMA_100 */
2897 +#define OMAP44XX_DMA_ABE_REQ1 102 /* S_DMA_101 */
2898 +#define OMAP44XX_DMA_ABE_REQ2 103 /* S_DMA_102 */
2899 +#define OMAP44XX_DMA_ABE_REQ3 104 /* S_DMA_103 */
2900 +#define OMAP44XX_DMA_ABE_REQ4 105 /* S_DMA_104 */
2901 +#define OMAP44XX_DMA_ABE_REQ5 106 /* S_DMA_105 */
2902 +#define OMAP44XX_DMA_ABE_REQ6 107 /* S_DMA_106 */
2903 +#define OMAP44XX_DMA_ABE_REQ7 108 /* S_DMA_107 */
2904 +#define OMAP44XX_DMA_I2C4_TX 124 /* S_DMA_123 */
2905 +#define OMAP44XX_DMA_I2C4_RX 125 /* S_DMA_124 */
2906 +
2907 +/*----------------------------------------------------------------------------*/
2908 +
2909 +#define OMAP1_DMA_TOUT_IRQ (1 << 0)
2910 +#define OMAP_DMA_DROP_IRQ (1 << 1)
2911 +#define OMAP_DMA_HALF_IRQ (1 << 2)
2912 +#define OMAP_DMA_FRAME_IRQ (1 << 3)
2913 +#define OMAP_DMA_LAST_IRQ (1 << 4)
2914 +#define OMAP_DMA_BLOCK_IRQ (1 << 5)
2915 +#define OMAP1_DMA_SYNC_IRQ (1 << 6)
2916 +#define OMAP2_DMA_PKT_IRQ (1 << 7)
2917 +#define OMAP2_DMA_TRANS_ERR_IRQ (1 << 8)
2918 +#define OMAP2_DMA_SECURE_ERR_IRQ (1 << 9)
2919 +#define OMAP2_DMA_SUPERVISOR_ERR_IRQ (1 << 10)
2920 +#define OMAP2_DMA_MISALIGNED_ERR_IRQ (1 << 11)
2921 +
2922 +#define OMAP_DMA_CCR_EN (1 << 7)
2923 +
2924 +#define OMAP_DMA_DATA_TYPE_S8 0x00
2925 +#define OMAP_DMA_DATA_TYPE_S16 0x01
2926 +#define OMAP_DMA_DATA_TYPE_S32 0x02
2927 +
2928 +#define OMAP_DMA_SYNC_ELEMENT 0x00
2929 +#define OMAP_DMA_SYNC_FRAME 0x01
2930 +#define OMAP_DMA_SYNC_BLOCK 0x02
2931 +#define OMAP_DMA_SYNC_PACKET 0x03
2932 +
2933 +#define OMAP_DMA_SRC_SYNC 0x01
2934 +#define OMAP_DMA_DST_SYNC 0x00
2935 +
2936 +#define OMAP_DMA_PORT_EMIFF 0x00
2937 +#define OMAP_DMA_PORT_EMIFS 0x01
2938 +#define OMAP_DMA_PORT_OCP_T1 0x02
2939 +#define OMAP_DMA_PORT_TIPB 0x03
2940 +#define OMAP_DMA_PORT_OCP_T2 0x04
2941 +#define OMAP_DMA_PORT_MPUI 0x05
2942 +
2943 +#define OMAP_DMA_AMODE_CONSTANT 0x00
2944 +#define OMAP_DMA_AMODE_POST_INC 0x01
2945 +#define OMAP_DMA_AMODE_SINGLE_IDX 0x02
2946 +#define OMAP_DMA_AMODE_DOUBLE_IDX 0x03
2947 +
2948 +#define DMA_DEFAULT_FIFO_DEPTH 0x10
2949 +#define DMA_DEFAULT_ARB_RATE 0x01
2950 +/* Pass THREAD_RESERVE ORed with THREAD_FIFO for tparams */
2951 +#define DMA_THREAD_RESERVE_NORM (0x00 << 12) /* Def */
2952 +#define DMA_THREAD_RESERVE_ONET (0x01 << 12)
2953 +#define DMA_THREAD_RESERVE_TWOT (0x02 << 12)
2954 +#define DMA_THREAD_RESERVE_THREET (0x03 << 12)
2955 +#define DMA_THREAD_FIFO_NONE (0x00 << 14) /* Def */
2956 +#define DMA_THREAD_FIFO_75 (0x01 << 14)
2957 +#define DMA_THREAD_FIFO_25 (0x02 << 14)
2958 +#define DMA_THREAD_FIFO_50 (0x03 << 14)
2959 +
2960 +/* DMA4_OCP_SYSCONFIG bits */
2961 +#define DMA_SYSCONFIG_MIDLEMODE_MASK (3 << 12)
2962 +#define DMA_SYSCONFIG_CLOCKACTIVITY_MASK (3 << 8)
2963 +#define DMA_SYSCONFIG_EMUFREE (1 << 5)
2964 +#define DMA_SYSCONFIG_SIDLEMODE_MASK (3 << 3)
2965 +#define DMA_SYSCONFIG_SOFTRESET (1 << 2)
2966 +#define DMA_SYSCONFIG_AUTOIDLE (1 << 0)
2967 +
2968 +#define DMA_SYSCONFIG_MIDLEMODE(n) ((n) << 12)
2969 +#define DMA_SYSCONFIG_SIDLEMODE(n) ((n) << 3)
2970 +
2971 +#define DMA_IDLEMODE_SMARTIDLE 0x2
2972 +#define DMA_IDLEMODE_NO_IDLE 0x1
2973 +#define DMA_IDLEMODE_FORCE_IDLE 0x0
2974 +
2975 +/* Chaining modes*/
2976 +#ifndef CONFIG_ARCH_OMAP1
2977 +#define OMAP_DMA_STATIC_CHAIN 0x1
2978 +#define OMAP_DMA_DYNAMIC_CHAIN 0x2
2979 +#define OMAP_DMA_CHAIN_ACTIVE 0x1
2980 +#define OMAP_DMA_CHAIN_INACTIVE 0x0
2981 +#endif
2982 +
2983 +#define DMA_CH_PRIO_HIGH 0x1
2984 +#define DMA_CH_PRIO_LOW 0x0 /* Def */
2985 +
2986 +enum omap_dma_burst_mode {
2987 + OMAP_DMA_DATA_BURST_DIS = 0,
2988 + OMAP_DMA_DATA_BURST_4,
2989 + OMAP_DMA_DATA_BURST_8,
2990 + OMAP_DMA_DATA_BURST_16,
2991 +};
2992 +
2993 +enum end_type {
2994 + OMAP_DMA_LITTLE_ENDIAN = 0,
2995 + OMAP_DMA_BIG_ENDIAN
2996 +};
2997 +
2998 +enum omap_dma_color_mode {
2999 + OMAP_DMA_COLOR_DIS = 0,
3000 + OMAP_DMA_CONSTANT_FILL,
3001 + OMAP_DMA_TRANSPARENT_COPY
3002 +};
3003 +
3004 +enum omap_dma_write_mode {
3005 + OMAP_DMA_WRITE_NON_POSTED = 0,
3006 + OMAP_DMA_WRITE_POSTED,
3007 + OMAP_DMA_WRITE_LAST_NON_POSTED
3008 +};
3009 +
3010 +enum omap_dma_channel_mode {
3011 + OMAP_DMA_LCH_2D = 0,
3012 + OMAP_DMA_LCH_G,
3013 + OMAP_DMA_LCH_P,
3014 + OMAP_DMA_LCH_PD
3015 +};
3016 +
3017 +struct omap_dma_channel_params {
3018 + int data_type; /* data type 8,16,32 */
3019 + int elem_count; /* number of elements in a frame */
3020 + int frame_count; /* number of frames in a element */
3021 +
3022 + int src_port; /* Only on OMAP1 REVISIT: Is this needed? */
3023 + int src_amode; /* constant, post increment, indexed,
3024 + double indexed */
3025 + unsigned long src_start; /* source address : physical */
3026 + int src_ei; /* source element index */
3027 + int src_fi; /* source frame index */
3028 +
3029 + int dst_port; /* Only on OMAP1 REVISIT: Is this needed? */
3030 + int dst_amode; /* constant, post increment, indexed,
3031 + double indexed */
3032 + unsigned long dst_start; /* source address : physical */
3033 + int dst_ei; /* source element index */
3034 + int dst_fi; /* source frame index */
3035 +
3036 + int trigger; /* trigger attached if the channel is
3037 + synchronized */
3038 + int sync_mode; /* sycn on element, frame , block or packet */
3039 + int src_or_dst_synch; /* source synch(1) or destination synch(0) */
3040 +
3041 + int ie; /* interrupt enabled */
3042 +
3043 + unsigned char read_prio;/* read priority */
3044 + unsigned char write_prio;/* write priority */
3045 +
3046 +#ifndef CONFIG_ARCH_OMAP1
3047 + enum omap_dma_burst_mode burst_mode; /* Burst mode 4/8/16 words */
3048 +#endif
3049 +};
3050 +
3051 +
3052 +extern void omap_set_dma_priority(int lch, int dst_port, int priority);
3053 +extern int omap_request_dma(int dev_id, const char *dev_name,
3054 + void (*callback)(int lch, u16 ch_status, void *data),
3055 + void *data, int *dma_ch);
3056 +extern void omap_enable_dma_irq(int ch, u16 irq_bits);
3057 +extern void omap_disable_dma_irq(int ch, u16 irq_bits);
3058 +extern void omap_free_dma(int ch);
3059 +extern void omap_start_dma(int lch);
3060 +extern void omap_stop_dma(int lch);
3061 +extern void omap_set_dma_transfer_params(int lch, int data_type,
3062 + int elem_count, int frame_count,
3063 + int sync_mode,
3064 + int dma_trigger, int src_or_dst_synch);
3065 +extern void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode,
3066 + u32 color);
3067 +extern void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode);
3068 +extern void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode);
3069 +
3070 +extern void omap_set_dma_src_params(int lch, int src_port, int src_amode,
3071 + unsigned long src_start,
3072 + int src_ei, int src_fi);
3073 +extern void omap_set_dma_src_index(int lch, int eidx, int fidx);
3074 +extern void omap_set_dma_src_data_pack(int lch, int enable);
3075 +extern void omap_set_dma_src_burst_mode(int lch,
3076 + enum omap_dma_burst_mode burst_mode);
3077 +
3078 +extern void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
3079 + unsigned long dest_start,
3080 + int dst_ei, int dst_fi);
3081 +extern void omap_set_dma_dest_index(int lch, int eidx, int fidx);
3082 +extern void omap_set_dma_dest_data_pack(int lch, int enable);
3083 +extern void omap_set_dma_dest_burst_mode(int lch,
3084 + enum omap_dma_burst_mode burst_mode);
3085 +
3086 +extern void omap_set_dma_params(int lch,
3087 + struct omap_dma_channel_params *params);
3088 +
3089 +extern void omap_dma_link_lch(int lch_head, int lch_queue);
3090 +extern void omap_dma_unlink_lch(int lch_head, int lch_queue);
3091 +
3092 +extern int omap_set_dma_callback(int lch,
3093 + void (*callback)(int lch, u16 ch_status, void *data),
3094 + void *data);
3095 +extern dma_addr_t omap_get_dma_src_pos(int lch);
3096 +extern dma_addr_t omap_get_dma_dst_pos(int lch);
3097 +extern void omap_clear_dma(int lch);
3098 +extern int omap_get_dma_active_status(int lch);
3099 +extern int omap_dma_running(void);
3100 +extern void omap_dma_set_global_params(int arb_rate, int max_fifo_depth,
3101 + int tparams);
3102 +extern int omap_dma_set_prio_lch(int lch, unsigned char read_prio,
3103 + unsigned char write_prio);
3104 +extern void omap_set_dma_dst_endian_type(int lch, enum end_type etype);
3105 +extern void omap_set_dma_src_endian_type(int lch, enum end_type etype);
3106 +extern int omap_get_dma_index(int lch, int *ei, int *fi);
3107 +
3108 +void omap_dma_global_context_save(void);
3109 +void omap_dma_global_context_restore(void);
3110 +
3111 +extern void omap_dma_disable_irq(int lch);
3112 +
3113 +/* Chaining APIs */
3114 +#ifndef CONFIG_ARCH_OMAP1
3115 +extern int omap_request_dma_chain(int dev_id, const char *dev_name,
3116 + void (*callback) (int lch, u16 ch_status,
3117 + void *data),
3118 + int *chain_id, int no_of_chans,
3119 + int chain_mode,
3120 + struct omap_dma_channel_params params);
3121 +extern int omap_free_dma_chain(int chain_id);
3122 +extern int omap_dma_chain_a_transfer(int chain_id, int src_start,
3123 + int dest_start, int elem_count,
3124 + int frame_count, void *callbk_data);
3125 +extern int omap_start_dma_chain_transfers(int chain_id);
3126 +extern int omap_stop_dma_chain_transfers(int chain_id);
3127 +extern int omap_get_dma_chain_index(int chain_id, int *ei, int *fi);
3128 +extern int omap_get_dma_chain_dst_pos(int chain_id);
3129 +extern int omap_get_dma_chain_src_pos(int chain_id);
3130 +
3131 +extern int omap_modify_dma_chain_params(int chain_id,
3132 + struct omap_dma_channel_params params);
3133 +extern int omap_dma_chain_status(int chain_id);
3134 +#endif
3135 +
3136 +#if defined(CONFIG_ARCH_OMAP1) && defined(CONFIG_FB_OMAP)
3137 +#include <mach/lcd_dma.h>
3138 +#else
3139 +static inline int omap_lcd_dma_running(void)
3140 +{
3141 + return 0;
3142 +}
3143 +#endif
3144 +
3145 +#endif /* __ASM_ARCH_DMA_H */
3146 Index: linux-2.6.35/arch/arm/plat-omap/include/mach/dmtimer.h
3147 ===================================================================
3148 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
3149 +++ linux-2.6.35/arch/arm/plat-omap/include/mach/dmtimer.h 2010-08-08 12:56:47.000000000 +0200
3150 @@ -0,0 +1,84 @@
3151 +/*
3152 + * arch/arm/plat-omap/include/mach/dmtimer.h
3153 + *
3154 + * OMAP Dual-Mode Timers
3155 + *
3156 + * Copyright (C) 2005 Nokia Corporation
3157 + * Author: Lauri Leukkunen <lauri.leukkunen@nokia.com>
3158 + * PWM and clock framwork support by Timo Teras.
3159 + *
3160 + * This program is free software; you can redistribute it and/or modify it
3161 + * under the terms of the GNU General Public License as published by the
3162 + * Free Software Foundation; either version 2 of the License, or (at your
3163 + * option) any later version.
3164 + *
3165 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
3166 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
3167 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
3168 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
3169 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
3170 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
3171 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
3172 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3173 + *
3174 + * You should have received a copy of the GNU General Public License along
3175 + * with this program; if not, write to the Free Software Foundation, Inc.,
3176 + * 675 Mass Ave, Cambridge, MA 02139, USA.
3177 + */
3178 +
3179 +#ifndef __ASM_ARCH_DMTIMER_H
3180 +#define __ASM_ARCH_DMTIMER_H
3181 +
3182 +/* clock sources */
3183 +#define OMAP_TIMER_SRC_SYS_CLK 0x00
3184 +#define OMAP_TIMER_SRC_32_KHZ 0x01
3185 +#define OMAP_TIMER_SRC_EXT_CLK 0x02
3186 +
3187 +/* timer interrupt enable bits */
3188 +#define OMAP_TIMER_INT_CAPTURE (1 << 2)
3189 +#define OMAP_TIMER_INT_OVERFLOW (1 << 1)
3190 +#define OMAP_TIMER_INT_MATCH (1 << 0)
3191 +
3192 +/* trigger types */
3193 +#define OMAP_TIMER_TRIGGER_NONE 0x00
3194 +#define OMAP_TIMER_TRIGGER_OVERFLOW 0x01
3195 +#define OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE 0x02
3196 +
3197 +struct omap_dm_timer;
3198 +struct clk;
3199 +
3200 +int omap_dm_timer_init(void);
3201 +
3202 +struct omap_dm_timer *omap_dm_timer_request(void);
3203 +struct omap_dm_timer *omap_dm_timer_request_specific(int timer_id);
3204 +void omap_dm_timer_free(struct omap_dm_timer *timer);
3205 +void omap_dm_timer_enable(struct omap_dm_timer *timer);
3206 +void omap_dm_timer_disable(struct omap_dm_timer *timer);
3207 +
3208 +int omap_dm_timer_get_irq(struct omap_dm_timer *timer);
3209 +
3210 +u32 omap_dm_timer_modify_idlect_mask(u32 inputmask);
3211 +struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer);
3212 +
3213 +void omap_dm_timer_trigger(struct omap_dm_timer *timer);
3214 +void omap_dm_timer_start(struct omap_dm_timer *timer);
3215 +void omap_dm_timer_stop(struct omap_dm_timer *timer);
3216 +
3217 +int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source);
3218 +void omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload, unsigned int value);
3219 +void omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload, unsigned int value);
3220 +void omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable, unsigned int match);
3221 +void omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on, int toggle, int trigger);
3222 +void omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler);
3223 +
3224 +void omap_dm_timer_set_int_enable(struct omap_dm_timer *timer, unsigned int value);
3225 +
3226 +unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer);
3227 +void omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value);
3228 +unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer);
3229 +void omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value);
3230 +
3231 +int omap_dm_timers_active(void);
3232 +
3233 +
3234 +#endif /* __ASM_ARCH_DMTIMER_H */
3235 Index: linux-2.6.35/arch/arm/plat-omap/include/mach/dsp_common.h
3236 ===================================================================
3237 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
3238 +++ linux-2.6.35/arch/arm/plat-omap/include/mach/dsp_common.h 2010-08-08 12:56:48.000000000 +0200
3239 @@ -0,0 +1,40 @@
3240 +/*
3241 + * This file is part of OMAP DSP driver (DSP Gateway version 3.3.1)
3242 + *
3243 + * Copyright (C) 2004-2006 Nokia Corporation. All rights reserved.
3244 + *
3245 + * Contact: Toshihiro Kobayashi <toshihiro.kobayashi@nokia.com>
3246 + *
3247 + * This program is free software; you can redistribute it and/or
3248 + * modify it under the terms of the GNU General Public License
3249 + * version 2 as published by the Free Software Foundation.
3250 + *
3251 + * This program is distributed in the hope that it will be useful, but
3252 + * WITHOUT ANY WARRANTY; without even the implied warranty of
3253 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
3254 + * General Public License for more details.
3255 + *
3256 + * You should have received a copy of the GNU General Public License
3257 + * along with this program; if not, write to the Free Software
3258 + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
3259 + * 02110-1301 USA
3260 + *
3261 + */
3262 +
3263 +#ifndef ASM_ARCH_DSP_COMMON_H
3264 +#define ASM_ARCH_DSP_COMMON_H
3265 +
3266 +#if defined(CONFIG_ARCH_OMAP1) && defined(CONFIG_OMAP_MMU_FWK)
3267 +extern void omap_dsp_request_mpui(void);
3268 +extern void omap_dsp_release_mpui(void);
3269 +extern int omap_dsp_request_mem(void);
3270 +extern int omap_dsp_release_mem(void);
3271 +#else
3272 +static inline int omap_dsp_request_mem(void)
3273 +{
3274 + return 0;
3275 +}
3276 +#define omap_dsp_release_mem() do {} while (0)
3277 +#endif
3278 +
3279 +#endif /* ASM_ARCH_DSP_COMMON_H */
3280 Index: linux-2.6.35/arch/arm/plat-omap/include/mach/fpga.h
3281 ===================================================================
3282 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
3283 +++ linux-2.6.35/arch/arm/plat-omap/include/mach/fpga.h 2010-08-08 12:56:49.000000000 +0200
3284 @@ -0,0 +1,197 @@
3285 +/*
3286 + * arch/arm/plat-omap/include/mach/fpga.h
3287 + *
3288 + * Interrupt handler for OMAP-1510 FPGA
3289 + *
3290 + * Copyright (C) 2001 RidgeRun, Inc.
3291 + * Author: Greg Lonnon <glonnon@ridgerun.com>
3292 + *
3293 + * Copyright (C) 2002 MontaVista Software, Inc.
3294 + *
3295 + * Separated FPGA interrupts from innovator1510.c and cleaned up for 2.6
3296 + * Copyright (C) 2004 Nokia Corporation by Tony Lindrgen <tony@atomide.com>
3297 + *
3298 + * This program is free software; you can redistribute it and/or modify
3299 + * it under the terms of the GNU General Public License version 2 as
3300 + * published by the Free Software Foundation.
3301 + */
3302 +
3303 +#ifndef __ASM_ARCH_OMAP_FPGA_H
3304 +#define __ASM_ARCH_OMAP_FPGA_H
3305 +
3306 +#if defined(CONFIG_MACH_OMAP_INNOVATOR) && defined(CONFIG_ARCH_OMAP15XX)
3307 +extern void omap1510_fpga_init_irq(void);
3308 +#else
3309 +#define omap1510_fpga_init_irq() (0)
3310 +#endif
3311 +
3312 +#define fpga_read(reg) __raw_readb(reg)
3313 +#define fpga_write(val, reg) __raw_writeb(val, reg)
3314 +
3315 +/*
3316 + * ---------------------------------------------------------------------------
3317 + * H2/P2 Debug board FPGA
3318 + * ---------------------------------------------------------------------------
3319 + */
3320 +/* maps in the FPGA registers and the ETHR registers */
3321 +#define H2P2_DBG_FPGA_BASE IOMEM(0xE8000000) /* VA */
3322 +#define H2P2_DBG_FPGA_SIZE SZ_4K /* SIZE */
3323 +#define H2P2_DBG_FPGA_START 0x04000000 /* PA */
3324 +
3325 +#define H2P2_DBG_FPGA_ETHR_START (H2P2_DBG_FPGA_START + 0x300)
3326 +#define H2P2_DBG_FPGA_FPGA_REV (H2P2_DBG_FPGA_BASE + 0x10) /* FPGA Revision */
3327 +#define H2P2_DBG_FPGA_BOARD_REV (H2P2_DBG_FPGA_BASE + 0x12) /* Board Revision */
3328 +#define H2P2_DBG_FPGA_GPIO (H2P2_DBG_FPGA_BASE + 0x14) /* GPIO outputs */
3329 +#define H2P2_DBG_FPGA_LEDS (H2P2_DBG_FPGA_BASE + 0x16) /* LEDs outputs */
3330 +#define H2P2_DBG_FPGA_MISC_INPUTS (H2P2_DBG_FPGA_BASE + 0x18) /* Misc inputs */
3331 +#define H2P2_DBG_FPGA_LAN_STATUS (H2P2_DBG_FPGA_BASE + 0x1A) /* LAN Status line */
3332 +#define H2P2_DBG_FPGA_LAN_RESET (H2P2_DBG_FPGA_BASE + 0x1C) /* LAN Reset line */
3333 +
3334 +/* NOTE: most boards don't have a static mapping for the FPGA ... */
3335 +struct h2p2_dbg_fpga {
3336 + /* offset 0x00 */
3337 + u16 smc91x[8];
3338 + /* offset 0x10 */
3339 + u16 fpga_rev;
3340 + u16 board_rev;
3341 + u16 gpio_outputs;
3342 + u16 leds;
3343 + /* offset 0x18 */
3344 + u16 misc_inputs;
3345 + u16 lan_status;
3346 + u16 lan_reset;
3347 + u16 reserved0;
3348 + /* offset 0x20 */
3349 + u16 ps2_data;
3350 + u16 ps2_ctrl;
3351 + /* plus also 4 rs232 ports ... */
3352 +};
3353 +
3354 +/* LEDs definition on debug board (16 LEDs, all physically green) */
3355 +#define H2P2_DBG_FPGA_LED_GREEN (1 << 15)
3356 +#define H2P2_DBG_FPGA_LED_AMBER (1 << 14)
3357 +#define H2P2_DBG_FPGA_LED_RED (1 << 13)
3358 +#define H2P2_DBG_FPGA_LED_BLUE (1 << 12)
3359 +/* cpu0 load-meter LEDs */
3360 +#define H2P2_DBG_FPGA_LOAD_METER (1 << 0) // A bit of fun on our board ...
3361 +#define H2P2_DBG_FPGA_LOAD_METER_SIZE 11
3362 +#define H2P2_DBG_FPGA_LOAD_METER_MASK ((1 << H2P2_DBG_FPGA_LOAD_METER_SIZE) - 1)
3363 +
3364 +#define H2P2_DBG_FPGA_P2_LED_TIMER (1 << 0)
3365 +#define H2P2_DBG_FPGA_P2_LED_IDLE (1 << 1)
3366 +
3367 +/*
3368 + * ---------------------------------------------------------------------------
3369 + * OMAP-1510 FPGA
3370 + * ---------------------------------------------------------------------------
3371 + */
3372 +#define OMAP1510_FPGA_BASE IOMEM(0xE8000000) /* VA */
3373 +#define OMAP1510_FPGA_SIZE SZ_4K
3374 +#define OMAP1510_FPGA_START 0x08000000 /* PA */
3375 +
3376 +/* Revision */
3377 +#define OMAP1510_FPGA_REV_LOW (OMAP1510_FPGA_BASE + 0x0)
3378 +#define OMAP1510_FPGA_REV_HIGH (OMAP1510_FPGA_BASE + 0x1)
3379 +
3380 +#define OMAP1510_FPGA_LCD_PANEL_CONTROL (OMAP1510_FPGA_BASE + 0x2)
3381 +#define OMAP1510_FPGA_LED_DIGIT (OMAP1510_FPGA_BASE + 0x3)
3382 +#define INNOVATOR_FPGA_HID_SPI (OMAP1510_FPGA_BASE + 0x4)
3383 +#define OMAP1510_FPGA_POWER (OMAP1510_FPGA_BASE + 0x5)
3384 +
3385 +/* Interrupt status */
3386 +#define OMAP1510_FPGA_ISR_LO (OMAP1510_FPGA_BASE + 0x6)
3387 +#define OMAP1510_FPGA_ISR_HI (OMAP1510_FPGA_BASE + 0x7)
3388 +
3389 +/* Interrupt mask */
3390 +#define OMAP1510_FPGA_IMR_LO (OMAP1510_FPGA_BASE + 0x8)
3391 +#define OMAP1510_FPGA_IMR_HI (OMAP1510_FPGA_BASE + 0x9)
3392 +
3393 +/* Reset registers */
3394 +#define OMAP1510_FPGA_HOST_RESET (OMAP1510_FPGA_BASE + 0xa)
3395 +#define OMAP1510_FPGA_RST (OMAP1510_FPGA_BASE + 0xb)
3396 +
3397 +#define OMAP1510_FPGA_AUDIO (OMAP1510_FPGA_BASE + 0xc)
3398 +#define OMAP1510_FPGA_DIP (OMAP1510_FPGA_BASE + 0xe)
3399 +#define OMAP1510_FPGA_FPGA_IO (OMAP1510_FPGA_BASE + 0xf)
3400 +#define OMAP1510_FPGA_UART1 (OMAP1510_FPGA_BASE + 0x14)
3401 +#define OMAP1510_FPGA_UART2 (OMAP1510_FPGA_BASE + 0x15)
3402 +#define OMAP1510_FPGA_OMAP1510_STATUS (OMAP1510_FPGA_BASE + 0x16)
3403 +#define OMAP1510_FPGA_BOARD_REV (OMAP1510_FPGA_BASE + 0x18)
3404 +#define OMAP1510P1_PPT_DATA (OMAP1510_FPGA_BASE + 0x100)
3405 +#define OMAP1510P1_PPT_STATUS (OMAP1510_FPGA_BASE + 0x101)
3406 +#define OMAP1510P1_PPT_CONTROL (OMAP1510_FPGA_BASE + 0x102)
3407 +
3408 +#define OMAP1510_FPGA_TOUCHSCREEN (OMAP1510_FPGA_BASE + 0x204)
3409 +
3410 +#define INNOVATOR_FPGA_INFO (OMAP1510_FPGA_BASE + 0x205)
3411 +#define INNOVATOR_FPGA_LCD_BRIGHT_LO (OMAP1510_FPGA_BASE + 0x206)
3412 +#define INNOVATOR_FPGA_LCD_BRIGHT_HI (OMAP1510_FPGA_BASE + 0x207)
3413 +#define INNOVATOR_FPGA_LED_GRN_LO (OMAP1510_FPGA_BASE + 0x208)
3414 +#define INNOVATOR_FPGA_LED_GRN_HI (OMAP1510_FPGA_BASE + 0x209)
3415 +#define INNOVATOR_FPGA_LED_RED_LO (OMAP1510_FPGA_BASE + 0x20a)
3416 +#define INNOVATOR_FPGA_LED_RED_HI (OMAP1510_FPGA_BASE + 0x20b)
3417 +#define INNOVATOR_FPGA_CAM_USB_CONTROL (OMAP1510_FPGA_BASE + 0x20c)
3418 +#define INNOVATOR_FPGA_EXP_CONTROL (OMAP1510_FPGA_BASE + 0x20d)
3419 +#define INNOVATOR_FPGA_ISR2 (OMAP1510_FPGA_BASE + 0x20e)
3420 +#define INNOVATOR_FPGA_IMR2 (OMAP1510_FPGA_BASE + 0x210)
3421 +
3422 +#define OMAP1510_FPGA_ETHR_START (OMAP1510_FPGA_START + 0x300)
3423 +
3424 +/*
3425 + * Power up Giga UART driver, turn on HID clock.
3426 + * Turn off BT power, since we're not using it and it
3427 + * draws power.
3428 + */
3429 +#define OMAP1510_FPGA_RESET_VALUE 0x42
3430 +
3431 +#define OMAP1510_FPGA_PCR_IF_PD0 (1 << 7)
3432 +#define OMAP1510_FPGA_PCR_COM2_EN (1 << 6)
3433 +#define OMAP1510_FPGA_PCR_COM1_EN (1 << 5)
3434 +#define OMAP1510_FPGA_PCR_EXP_PD0 (1 << 4)
3435 +#define OMAP1510_FPGA_PCR_EXP_PD1 (1 << 3)
3436 +#define OMAP1510_FPGA_PCR_48MHZ_CLK (1 << 2)
3437 +#define OMAP1510_FPGA_PCR_4MHZ_CLK (1 << 1)
3438 +#define OMAP1510_FPGA_PCR_RSRVD_BIT0 (1 << 0)
3439 +
3440 +/*
3441 + * Innovator/OMAP1510 FPGA HID register bit definitions
3442 + */
3443 +#define OMAP1510_FPGA_HID_SCLK (1<<0) /* output */
3444 +#define OMAP1510_FPGA_HID_MOSI (1<<1) /* output */
3445 +#define OMAP1510_FPGA_HID_nSS (1<<2) /* output 0/1 chip idle/select */
3446 +#define OMAP1510_FPGA_HID_nHSUS (1<<3) /* output 0/1 host active/suspended */
3447 +#define OMAP1510_FPGA_HID_MISO (1<<4) /* input */
3448 +#define OMAP1510_FPGA_HID_ATN (1<<5) /* input 0/1 chip idle/ATN */
3449 +#define OMAP1510_FPGA_HID_rsrvd (1<<6)
3450 +#define OMAP1510_FPGA_HID_RESETn (1<<7) /* output - 0/1 USAR reset/run */
3451 +
3452 +/* The FPGA IRQ is cascaded through GPIO_13 */
3453 +#define OMAP1510_INT_FPGA (IH_GPIO_BASE + 13)
3454 +
3455 +/* IRQ Numbers for interrupts muxed through the FPGA */
3456 +#define OMAP1510_INT_FPGA_ATN (OMAP_FPGA_IRQ_BASE + 0)
3457 +#define OMAP1510_INT_FPGA_ACK (OMAP_FPGA_IRQ_BASE + 1)
3458 +#define OMAP1510_INT_FPGA2 (OMAP_FPGA_IRQ_BASE + 2)
3459 +#define OMAP1510_INT_FPGA3 (OMAP_FPGA_IRQ_BASE + 3)
3460 +#define OMAP1510_INT_FPGA4 (OMAP_FPGA_IRQ_BASE + 4)
3461 +#define OMAP1510_INT_FPGA5 (OMAP_FPGA_IRQ_BASE + 5)
3462 +#define OMAP1510_INT_FPGA6 (OMAP_FPGA_IRQ_BASE + 6)
3463 +#define OMAP1510_INT_FPGA7 (OMAP_FPGA_IRQ_BASE + 7)
3464 +#define OMAP1510_INT_FPGA8 (OMAP_FPGA_IRQ_BASE + 8)
3465 +#define OMAP1510_INT_FPGA9 (OMAP_FPGA_IRQ_BASE + 9)
3466 +#define OMAP1510_INT_FPGA10 (OMAP_FPGA_IRQ_BASE + 10)
3467 +#define OMAP1510_INT_FPGA11 (OMAP_FPGA_IRQ_BASE + 11)
3468 +#define OMAP1510_INT_FPGA12 (OMAP_FPGA_IRQ_BASE + 12)
3469 +#define OMAP1510_INT_ETHER (OMAP_FPGA_IRQ_BASE + 13)
3470 +#define OMAP1510_INT_FPGAUART1 (OMAP_FPGA_IRQ_BASE + 14)
3471 +#define OMAP1510_INT_FPGAUART2 (OMAP_FPGA_IRQ_BASE + 15)
3472 +#define OMAP1510_INT_FPGA_TS (OMAP_FPGA_IRQ_BASE + 16)
3473 +#define OMAP1510_INT_FPGA17 (OMAP_FPGA_IRQ_BASE + 17)
3474 +#define OMAP1510_INT_FPGA_CAM (OMAP_FPGA_IRQ_BASE + 18)
3475 +#define OMAP1510_INT_FPGA_RTC_A (OMAP_FPGA_IRQ_BASE + 19)
3476 +#define OMAP1510_INT_FPGA_RTC_B (OMAP_FPGA_IRQ_BASE + 20)
3477 +#define OMAP1510_INT_FPGA_CD (OMAP_FPGA_IRQ_BASE + 21)
3478 +#define OMAP1510_INT_FPGA22 (OMAP_FPGA_IRQ_BASE + 22)
3479 +#define OMAP1510_INT_FPGA23 (OMAP_FPGA_IRQ_BASE + 23)
3480 +
3481 +#endif
3482 Index: linux-2.6.35/arch/arm/plat-omap/include/mach/gpio.h
3483 ===================================================================
3484 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
3485 +++ linux-2.6.35/arch/arm/plat-omap/include/mach/gpio.h 2010-08-08 12:56:49.000000000 +0200
3486 @@ -0,0 +1,129 @@
3487 +/*
3488 + * arch/arm/plat-omap/include/mach/gpio.h
3489 + *
3490 + * OMAP GPIO handling defines and functions
3491 + *
3492 + * Copyright (C) 2003-2005 Nokia Corporation
3493 + *
3494 + * Written by Juha Yrjölä <juha.yrjola@nokia.com>
3495 + *
3496 + * This program is free software; you can redistribute it and/or modify
3497 + * it under the terms of the GNU General Public License as published by
3498 + * the Free Software Foundation; either version 2 of the License, or
3499 + * (at your option) any later version.
3500 + *
3501 + * This program is distributed in the hope that it will be useful,
3502 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3503 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3504 + * GNU General Public License for more details.
3505 + *
3506 + * You should have received a copy of the GNU General Public License
3507 + * along with this program; if not, write to the Free Software
3508 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
3509 + *
3510 + */
3511 +
3512 +#ifndef __ASM_ARCH_OMAP_GPIO_H
3513 +#define __ASM_ARCH_OMAP_GPIO_H
3514 +
3515 +#include <linux/io.h>
3516 +#include <mach/irqs.h>
3517 +
3518 +#define OMAP1_MPUIO_BASE 0xfffb5000
3519 +
3520 +#if (defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850))
3521 +
3522 +#define OMAP_MPUIO_INPUT_LATCH 0x00
3523 +#define OMAP_MPUIO_OUTPUT 0x02
3524 +#define OMAP_MPUIO_IO_CNTL 0x04
3525 +#define OMAP_MPUIO_KBR_LATCH 0x08
3526 +#define OMAP_MPUIO_KBC 0x0a
3527 +#define OMAP_MPUIO_GPIO_EVENT_MODE 0x0c
3528 +#define OMAP_MPUIO_GPIO_INT_EDGE 0x0e
3529 +#define OMAP_MPUIO_KBD_INT 0x10
3530 +#define OMAP_MPUIO_GPIO_INT 0x12
3531 +#define OMAP_MPUIO_KBD_MASKIT 0x14
3532 +#define OMAP_MPUIO_GPIO_MASKIT 0x16
3533 +#define OMAP_MPUIO_GPIO_DEBOUNCING 0x18
3534 +#define OMAP_MPUIO_LATCH 0x1a
3535 +#else
3536 +#define OMAP_MPUIO_INPUT_LATCH 0x00
3537 +#define OMAP_MPUIO_OUTPUT 0x04
3538 +#define OMAP_MPUIO_IO_CNTL 0x08
3539 +#define OMAP_MPUIO_KBR_LATCH 0x10
3540 +#define OMAP_MPUIO_KBC 0x14
3541 +#define OMAP_MPUIO_GPIO_EVENT_MODE 0x18
3542 +#define OMAP_MPUIO_GPIO_INT_EDGE 0x1c
3543 +#define OMAP_MPUIO_KBD_INT 0x20
3544 +#define OMAP_MPUIO_GPIO_INT 0x24
3545 +#define OMAP_MPUIO_KBD_MASKIT 0x28
3546 +#define OMAP_MPUIO_GPIO_MASKIT 0x2c
3547 +#define OMAP_MPUIO_GPIO_DEBOUNCING 0x30
3548 +#define OMAP_MPUIO_LATCH 0x34
3549 +#endif
3550 +
3551 +#define OMAP34XX_NR_GPIOS 6
3552 +
3553 +#define OMAP_MPUIO(nr) (OMAP_MAX_GPIO_LINES + (nr))
3554 +#define OMAP_GPIO_IS_MPUIO(nr) ((nr) >= OMAP_MAX_GPIO_LINES)
3555 +
3556 +#define OMAP_GPIO_IRQ(nr) (OMAP_GPIO_IS_MPUIO(nr) ? \
3557 + IH_MPUIO_BASE + ((nr) & 0x0f) : \
3558 + IH_GPIO_BASE + (nr))
3559 +
3560 +extern int omap_gpio_init(void); /* Call from board init only */
3561 +extern void omap2_gpio_prepare_for_retention(void);
3562 +extern void omap2_gpio_resume_after_retention(void);
3563 +extern void omap_set_gpio_debounce(int gpio, int enable);
3564 +extern void omap_set_gpio_debounce_time(int gpio, int enable);
3565 +extern void omap_gpio_save_context(void);
3566 +extern void omap_gpio_restore_context(void);
3567 +/*-------------------------------------------------------------------------*/
3568 +
3569 +/* Wrappers for "new style" GPIO calls, using the new infrastructure
3570 + * which lets us plug in FPGA, I2C, and other implementations.
3571 + * *
3572 + * The original OMAP-specfic calls should eventually be removed.
3573 + */
3574 +
3575 +#include <linux/errno.h>
3576 +#include <asm-generic/gpio.h>
3577 +
3578 +static inline int gpio_get_value(unsigned gpio)
3579 +{
3580 + return __gpio_get_value(gpio);
3581 +}
3582 +
3583 +static inline void gpio_set_value(unsigned gpio, int value)
3584 +{
3585 + __gpio_set_value(gpio, value);
3586 +}
3587 +
3588 +static inline int gpio_cansleep(unsigned gpio)
3589 +{
3590 + return __gpio_cansleep(gpio);
3591 +}
3592 +
3593 +static inline int gpio_to_irq(unsigned gpio)
3594 +{
3595 + return __gpio_to_irq(gpio);
3596 +}
3597 +
3598 +static inline int irq_to_gpio(unsigned irq)
3599 +{
3600 + int tmp;
3601 +
3602 + /* omap1 SOC mpuio */
3603 + if (cpu_class_is_omap1() && (irq < (IH_MPUIO_BASE + 16)))
3604 + return (irq - IH_MPUIO_BASE) + OMAP_MAX_GPIO_LINES;
3605 +
3606 + /* SOC gpio */
3607 + tmp = irq - IH_GPIO_BASE;
3608 + if (tmp < OMAP_MAX_GPIO_LINES)
3609 + return tmp;
3610 +
3611 + /* we don't supply reverse mappings for non-SOC gpios */
3612 + return -EIO;
3613 +}
3614 +
3615 +#endif
3616 Index: linux-2.6.35/arch/arm/plat-omap/include/mach/gpio-switch.h
3617 ===================================================================
3618 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
3619 +++ linux-2.6.35/arch/arm/plat-omap/include/mach/gpio-switch.h 2010-08-08 12:56:50.000000000 +0200
3620 @@ -0,0 +1,54 @@
3621 +/*
3622 + * GPIO switch definitions
3623 + *
3624 + * Copyright (C) 2006 Nokia Corporation
3625 + *
3626 + * This program is free software; you can redistribute it and/or modify
3627 + * it under the terms of the GNU General Public License version 2 as
3628 + * published by the Free Software Foundation.
3629 + */
3630 +
3631 +#ifndef __ASM_ARCH_OMAP_GPIO_SWITCH_H
3632 +#define __ASM_ARCH_OMAP_GPIO_SWITCH_H
3633 +
3634 +#include <linux/types.h>
3635 +
3636 +/* Cover:
3637 + * high -> closed
3638 + * low -> open
3639 + * Connection:
3640 + * high -> connected
3641 + * low -> disconnected
3642 + * Activity:
3643 + * high -> active
3644 + * low -> inactive
3645 + *
3646 + */
3647 +#define OMAP_GPIO_SWITCH_TYPE_COVER 0x0000
3648 +#define OMAP_GPIO_SWITCH_TYPE_CONNECTION 0x0001
3649 +#define OMAP_GPIO_SWITCH_TYPE_ACTIVITY 0x0002
3650 +#define OMAP_GPIO_SWITCH_FLAG_INVERTED 0x0001
3651 +#define OMAP_GPIO_SWITCH_FLAG_OUTPUT 0x0002
3652 +
3653 +struct omap_gpio_switch {
3654 + const char *name;
3655 + s16 gpio;
3656 + unsigned flags:4;
3657 + unsigned type:4;
3658 +
3659 + /* Time in ms to debounce when transitioning from
3660 + * inactive state to active state. */
3661 + u16 debounce_rising;
3662 + /* Same for transition from active to inactive state. */
3663 + u16 debounce_falling;
3664 +
3665 + /* notify board-specific code about state changes */
3666 + void (* notify)(void *data, int state);
3667 + void *notify_data;
3668 +};
3669 +
3670 +/* Call at init time only */
3671 +extern void omap_register_gpio_switches(const struct omap_gpio_switch *tbl,
3672 + int count);
3673 +
3674 +#endif
3675 Index: linux-2.6.35/arch/arm/plat-omap/include/mach/gpmc.h
3676 ===================================================================
3677 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
3678 +++ linux-2.6.35/arch/arm/plat-omap/include/mach/gpmc.h 2010-08-08 12:56:51.000000000 +0200
3679 @@ -0,0 +1,115 @@
3680 +/*
3681 + * General-Purpose Memory Controller for OMAP2
3682 + *
3683 + * Copyright (C) 2005-2006 Nokia Corporation
3684 + *
3685 + * This program is free software; you can redistribute it and/or modify
3686 + * it under the terms of the GNU General Public License version 2 as
3687 + * published by the Free Software Foundation.
3688 + */
3689 +
3690 +#ifndef __OMAP2_GPMC_H
3691 +#define __OMAP2_GPMC_H
3692 +
3693 +/* Maximum Number of Chip Selects */
3694 +#define GPMC_CS_NUM 8
3695 +
3696 +#define GPMC_CS_CONFIG1 0x00
3697 +#define GPMC_CS_CONFIG2 0x04
3698 +#define GPMC_CS_CONFIG3 0x08
3699 +#define GPMC_CS_CONFIG4 0x0c
3700 +#define GPMC_CS_CONFIG5 0x10
3701 +#define GPMC_CS_CONFIG6 0x14
3702 +#define GPMC_CS_CONFIG7 0x18
3703 +#define GPMC_CS_NAND_COMMAND 0x1c
3704 +#define GPMC_CS_NAND_ADDRESS 0x20
3705 +#define GPMC_CS_NAND_DATA 0x24
3706 +
3707 +#define GPMC_CONFIG 0x50
3708 +#define GPMC_STATUS 0x54
3709 +
3710 +#define GPMC_CONFIG1_WRAPBURST_SUPP (1 << 31)
3711 +#define GPMC_CONFIG1_READMULTIPLE_SUPP (1 << 30)
3712 +#define GPMC_CONFIG1_READTYPE_ASYNC (0 << 29)
3713 +#define GPMC_CONFIG1_READTYPE_SYNC (1 << 29)
3714 +#define GPMC_CONFIG1_WRITEMULTIPLE_SUPP (1 << 28)
3715 +#define GPMC_CONFIG1_WRITETYPE_ASYNC (0 << 27)
3716 +#define GPMC_CONFIG1_WRITETYPE_SYNC (1 << 27)
3717 +#define GPMC_CONFIG1_CLKACTIVATIONTIME(val) ((val & 3) << 25)
3718 +#define GPMC_CONFIG1_PAGE_LEN(val) ((val & 3) << 23)
3719 +#define GPMC_CONFIG1_WAIT_READ_MON (1 << 22)
3720 +#define GPMC_CONFIG1_WAIT_WRITE_MON (1 << 21)
3721 +#define GPMC_CONFIG1_WAIT_MON_IIME(val) ((val & 3) << 18)
3722 +#define GPMC_CONFIG1_WAIT_PIN_SEL(val) ((val & 3) << 16)
3723 +#define GPMC_CONFIG1_DEVICESIZE(val) ((val & 3) << 12)
3724 +#define GPMC_CONFIG1_DEVICESIZE_16 GPMC_CONFIG1_DEVICESIZE(1)
3725 +#define GPMC_CONFIG1_DEVICETYPE(val) ((val & 3) << 10)
3726 +#define GPMC_CONFIG1_DEVICETYPE_NOR GPMC_CONFIG1_DEVICETYPE(0)
3727 +#define GPMC_CONFIG1_DEVICETYPE_NAND GPMC_CONFIG1_DEVICETYPE(2)
3728 +#define GPMC_CONFIG1_MUXADDDATA (1 << 9)
3729 +#define GPMC_CONFIG1_TIME_PARA_GRAN (1 << 4)
3730 +#define GPMC_CONFIG1_FCLK_DIV(val) (val & 3)
3731 +#define GPMC_CONFIG1_FCLK_DIV2 (GPMC_CONFIG1_FCLK_DIV(1))
3732 +#define GPMC_CONFIG1_FCLK_DIV3 (GPMC_CONFIG1_FCLK_DIV(2))
3733 +#define GPMC_CONFIG1_FCLK_DIV4 (GPMC_CONFIG1_FCLK_DIV(3))
3734 +#define GPMC_CONFIG7_CSVALID (1 << 6)
3735 +
3736 +/*
3737 + * Note that all values in this struct are in nanoseconds, while
3738 + * the register values are in gpmc_fck cycles.
3739 + */
3740 +struct gpmc_timings {
3741 + /* Minimum clock period for synchronous mode */
3742 + u16 sync_clk;
3743 +
3744 + /* Chip-select signal timings corresponding to GPMC_CS_CONFIG2 */
3745 + u16 cs_on; /* Assertion time */
3746 + u16 cs_rd_off; /* Read deassertion time */
3747 + u16 cs_wr_off; /* Write deassertion time */
3748 +
3749 + /* ADV signal timings corresponding to GPMC_CONFIG3 */
3750 + u16 adv_on; /* Assertion time */
3751 + u16 adv_rd_off; /* Read deassertion time */
3752 + u16 adv_wr_off; /* Write deassertion time */
3753 +
3754 + /* WE signals timings corresponding to GPMC_CONFIG4 */
3755 + u16 we_on; /* WE assertion time */
3756 + u16 we_off; /* WE deassertion time */
3757 +
3758 + /* OE signals timings corresponding to GPMC_CONFIG4 */
3759 + u16 oe_on; /* OE assertion time */
3760 + u16 oe_off; /* OE deassertion time */
3761 +
3762 + /* Access time and cycle time timings corresponding to GPMC_CONFIG5 */
3763 + u16 page_burst_access; /* Multiple access word delay */
3764 + u16 access; /* Start-cycle to first data valid delay */
3765 + u16 rd_cycle; /* Total read cycle time */
3766 + u16 wr_cycle; /* Total write cycle time */
3767 +
3768 + /* The following are only on OMAP3430 */
3769 + u16 wr_access; /* WRACCESSTIME */
3770 + u16 wr_data_mux_bus; /* WRDATAONADMUXBUS */
3771 +};
3772 +
3773 +extern unsigned int gpmc_ns_to_ticks(unsigned int time_ns);
3774 +extern unsigned int gpmc_ticks_to_ns(unsigned int ticks);
3775 +extern unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns);
3776 +extern unsigned long gpmc_get_fclk_period(void);
3777 +
3778 +extern void gpmc_cs_write_reg(int cs, int idx, u32 val);
3779 +extern u32 gpmc_cs_read_reg(int cs, int idx);
3780 +extern int gpmc_cs_calc_divider(int cs, unsigned int sync_clk);
3781 +extern int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t);
3782 +extern int gpmc_cs_request(int cs, unsigned long size, unsigned long *base);
3783 +extern void gpmc_cs_free(int cs);
3784 +extern int gpmc_cs_set_reserved(int cs, int reserved);
3785 +extern int gpmc_cs_reserved(int cs);
3786 +extern int gpmc_prefetch_enable(int cs, int dma_mode,
3787 + unsigned int u32_count, int is_write);
3788 +extern void gpmc_prefetch_reset(void);
3789 +extern int gpmc_prefetch_status(void);
3790 +extern void omap3_gpmc_save_context(void);
3791 +extern void omap3_gpmc_restore_context(void);
3792 +extern void __init gpmc_init(void);
3793 +
3794 +#endif
3795 Index: linux-2.6.35/arch/arm/plat-omap/include/mach/gpmc-smc91x.h
3796 ===================================================================
3797 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
3798 +++ linux-2.6.35/arch/arm/plat-omap/include/mach/gpmc-smc91x.h 2010-08-08 12:56:51.000000000 +0200
3799 @@ -0,0 +1,42 @@
3800 +/*
3801 + * arch/arm/plat-omap/include/mach/gpmc-smc91x.h
3802 + *
3803 + * Copyright (C) 2009 Nokia Corporation
3804 + *
3805 + * This program is free software; you can redistribute it and/or modify
3806 + * it under the terms of the GNU General Public License version 2 as
3807 + * published by the Free Software Foundation.
3808 + */
3809 +
3810 +#ifndef __ASM_ARCH_OMAP_GPMC_SMC91X_H__
3811 +
3812 +#define GPMC_TIMINGS_SMC91C96 (1 << 4)
3813 +#define GPMC_MUX_ADD_DATA (1 << 5) /* GPMC_CONFIG1_MUXADDDATA */
3814 +#define GPMC_READ_MON (1 << 6) /* GPMC_CONFIG1_WAIT_READ_MON */
3815 +#define GPMC_WRITE_MON (1 << 7) /* GPMC_CONFIG1_WAIT_WRITE_MON */
3816 +
3817 +struct omap_smc91x_platform_data {
3818 + int cs;
3819 + int gpio_irq;
3820 + int gpio_pwrdwn;
3821 + int gpio_reset;
3822 + int wait_pin; /* Optional GPMC_CONFIG1_WAITPINSELECT */
3823 + u32 flags;
3824 + int (*retime)(void);
3825 +};
3826 +
3827 +#if defined(CONFIG_SMC91X) || \
3828 + defined(CONFIG_SMC91X_MODULE)
3829 +
3830 +extern void gpmc_smc91x_init(struct omap_smc91x_platform_data *d);
3831 +
3832 +#else
3833 +
3834 +#define board_smc91x_data NULL
3835 +
3836 +static inline void gpmc_smc91x_init(struct omap_smc91x_platform_data *d)
3837 +{
3838 +}
3839 +
3840 +#endif
3841 +#endif
3842 Index: linux-2.6.35/arch/arm/plat-omap/include/mach/hardware.h
3843 ===================================================================
3844 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
3845 +++ linux-2.6.35/arch/arm/plat-omap/include/mach/hardware.h 2010-08-08 12:56:52.000000000 +0200
3846 @@ -0,0 +1,290 @@
3847 +/*
3848 + * arch/arm/plat-omap/include/mach/hardware.h
3849 + *
3850 + * Hardware definitions for TI OMAP processors and boards
3851 + *
3852 + * NOTE: Please put device driver specific defines into a separate header
3853 + * file for each driver.
3854 + *
3855 + * Copyright (C) 2001 RidgeRun, Inc.
3856 + * Author: RidgeRun, Inc. Greg Lonnon <glonnon@ridgerun.com>
3857 + *
3858 + * Reorganized for Linux-2.6 by Tony Lindgren <tony@atomide.com>
3859 + * and Dirk Behme <dirk.behme@de.bosch.com>
3860 + *
3861 + * This program is free software; you can redistribute it and/or modify it
3862 + * under the terms of the GNU General Public License as published by the
3863 + * Free Software Foundation; either version 2 of the License, or (at your
3864 + * option) any later version.
3865 + *
3866 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
3867 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
3868 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
3869 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
3870 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
3871 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
3872 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
3873 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
3874 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
3875 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3876 + *
3877 + * You should have received a copy of the GNU General Public License along
3878 + * with this program; if not, write to the Free Software Foundation, Inc.,
3879 + * 675 Mass Ave, Cambridge, MA 02139, USA.
3880 + */
3881 +
3882 +#ifndef __ASM_ARCH_OMAP_HARDWARE_H
3883 +#define __ASM_ARCH_OMAP_HARDWARE_H
3884 +
3885 +#include <asm/sizes.h>
3886 +#ifndef __ASSEMBLER__
3887 +#include <asm/types.h>
3888 +#include <plat/cpu.h>
3889 +#endif
3890 +#include <plat/serial.h>
3891 +
3892 +/*
3893 + * ---------------------------------------------------------------------------
3894 + * Common definitions for all OMAP processors
3895 + * NOTE: Put all processor or board specific parts to the special header
3896 + * files.
3897 + * ---------------------------------------------------------------------------
3898 + */
3899 +
3900 +/*
3901 + * ----------------------------------------------------------------------------
3902 + * Timers
3903 + * ----------------------------------------------------------------------------
3904 + */
3905 +#define OMAP_MPU_TIMER1_BASE (0xfffec500)
3906 +#define OMAP_MPU_TIMER2_BASE (0xfffec600)
3907 +#define OMAP_MPU_TIMER3_BASE (0xfffec700)
3908 +#define MPU_TIMER_FREE (1 << 6)
3909 +#define MPU_TIMER_CLOCK_ENABLE (1 << 5)
3910 +#define MPU_TIMER_AR (1 << 1)
3911 +#define MPU_TIMER_ST (1 << 0)
3912 +
3913 +/*
3914 + * ----------------------------------------------------------------------------
3915 + * Clocks
3916 + * ----------------------------------------------------------------------------
3917 + */
3918 +#define CLKGEN_REG_BASE (0xfffece00)
3919 +#define ARM_CKCTL (CLKGEN_REG_BASE + 0x0)
3920 +#define ARM_IDLECT1 (CLKGEN_REG_BASE + 0x4)
3921 +#define ARM_IDLECT2 (CLKGEN_REG_BASE + 0x8)
3922 +#define ARM_EWUPCT (CLKGEN_REG_BASE + 0xC)
3923 +#define ARM_RSTCT1 (CLKGEN_REG_BASE + 0x10)
3924 +#define ARM_RSTCT2 (CLKGEN_REG_BASE + 0x14)
3925 +#define ARM_SYSST (CLKGEN_REG_BASE + 0x18)
3926 +#define ARM_IDLECT3 (CLKGEN_REG_BASE + 0x24)
3927 +
3928 +#define CK_RATEF 1
3929 +#define CK_IDLEF 2
3930 +#define CK_ENABLEF 4
3931 +#define CK_SELECTF 8
3932 +#define SETARM_IDLE_SHIFT
3933 +
3934 +/* DPLL control registers */
3935 +#define DPLL_CTL (0xfffecf00)
3936 +
3937 +/* DSP clock control. Must use __raw_readw() and __raw_writew() with these */
3938 +#define DSP_CONFIG_REG_BASE IOMEM(0xe1008000)
3939 +#define DSP_CKCTL (DSP_CONFIG_REG_BASE + 0x0)
3940 +#define DSP_IDLECT1 (DSP_CONFIG_REG_BASE + 0x4)
3941 +#define DSP_IDLECT2 (DSP_CONFIG_REG_BASE + 0x8)
3942 +#define DSP_RSTCT2 (DSP_CONFIG_REG_BASE + 0x14)
3943 +
3944 +/*
3945 + * ---------------------------------------------------------------------------
3946 + * UPLD
3947 + * ---------------------------------------------------------------------------
3948 + */
3949 +#define ULPD_REG_BASE (0xfffe0800)
3950 +#define ULPD_IT_STATUS (ULPD_REG_BASE + 0x14)
3951 +#define ULPD_SETUP_ANALOG_CELL_3 (ULPD_REG_BASE + 0x24)
3952 +#define ULPD_CLOCK_CTRL (ULPD_REG_BASE + 0x30)
3953 +# define DIS_USB_PVCI_CLK (1 << 5) /* no USB/FAC synch */
3954 +# define USB_MCLK_EN (1 << 4) /* enable W4_USB_CLKO */
3955 +#define ULPD_SOFT_REQ (ULPD_REG_BASE + 0x34)
3956 +# define SOFT_UDC_REQ (1 << 4)
3957 +# define SOFT_USB_CLK_REQ (1 << 3)
3958 +# define SOFT_DPLL_REQ (1 << 0)
3959 +#define ULPD_DPLL_CTRL (ULPD_REG_BASE + 0x3c)
3960 +#define ULPD_STATUS_REQ (ULPD_REG_BASE + 0x40)
3961 +#define ULPD_APLL_CTRL (ULPD_REG_BASE + 0x4c)
3962 +#define ULPD_POWER_CTRL (ULPD_REG_BASE + 0x50)
3963 +#define ULPD_SOFT_DISABLE_REQ_REG (ULPD_REG_BASE + 0x68)
3964 +# define DIS_MMC2_DPLL_REQ (1 << 11)
3965 +# define DIS_MMC1_DPLL_REQ (1 << 10)
3966 +# define DIS_UART3_DPLL_REQ (1 << 9)
3967 +# define DIS_UART2_DPLL_REQ (1 << 8)
3968 +# define DIS_UART1_DPLL_REQ (1 << 7)
3969 +# define DIS_USB_HOST_DPLL_REQ (1 << 6)
3970 +#define ULPD_SDW_CLK_DIV_CTRL_SEL (ULPD_REG_BASE + 0x74)
3971 +#define ULPD_CAM_CLK_CTRL (ULPD_REG_BASE + 0x7c)
3972 +
3973 +/*
3974 + * ---------------------------------------------------------------------------
3975 + * Watchdog timer
3976 + * ---------------------------------------------------------------------------
3977 + */
3978 +
3979 +/* Watchdog timer within the OMAP3.2 gigacell */
3980 +#define OMAP_MPU_WATCHDOG_BASE (0xfffec800)
3981 +#define OMAP_WDT_TIMER (OMAP_MPU_WATCHDOG_BASE + 0x0)
3982 +#define OMAP_WDT_LOAD_TIM (OMAP_MPU_WATCHDOG_BASE + 0x4)
3983 +#define OMAP_WDT_READ_TIM (OMAP_MPU_WATCHDOG_BASE + 0x4)
3984 +#define OMAP_WDT_TIMER_MODE (OMAP_MPU_WATCHDOG_BASE + 0x8)
3985 +
3986 +/*
3987 + * ---------------------------------------------------------------------------
3988 + * Interrupts
3989 + * ---------------------------------------------------------------------------
3990 + */
3991 +#ifdef CONFIG_ARCH_OMAP1
3992 +
3993 +/*
3994 + * XXX: These probably want to be moved to arch/arm/mach-omap/omap1/irq.c
3995 + * or something similar.. -- PFM.
3996 + */
3997 +
3998 +#define OMAP_IH1_BASE 0xfffecb00
3999 +#define OMAP_IH2_BASE 0xfffe0000
4000 +
4001 +#define OMAP_IH1_ITR (OMAP_IH1_BASE + 0x00)
4002 +#define OMAP_IH1_MIR (OMAP_IH1_BASE + 0x04)
4003 +#define OMAP_IH1_SIR_IRQ (OMAP_IH1_BASE + 0x10)
4004 +#define OMAP_IH1_SIR_FIQ (OMAP_IH1_BASE + 0x14)
4005 +#define OMAP_IH1_CONTROL (OMAP_IH1_BASE + 0x18)
4006 +#define OMAP_IH1_ILR0 (OMAP_IH1_BASE + 0x1c)
4007 +#define OMAP_IH1_ISR (OMAP_IH1_BASE + 0x9c)
4008 +
4009 +#define OMAP_IH2_ITR (OMAP_IH2_BASE + 0x00)
4010 +#define OMAP_IH2_MIR (OMAP_IH2_BASE + 0x04)
4011 +#define OMAP_IH2_SIR_IRQ (OMAP_IH2_BASE + 0x10)
4012 +#define OMAP_IH2_SIR_FIQ (OMAP_IH2_BASE + 0x14)
4013 +#define OMAP_IH2_CONTROL (OMAP_IH2_BASE + 0x18)
4014 +#define OMAP_IH2_ILR0 (OMAP_IH2_BASE + 0x1c)
4015 +#define OMAP_IH2_ISR (OMAP_IH2_BASE + 0x9c)
4016 +
4017 +#define IRQ_ITR_REG_OFFSET 0x00
4018 +#define IRQ_MIR_REG_OFFSET 0x04
4019 +#define IRQ_SIR_IRQ_REG_OFFSET 0x10
4020 +#define IRQ_SIR_FIQ_REG_OFFSET 0x14
4021 +#define IRQ_CONTROL_REG_OFFSET 0x18
4022 +#define IRQ_ISR_REG_OFFSET 0x9c
4023 +#define IRQ_ILR0_REG_OFFSET 0x1c
4024 +#define IRQ_GMR_REG_OFFSET 0xa0
4025 +
4026 +#endif
4027 +
4028 +/*
4029 + * ----------------------------------------------------------------------------
4030 + * System control registers
4031 + * ----------------------------------------------------------------------------
4032 + */
4033 +#define MOD_CONF_CTRL_0 0xfffe1080
4034 +#define MOD_CONF_CTRL_1 0xfffe1110
4035 +
4036 +/*
4037 + * ----------------------------------------------------------------------------
4038 + * Pin multiplexing registers
4039 + * ----------------------------------------------------------------------------
4040 + */
4041 +#define FUNC_MUX_CTRL_0 0xfffe1000
4042 +#define FUNC_MUX_CTRL_1 0xfffe1004
4043 +#define FUNC_MUX_CTRL_2 0xfffe1008
4044 +#define COMP_MODE_CTRL_0 0xfffe100c
4045 +#define FUNC_MUX_CTRL_3 0xfffe1010
4046 +#define FUNC_MUX_CTRL_4 0xfffe1014
4047 +#define FUNC_MUX_CTRL_5 0xfffe1018
4048 +#define FUNC_MUX_CTRL_6 0xfffe101C
4049 +#define FUNC_MUX_CTRL_7 0xfffe1020
4050 +#define FUNC_MUX_CTRL_8 0xfffe1024
4051 +#define FUNC_MUX_CTRL_9 0xfffe1028
4052 +#define FUNC_MUX_CTRL_A 0xfffe102C
4053 +#define FUNC_MUX_CTRL_B 0xfffe1030
4054 +#define FUNC_MUX_CTRL_C 0xfffe1034
4055 +#define FUNC_MUX_CTRL_D 0xfffe1038
4056 +#define PULL_DWN_CTRL_0 0xfffe1040
4057 +#define PULL_DWN_CTRL_1 0xfffe1044
4058 +#define PULL_DWN_CTRL_2 0xfffe1048
4059 +#define PULL_DWN_CTRL_3 0xfffe104c
4060 +#define PULL_DWN_CTRL_4 0xfffe10ac
4061 +
4062 +/* OMAP-1610 specific multiplexing registers */
4063 +#define FUNC_MUX_CTRL_E 0xfffe1090
4064 +#define FUNC_MUX_CTRL_F 0xfffe1094
4065 +#define FUNC_MUX_CTRL_10 0xfffe1098
4066 +#define FUNC_MUX_CTRL_11 0xfffe109c
4067 +#define FUNC_MUX_CTRL_12 0xfffe10a0
4068 +#define PU_PD_SEL_0 0xfffe10b4
4069 +#define PU_PD_SEL_1 0xfffe10b8
4070 +#define PU_PD_SEL_2 0xfffe10bc
4071 +#define PU_PD_SEL_3 0xfffe10c0
4072 +#define PU_PD_SEL_4 0xfffe10c4
4073 +
4074 +/* Timer32K for 1610 and 1710*/
4075 +#define OMAP_TIMER32K_BASE 0xFFFBC400
4076 +
4077 +/*
4078 + * ---------------------------------------------------------------------------
4079 + * TIPB bus interface
4080 + * ---------------------------------------------------------------------------
4081 + */
4082 +#define TIPB_PUBLIC_CNTL_BASE 0xfffed300
4083 +#define MPU_PUBLIC_TIPB_CNTL (TIPB_PUBLIC_CNTL_BASE + 0x8)
4084 +#define TIPB_PRIVATE_CNTL_BASE 0xfffeca00
4085 +#define MPU_PRIVATE_TIPB_CNTL (TIPB_PRIVATE_CNTL_BASE + 0x8)
4086 +
4087 +/*
4088 + * ----------------------------------------------------------------------------
4089 + * MPUI interface
4090 + * ----------------------------------------------------------------------------
4091 + */
4092 +#define MPUI_BASE (0xfffec900)
4093 +#define MPUI_CTRL (MPUI_BASE + 0x0)
4094 +#define MPUI_DEBUG_ADDR (MPUI_BASE + 0x4)
4095 +#define MPUI_DEBUG_DATA (MPUI_BASE + 0x8)
4096 +#define MPUI_DEBUG_FLAG (MPUI_BASE + 0xc)
4097 +#define MPUI_STATUS_REG (MPUI_BASE + 0x10)
4098 +#define MPUI_DSP_STATUS (MPUI_BASE + 0x14)
4099 +#define MPUI_DSP_BOOT_CONFIG (MPUI_BASE + 0x18)
4100 +#define MPUI_DSP_API_CONFIG (MPUI_BASE + 0x1c)
4101 +
4102 +/*
4103 + * ----------------------------------------------------------------------------
4104 + * LED Pulse Generator
4105 + * ----------------------------------------------------------------------------
4106 + */
4107 +#define OMAP_LPG1_BASE 0xfffbd000
4108 +#define OMAP_LPG2_BASE 0xfffbd800
4109 +#define OMAP_LPG1_LCR (OMAP_LPG1_BASE + 0x00)
4110 +#define OMAP_LPG1_PMR (OMAP_LPG1_BASE + 0x04)
4111 +#define OMAP_LPG2_LCR (OMAP_LPG2_BASE + 0x00)
4112 +#define OMAP_LPG2_PMR (OMAP_LPG2_BASE + 0x04)
4113 +
4114 +/*
4115 + * ----------------------------------------------------------------------------
4116 + * Pulse-Width Light
4117 + * ----------------------------------------------------------------------------
4118 + */
4119 +#define OMAP_PWL_BASE 0xfffb5800
4120 +#define OMAP_PWL_ENABLE (OMAP_PWL_BASE + 0x00)
4121 +#define OMAP_PWL_CLK_ENABLE (OMAP_PWL_BASE + 0x04)
4122 +
4123 +/*
4124 + * ---------------------------------------------------------------------------
4125 + * Processor specific defines
4126 + * ---------------------------------------------------------------------------
4127 + */
4128 +
4129 +#include <plat/omap7xx.h>
4130 +#include <plat/omap1510.h>
4131 +#include <plat/omap16xx.h>
4132 +#include <plat/omap24xx.h>
4133 +#include <plat/omap34xx.h>
4134 +#include <plat/omap44xx.h>
4135 +
4136 +#endif /* __ASM_ARCH_OMAP_HARDWARE_H */
4137 Index: linux-2.6.35/arch/arm/plat-omap/include/mach/hwa742.h
4138 ===================================================================
4139 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
4140 +++ linux-2.6.35/arch/arm/plat-omap/include/mach/hwa742.h 2010-08-08 12:56:53.000000000 +0200
4141 @@ -0,0 +1,8 @@
4142 +#ifndef _HWA742_H
4143 +#define _HWA742_H
4144 +
4145 +struct hwa742_platform_data {
4146 + unsigned te_connected:1;
4147 +};
4148 +
4149 +#endif
4150 Index: linux-2.6.35/arch/arm/plat-omap/include/mach/i2c.h
4151 ===================================================================
4152 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
4153 +++ linux-2.6.35/arch/arm/plat-omap/include/mach/i2c.h 2010-08-08 12:56:53.000000000 +0200
4154 @@ -0,0 +1,39 @@
4155 +/*
4156 + * Helper module for board specific I2C bus registration
4157 + *
4158 + * Copyright (C) 2009 Nokia Corporation.
4159 + *
4160 + * This program is free software; you can redistribute it and/or
4161 + * modify it under the terms of the GNU General Public License
4162 + * version 2 as published by the Free Software Foundation.
4163 + *
4164 + * This program is distributed in the hope that it will be useful, but
4165 + * WITHOUT ANY WARRANTY; without even the implied warranty of
4166 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
4167 + * General Public License for more details.
4168 + *
4169 + * You should have received a copy of the GNU General Public License
4170 + * along with this program; if not, write to the Free Software
4171 + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
4172 + * 02110-1301 USA
4173 + *
4174 + */
4175 +
4176 +#include <linux/i2c.h>
4177 +
4178 +#if defined(CONFIG_I2C_OMAP) || defined(CONFIG_I2C_OMAP_MODULE)
4179 +extern int omap_register_i2c_bus(int bus_id, u32 clkrate,
4180 + struct i2c_board_info const *info,
4181 + unsigned len);
4182 +#else
4183 +static inline int omap_register_i2c_bus(int bus_id, u32 clkrate,
4184 + struct i2c_board_info const *info,
4185 + unsigned len)
4186 +{
4187 + return 0;
4188 +}
4189 +#endif
4190 +
4191 +int omap_plat_register_i2c_bus(int bus_id, u32 clkrate,
4192 + struct i2c_board_info const *info,
4193 + unsigned len);
4194 Index: linux-2.6.35/arch/arm/plat-omap/include/mach/io.h
4195 ===================================================================
4196 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
4197 +++ linux-2.6.35/arch/arm/plat-omap/include/mach/io.h 2010-08-08 12:56:54.000000000 +0200
4198 @@ -0,0 +1,287 @@
4199 +/*
4200 + * arch/arm/plat-omap/include/mach/io.h
4201 + *
4202 + * IO definitions for TI OMAP processors and boards
4203 + *
4204 + * Copied from arch/arm/mach-sa1100/include/mach/io.h
4205 + * Copyright (C) 1997-1999 Russell King
4206 + *
4207 + * Copyright (C) 2009 Texas Instruments
4208 + * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
4209 + *
4210 + * This program is free software; you can redistribute it and/or modify it
4211 + * under the terms of the GNU General Public License as published by the
4212 + * Free Software Foundation; either version 2 of the License, or (at your
4213 + * option) any later version.
4214 + *
4215 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
4216 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
4217 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
4218 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
4219 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
4220 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
4221 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
4222 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
4223 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
4224 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
4225 + *
4226 + * You should have received a copy of the GNU General Public License along
4227 + * with this program; if not, write to the Free Software Foundation, Inc.,
4228 + * 675 Mass Ave, Cambridge, MA 02139, USA.
4229 + *
4230 + * Modifications:
4231 + * 06-12-1997 RMK Created.
4232 + * 07-04-1999 RMK Major cleanup
4233 + */
4234 +
4235 +#ifndef __ASM_ARM_ARCH_IO_H
4236 +#define __ASM_ARM_ARCH_IO_H
4237 +
4238 +#include <mach/hardware.h>
4239 +
4240 +#define IO_SPACE_LIMIT 0xffffffff
4241 +
4242 +/*
4243 + * We don't actually have real ISA nor PCI buses, but there is so many
4244 + * drivers out there that might just work if we fake them...
4245 + */
4246 +#define __io(a) __typesafe_io(a)
4247 +#define __mem_pci(a) (a)
4248 +
4249 +/*
4250 + * ----------------------------------------------------------------------------
4251 + * I/O mapping
4252 + * ----------------------------------------------------------------------------
4253 + */
4254 +
4255 +#ifdef __ASSEMBLER__
4256 +#define IOMEM(x) (x)
4257 +#else
4258 +#define IOMEM(x) ((void __force __iomem *)(x))
4259 +#endif
4260 +
4261 +#define OMAP1_IO_OFFSET 0x01000000 /* Virtual IO = 0xfefb0000 */
4262 +#define OMAP1_IO_ADDRESS(pa) IOMEM((pa) - OMAP1_IO_OFFSET)
4263 +
4264 +#define OMAP2_L3_IO_OFFSET 0x90000000
4265 +#define OMAP2_L3_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_L3_IO_OFFSET) /* L3 */
4266 +
4267 +
4268 +#define OMAP2_L4_IO_OFFSET 0xb2000000
4269 +#define OMAP2_L4_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_L4_IO_OFFSET) /* L4 */
4270 +
4271 +#define OMAP4_L3_IO_OFFSET 0xb4000000
4272 +#define OMAP4_L3_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_L3_IO_OFFSET) /* L3 */
4273 +
4274 +#define OMAP4_L3_PER_IO_OFFSET 0xb1100000
4275 +#define OMAP4_L3_PER_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_L3_PER_IO_OFFSET)
4276 +
4277 +#define OMAP4_GPMC_IO_OFFSET 0xa9000000
4278 +#define OMAP4_GPMC_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_GPMC_IO_OFFSET)
4279 +
4280 +#define OMAP2_EMU_IO_OFFSET 0xaa800000 /* Emulation */
4281 +#define OMAP2_EMU_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_EMU_IO_OFFSET)
4282 +
4283 +/*
4284 + * ----------------------------------------------------------------------------
4285 + * Omap1 specific IO mapping
4286 + * ----------------------------------------------------------------------------
4287 + */
4288 +
4289 +#define OMAP1_IO_PHYS 0xFFFB0000
4290 +#define OMAP1_IO_SIZE 0x40000
4291 +#define OMAP1_IO_VIRT (OMAP1_IO_PHYS - OMAP1_IO_OFFSET)
4292 +
4293 +/*
4294 + * ----------------------------------------------------------------------------
4295 + * Omap2 specific IO mapping
4296 + * ----------------------------------------------------------------------------
4297 + */
4298 +
4299 +/* We map both L3 and L4 on OMAP2 */
4300 +#define L3_24XX_PHYS L3_24XX_BASE /* 0x68000000 --> 0xf8000000*/
4301 +#define L3_24XX_VIRT (L3_24XX_PHYS + OMAP2_L3_IO_OFFSET)
4302 +#define L3_24XX_SIZE SZ_1M /* 44kB of 128MB used, want 1MB sect */
4303 +#define L4_24XX_PHYS L4_24XX_BASE /* 0x48000000 --> 0xfa000000 */
4304 +#define L4_24XX_VIRT (L4_24XX_PHYS + OMAP2_L4_IO_OFFSET)
4305 +#define L4_24XX_SIZE SZ_1M /* 1MB of 128MB used, want 1MB sect */
4306 +
4307 +#define L4_WK_243X_PHYS L4_WK_243X_BASE /* 0x49000000 --> 0xfb000000 */
4308 +#define L4_WK_243X_VIRT (L4_WK_243X_PHYS + OMAP2_L4_IO_OFFSET)
4309 +#define L4_WK_243X_SIZE SZ_1M
4310 +#define OMAP243X_GPMC_PHYS OMAP243X_GPMC_BASE
4311 +#define OMAP243X_GPMC_VIRT (OMAP243X_GPMC_PHYS + OMAP2_L3_IO_OFFSET)
4312 + /* 0x6e000000 --> 0xfe000000 */
4313 +#define OMAP243X_GPMC_SIZE SZ_1M
4314 +#define OMAP243X_SDRC_PHYS OMAP243X_SDRC_BASE
4315 + /* 0x6D000000 --> 0xfd000000 */
4316 +#define OMAP243X_SDRC_VIRT (OMAP243X_SDRC_PHYS + OMAP2_L3_IO_OFFSET)
4317 +#define OMAP243X_SDRC_SIZE SZ_1M
4318 +#define OMAP243X_SMS_PHYS OMAP243X_SMS_BASE
4319 + /* 0x6c000000 --> 0xfc000000 */
4320 +#define OMAP243X_SMS_VIRT (OMAP243X_SMS_PHYS + OMAP2_L3_IO_OFFSET)
4321 +#define OMAP243X_SMS_SIZE SZ_1M
4322 +
4323 +/* DSP */
4324 +#define DSP_MEM_24XX_PHYS OMAP2420_DSP_MEM_BASE /* 0x58000000 */
4325 +#define DSP_MEM_24XX_VIRT 0xe0000000
4326 +#define DSP_MEM_24XX_SIZE 0x28000
4327 +#define DSP_IPI_24XX_PHYS OMAP2420_DSP_IPI_BASE /* 0x59000000 */
4328 +#define DSP_IPI_24XX_VIRT 0xe1000000
4329 +#define DSP_IPI_24XX_SIZE SZ_4K
4330 +#define DSP_MMU_24XX_PHYS OMAP2420_DSP_MMU_BASE /* 0x5a000000 */
4331 +#define DSP_MMU_24XX_VIRT 0xe2000000
4332 +#define DSP_MMU_24XX_SIZE SZ_4K
4333 +
4334 +/*
4335 + * ----------------------------------------------------------------------------
4336 + * Omap3 specific IO mapping
4337 + * ----------------------------------------------------------------------------
4338 + */
4339 +
4340 +/* We map both L3 and L4 on OMAP3 */
4341 +#define L3_34XX_PHYS L3_34XX_BASE /* 0x68000000 --> 0xf8000000 */
4342 +#define L3_34XX_VIRT (L3_34XX_PHYS + OMAP2_L3_IO_OFFSET)
4343 +#define L3_34XX_SIZE SZ_1M /* 44kB of 128MB used, want 1MB sect */
4344 +
4345 +#define L4_34XX_PHYS L4_34XX_BASE /* 0x48000000 --> 0xfa000000 */
4346 +#define L4_34XX_VIRT (L4_34XX_PHYS + OMAP2_L4_IO_OFFSET)
4347 +#define L4_34XX_SIZE SZ_4M /* 1MB of 128MB used, want 1MB sect */
4348 +
4349 +/*
4350 + * Need to look at the Size 4M for L4.
4351 + * VPOM3430 was not working for Int controller
4352 + */
4353 +
4354 +#define L4_WK_34XX_PHYS L4_WK_34XX_BASE /* 0x48300000 --> 0xfa300000 */
4355 +#define L4_WK_34XX_VIRT (L4_WK_34XX_PHYS + OMAP2_L4_IO_OFFSET)
4356 +#define L4_WK_34XX_SIZE SZ_1M
4357 +
4358 +#define L4_PER_34XX_PHYS L4_PER_34XX_BASE
4359 + /* 0x49000000 --> 0xfb000000 */
4360 +#define L4_PER_34XX_VIRT (L4_PER_34XX_PHYS + OMAP2_L4_IO_OFFSET)
4361 +#define L4_PER_34XX_SIZE SZ_1M
4362 +
4363 +#define L4_EMU_34XX_PHYS L4_EMU_34XX_BASE
4364 + /* 0x54000000 --> 0xfe800000 */
4365 +#define L4_EMU_34XX_VIRT (L4_EMU_34XX_PHYS + OMAP2_EMU_IO_OFFSET)
4366 +#define L4_EMU_34XX_SIZE SZ_8M
4367 +
4368 +#define OMAP34XX_GPMC_PHYS OMAP34XX_GPMC_BASE
4369 + /* 0x6e000000 --> 0xfe000000 */
4370 +#define OMAP34XX_GPMC_VIRT (OMAP34XX_GPMC_PHYS + OMAP2_L3_IO_OFFSET)
4371 +#define OMAP34XX_GPMC_SIZE SZ_1M
4372 +
4373 +#define OMAP343X_SMS_PHYS OMAP343X_SMS_BASE
4374 + /* 0x6c000000 --> 0xfc000000 */
4375 +#define OMAP343X_SMS_VIRT (OMAP343X_SMS_PHYS + OMAP2_L3_IO_OFFSET)
4376 +#define OMAP343X_SMS_SIZE SZ_1M
4377 +
4378 +#define OMAP343X_SDRC_PHYS OMAP343X_SDRC_BASE
4379 + /* 0x6D000000 --> 0xfd000000 */
4380 +#define OMAP343X_SDRC_VIRT (OMAP343X_SDRC_PHYS + OMAP2_L3_IO_OFFSET)
4381 +#define OMAP343X_SDRC_SIZE SZ_1M
4382 +
4383 +/* DSP */
4384 +#define DSP_MEM_34XX_PHYS OMAP34XX_DSP_MEM_BASE /* 0x58000000 */
4385 +#define DSP_MEM_34XX_VIRT 0xe0000000
4386 +#define DSP_MEM_34XX_SIZE 0x28000
4387 +#define DSP_IPI_34XX_PHYS OMAP34XX_DSP_IPI_BASE /* 0x59000000 */
4388 +#define DSP_IPI_34XX_VIRT 0xe1000000
4389 +#define DSP_IPI_34XX_SIZE SZ_4K
4390 +#define DSP_MMU_34XX_PHYS OMAP34XX_DSP_MMU_BASE /* 0x5a000000 */
4391 +#define DSP_MMU_34XX_VIRT 0xe2000000
4392 +#define DSP_MMU_34XX_SIZE SZ_4K
4393 +
4394 +/*
4395 + * ----------------------------------------------------------------------------
4396 + * Omap4 specific IO mapping
4397 + * ----------------------------------------------------------------------------
4398 + */
4399 +
4400 +/* We map both L3 and L4 on OMAP4 */
4401 +#define L3_44XX_PHYS L3_44XX_BASE /* 0x44000000 --> 0xf8000000 */
4402 +#define L3_44XX_VIRT (L3_44XX_PHYS + OMAP4_L3_IO_OFFSET)
4403 +#define L3_44XX_SIZE SZ_1M
4404 +
4405 +#define L4_44XX_PHYS L4_44XX_BASE /* 0x4a000000 --> 0xfc000000 */
4406 +#define L4_44XX_VIRT (L4_44XX_PHYS + OMAP2_L4_IO_OFFSET)
4407 +#define L4_44XX_SIZE SZ_4M
4408 +
4409 +
4410 +#define L4_WK_44XX_PHYS L4_WK_44XX_BASE /* 0x4a300000 --> 0xfc300000 */
4411 +#define L4_WK_44XX_VIRT (L4_WK_44XX_PHYS + OMAP2_L4_IO_OFFSET)
4412 +#define L4_WK_44XX_SIZE SZ_1M
4413 +
4414 +#define L4_PER_44XX_PHYS L4_PER_44XX_BASE
4415 + /* 0x48000000 --> 0xfa000000 */
4416 +#define L4_PER_44XX_VIRT (L4_PER_44XX_PHYS + OMAP2_L4_IO_OFFSET)
4417 +#define L4_PER_44XX_SIZE SZ_4M
4418 +
4419 +#define L4_ABE_44XX_PHYS L4_ABE_44XX_BASE
4420 + /* 0x49000000 --> 0xfb000000 */
4421 +#define L4_ABE_44XX_VIRT (L4_ABE_44XX_PHYS + OMAP2_L4_IO_OFFSET)
4422 +#define L4_ABE_44XX_SIZE SZ_1M
4423 +
4424 +#define L4_EMU_44XX_PHYS L4_EMU_44XX_BASE
4425 + /* 0x54000000 --> 0xfe800000 */
4426 +#define L4_EMU_44XX_VIRT (L4_EMU_44XX_PHYS + OMAP2_EMU_IO_OFFSET)
4427 +#define L4_EMU_44XX_SIZE SZ_8M
4428 +
4429 +#define OMAP44XX_GPMC_PHYS OMAP44XX_GPMC_BASE
4430 + /* 0x50000000 --> 0xf9000000 */
4431 +#define OMAP44XX_GPMC_VIRT (OMAP44XX_GPMC_PHYS + OMAP4_GPMC_IO_OFFSET)
4432 +#define OMAP44XX_GPMC_SIZE SZ_1M
4433 +
4434 +
4435 +#define OMAP44XX_EMIF1_PHYS OMAP44XX_EMIF1_BASE
4436 + /* 0x4c000000 --> 0xfd100000 */
4437 +#define OMAP44XX_EMIF1_VIRT (OMAP44XX_EMIF1_PHYS + OMAP4_L3_PER_IO_OFFSET)
4438 +#define OMAP44XX_EMIF1_SIZE SZ_1M
4439 +
4440 +#define OMAP44XX_EMIF2_PHYS OMAP44XX_EMIF2_BASE
4441 + /* 0x4d000000 --> 0xfd200000 */
4442 +#define OMAP44XX_EMIF2_VIRT (OMAP44XX_EMIF2_PHYS + OMAP4_L3_PER_IO_OFFSET)
4443 +#define OMAP44XX_EMIF2_SIZE SZ_1M
4444 +
4445 +#define OMAP44XX_DMM_PHYS OMAP44XX_DMM_BASE
4446 + /* 0x4e000000 --> 0xfd300000 */
4447 +#define OMAP44XX_DMM_VIRT (OMAP44XX_DMM_PHYS + OMAP4_L3_PER_IO_OFFSET)
4448 +#define OMAP44XX_DMM_SIZE SZ_1M
4449 +/*
4450 + * ----------------------------------------------------------------------------
4451 + * Omap specific register access
4452 + * ----------------------------------------------------------------------------
4453 + */
4454 +
4455 +#ifndef __ASSEMBLER__
4456 +
4457 +/*
4458 + * NOTE: Please use ioremap + __raw_read/write where possible instead of these
4459 + */
4460 +
4461 +extern u8 omap_readb(u32 pa);
4462 +extern u16 omap_readw(u32 pa);
4463 +extern u32 omap_readl(u32 pa);
4464 +extern void omap_writeb(u8 v, u32 pa);
4465 +extern void omap_writew(u16 v, u32 pa);
4466 +extern void omap_writel(u32 v, u32 pa);
4467 +
4468 +struct omap_sdrc_params;
4469 +
4470 +extern void omap1_map_common_io(void);
4471 +extern void omap1_init_common_hw(void);
4472 +
4473 +extern void omap2_map_common_io(void);
4474 +extern void omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
4475 + struct omap_sdrc_params *sdrc_cs1);
4476 +
4477 +#define __arch_ioremap(p,s,t) omap_ioremap(p,s,t)
4478 +#define __arch_iounmap(v) omap_iounmap(v)
4479 +
4480 +void __iomem *omap_ioremap(unsigned long phys, size_t size, unsigned int type);
4481 +void omap_iounmap(volatile void __iomem *addr);
4482 +
4483 +#endif
4484 +
4485 +#endif
4486 Index: linux-2.6.35/arch/arm/plat-omap/include/mach/iommu2.h
4487 ===================================================================
4488 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
4489 +++ linux-2.6.35/arch/arm/plat-omap/include/mach/iommu2.h 2010-08-08 12:56:54.000000000 +0200
4490 @@ -0,0 +1,96 @@
4491 +/*
4492 + * omap iommu: omap2 architecture specific definitions
4493 + *
4494 + * Copyright (C) 2008-2009 Nokia Corporation
4495 + *
4496 + * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
4497 + *
4498 + * This program is free software; you can redistribute it and/or modify
4499 + * it under the terms of the GNU General Public License version 2 as
4500 + * published by the Free Software Foundation.
4501 + */
4502 +
4503 +#ifndef __MACH_IOMMU2_H
4504 +#define __MACH_IOMMU2_H
4505 +
4506 +#include <linux/io.h>
4507 +
4508 +/*
4509 + * MMU Register offsets
4510 + */
4511 +#define MMU_REVISION 0x00
4512 +#define MMU_SYSCONFIG 0x10
4513 +#define MMU_SYSSTATUS 0x14
4514 +#define MMU_IRQSTATUS 0x18
4515 +#define MMU_IRQENABLE 0x1c
4516 +#define MMU_WALKING_ST 0x40
4517 +#define MMU_CNTL 0x44
4518 +#define MMU_FAULT_AD 0x48
4519 +#define MMU_TTB 0x4c
4520 +#define MMU_LOCK 0x50
4521 +#define MMU_LD_TLB 0x54
4522 +#define MMU_CAM 0x58
4523 +#define MMU_RAM 0x5c
4524 +#define MMU_GFLUSH 0x60
4525 +#define MMU_FLUSH_ENTRY 0x64
4526 +#define MMU_READ_CAM 0x68
4527 +#define MMU_READ_RAM 0x6c
4528 +#define MMU_EMU_FAULT_AD 0x70
4529 +
4530 +#define MMU_REG_SIZE 256
4531 +
4532 +/*
4533 + * MMU Register bit definitions
4534 + */
4535 +#define MMU_LOCK_BASE_SHIFT 10
4536 +#define MMU_LOCK_BASE_MASK (0x1f << MMU_LOCK_BASE_SHIFT)
4537 +#define MMU_LOCK_BASE(x) \
4538 + ((x & MMU_LOCK_BASE_MASK) >> MMU_LOCK_BASE_SHIFT)
4539 +
4540 +#define MMU_LOCK_VICT_SHIFT 4
4541 +#define MMU_LOCK_VICT_MASK (0x1f << MMU_LOCK_VICT_SHIFT)
4542 +#define MMU_LOCK_VICT(x) \
4543 + ((x & MMU_LOCK_VICT_MASK) >> MMU_LOCK_VICT_SHIFT)
4544 +
4545 +#define MMU_CAM_VATAG_SHIFT 12
4546 +#define MMU_CAM_VATAG_MASK \
4547 + ((~0UL >> MMU_CAM_VATAG_SHIFT) << MMU_CAM_VATAG_SHIFT)
4548 +#define MMU_CAM_P (1 << 3)
4549 +#define MMU_CAM_V (1 << 2)
4550 +#define MMU_CAM_PGSZ_MASK 3
4551 +#define MMU_CAM_PGSZ_1M (0 << 0)
4552 +#define MMU_CAM_PGSZ_64K (1 << 0)
4553 +#define MMU_CAM_PGSZ_4K (2 << 0)
4554 +#define MMU_CAM_PGSZ_16M (3 << 0)
4555 +
4556 +#define MMU_RAM_PADDR_SHIFT 12
4557 +#define MMU_RAM_PADDR_MASK \
4558 + ((~0UL >> MMU_RAM_PADDR_SHIFT) << MMU_RAM_PADDR_SHIFT)
4559 +#define MMU_RAM_ENDIAN_SHIFT 9
4560 +#define MMU_RAM_ENDIAN_MASK (1 << MMU_RAM_ENDIAN_SHIFT)
4561 +#define MMU_RAM_ENDIAN_BIG (1 << MMU_RAM_ENDIAN_SHIFT)
4562 +#define MMU_RAM_ENDIAN_LITTLE (0 << MMU_RAM_ENDIAN_SHIFT)
4563 +#define MMU_RAM_ELSZ_SHIFT 7
4564 +#define MMU_RAM_ELSZ_MASK (3 << MMU_RAM_ELSZ_SHIFT)
4565 +#define MMU_RAM_ELSZ_8 (0 << MMU_RAM_ELSZ_SHIFT)
4566 +#define MMU_RAM_ELSZ_16 (1 << MMU_RAM_ELSZ_SHIFT)
4567 +#define MMU_RAM_ELSZ_32 (2 << MMU_RAM_ELSZ_SHIFT)
4568 +#define MMU_RAM_ELSZ_NONE (3 << MMU_RAM_ELSZ_SHIFT)
4569 +#define MMU_RAM_MIXED_SHIFT 6
4570 +#define MMU_RAM_MIXED_MASK (1 << MMU_RAM_MIXED_SHIFT)
4571 +#define MMU_RAM_MIXED MMU_RAM_MIXED_MASK
4572 +
4573 +/*
4574 + * register accessors
4575 + */
4576 +static inline u32 iommu_read_reg(struct iommu *obj, size_t offs)
4577 +{
4578 + return __raw_readl(obj->regbase + offs);
4579 +}
4580 +
4581 +static inline void iommu_write_reg(struct iommu *obj, u32 val, size_t offs)
4582 +{
4583 + __raw_writel(val, obj->regbase + offs);
4584 +}
4585 +
4586 +#endif /* __MACH_IOMMU2_H */
4587 Index: linux-2.6.35/arch/arm/plat-omap/include/mach/iommu.h
4588 ===================================================================
4589 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
4590 +++ linux-2.6.35/arch/arm/plat-omap/include/mach/iommu.h 2010-08-08 12:56:55.000000000 +0200
4591 @@ -0,0 +1,168 @@
4592 +/*
4593 + * omap iommu: main structures
4594 + *
4595 + * Copyright (C) 2008-2009 Nokia Corporation
4596 + *
4597 + * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
4598 + *
4599 + * This program is free software; you can redistribute it and/or modify
4600 + * it under the terms of the GNU General Public License version 2 as
4601 + * published by the Free Software Foundation.
4602 + */
4603 +
4604 +#ifndef __MACH_IOMMU_H
4605 +#define __MACH_IOMMU_H
4606 +
4607 +struct iotlb_entry {
4608 + u32 da;
4609 + u32 pa;
4610 + u32 pgsz, prsvd, valid;
4611 + union {
4612 + u16 ap;
4613 + struct {
4614 + u32 endian, elsz, mixed;
4615 + };
4616 + };
4617 +};
4618 +
4619 +struct iommu {
4620 + const char *name;
4621 + struct module *owner;
4622 + struct clk *clk;
4623 + void __iomem *regbase;
4624 + struct device *dev;
4625 +
4626 + unsigned int refcount;
4627 + struct mutex iommu_lock; /* global for this whole object */
4628 +
4629 + /*
4630 + * We don't change iopgd for a situation like pgd for a task,
4631 + * but share it globally for each iommu.
4632 + */
4633 + u32 *iopgd;
4634 + spinlock_t page_table_lock; /* protect iopgd */
4635 +
4636 + int nr_tlb_entries;
4637 +
4638 + struct list_head mmap;
4639 + struct mutex mmap_lock; /* protect mmap */
4640 +
4641 + int (*isr)(struct iommu *obj);
4642 +
4643 + void *ctx; /* iommu context: registres saved area */
4644 +};
4645 +
4646 +struct cr_regs {
4647 + union {
4648 + struct {
4649 + u16 cam_l;
4650 + u16 cam_h;
4651 + };
4652 + u32 cam;
4653 + };
4654 + union {
4655 + struct {
4656 + u16 ram_l;
4657 + u16 ram_h;
4658 + };
4659 + u32 ram;
4660 + };
4661 +};
4662 +
4663 +struct iotlb_lock {
4664 + short base;
4665 + short vict;
4666 +};
4667 +
4668 +/* architecture specific functions */
4669 +struct iommu_functions {
4670 + unsigned long version;
4671 +
4672 + int (*enable)(struct iommu *obj);
4673 + void (*disable)(struct iommu *obj);
4674 + u32 (*fault_isr)(struct iommu *obj, u32 *ra);
4675 +
4676 + void (*tlb_read_cr)(struct iommu *obj, struct cr_regs *cr);
4677 + void (*tlb_load_cr)(struct iommu *obj, struct cr_regs *cr);
4678 +
4679 + struct cr_regs *(*alloc_cr)(struct iommu *obj, struct iotlb_entry *e);
4680 + int (*cr_valid)(struct cr_regs *cr);
4681 + u32 (*cr_to_virt)(struct cr_regs *cr);
4682 + void (*cr_to_e)(struct cr_regs *cr, struct iotlb_entry *e);
4683 + ssize_t (*dump_cr)(struct iommu *obj, struct cr_regs *cr, char *buf);
4684 +
4685 + u32 (*get_pte_attr)(struct iotlb_entry *e);
4686 +
4687 + void (*save_ctx)(struct iommu *obj);
4688 + void (*restore_ctx)(struct iommu *obj);
4689 + ssize_t (*dump_ctx)(struct iommu *obj, char *buf, ssize_t len);
4690 +};
4691 +
4692 +struct iommu_platform_data {
4693 + const char *name;
4694 + const char *clk_name;
4695 + const int nr_tlb_entries;
4696 +};
4697 +
4698 +#if defined(CONFIG_ARCH_OMAP1)
4699 +#error "iommu for this processor not implemented yet"
4700 +#else
4701 +#include <plat/iommu2.h>
4702 +#endif
4703 +
4704 +/*
4705 + * utilities for super page(16MB, 1MB, 64KB and 4KB)
4706 + */
4707 +
4708 +#define iopgsz_max(bytes) \
4709 + (((bytes) >= SZ_16M) ? SZ_16M : \
4710 + ((bytes) >= SZ_1M) ? SZ_1M : \
4711 + ((bytes) >= SZ_64K) ? SZ_64K : \
4712 + ((bytes) >= SZ_4K) ? SZ_4K : 0)
4713 +
4714 +#define bytes_to_iopgsz(bytes) \
4715 + (((bytes) == SZ_16M) ? MMU_CAM_PGSZ_16M : \
4716 + ((bytes) == SZ_1M) ? MMU_CAM_PGSZ_1M : \
4717 + ((bytes) == SZ_64K) ? MMU_CAM_PGSZ_64K : \
4718 + ((bytes) == SZ_4K) ? MMU_CAM_PGSZ_4K : -1)
4719 +
4720 +#define iopgsz_to_bytes(iopgsz) \
4721 + (((iopgsz) == MMU_CAM_PGSZ_16M) ? SZ_16M : \
4722 + ((iopgsz) == MMU_CAM_PGSZ_1M) ? SZ_1M : \
4723 + ((iopgsz) == MMU_CAM_PGSZ_64K) ? SZ_64K : \
4724 + ((iopgsz) == MMU_CAM_PGSZ_4K) ? SZ_4K : 0)
4725 +
4726 +#define iopgsz_ok(bytes) (bytes_to_iopgsz(bytes) >= 0)
4727 +
4728 +/*
4729 + * global functions
4730 + */
4731 +extern u32 iommu_arch_version(void);
4732 +
4733 +extern void iotlb_cr_to_e(struct cr_regs *cr, struct iotlb_entry *e);
4734 +extern u32 iotlb_cr_to_virt(struct cr_regs *cr);
4735 +
4736 +extern int load_iotlb_entry(struct iommu *obj, struct iotlb_entry *e);
4737 +extern void flush_iotlb_page(struct iommu *obj, u32 da);
4738 +extern void flush_iotlb_range(struct iommu *obj, u32 start, u32 end);
4739 +extern void flush_iotlb_all(struct iommu *obj);
4740 +
4741 +extern int iopgtable_store_entry(struct iommu *obj, struct iotlb_entry *e);
4742 +extern size_t iopgtable_clear_entry(struct iommu *obj, u32 iova);
4743 +
4744 +extern struct iommu *iommu_get(const char *name);
4745 +extern void iommu_put(struct iommu *obj);
4746 +
4747 +extern void iommu_save_ctx(struct iommu *obj);
4748 +extern void iommu_restore_ctx(struct iommu *obj);
4749 +
4750 +extern int install_iommu_arch(const struct iommu_functions *ops);
4751 +extern void uninstall_iommu_arch(const struct iommu_functions *ops);
4752 +
4753 +extern int foreach_iommu_device(void *data,
4754 + int (*fn)(struct device *, void *));
4755 +
4756 +extern ssize_t iommu_dump_ctx(struct iommu *obj, char *buf, ssize_t len);
4757 +extern size_t dump_tlb_entries(struct iommu *obj, char *buf, ssize_t len);
4758 +
4759 +#endif /* __MACH_IOMMU_H */
4760 Index: linux-2.6.35/arch/arm/plat-omap/include/mach/iovmm.h
4761 ===================================================================
4762 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
4763 +++ linux-2.6.35/arch/arm/plat-omap/include/mach/iovmm.h 2010-08-08 12:56:56.000000000 +0200
4764 @@ -0,0 +1,94 @@
4765 +/*
4766 + * omap iommu: simple virtual address space management
4767 + *
4768 + * Copyright (C) 2008-2009 Nokia Corporation
4769 + *
4770 + * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
4771 + *
4772 + * This program is free software; you can redistribute it and/or modify
4773 + * it under the terms of the GNU General Public License version 2 as
4774 + * published by the Free Software Foundation.
4775 + */
4776 +
4777 +#ifndef __IOMMU_MMAP_H
4778 +#define __IOMMU_MMAP_H
4779 +
4780 +struct iovm_struct {
4781 + struct iommu *iommu; /* iommu object which this belongs to */
4782 + u32 da_start; /* area definition */
4783 + u32 da_end;
4784 + u32 flags; /* IOVMF_: see below */
4785 + struct list_head list; /* linked in ascending order */
4786 + const struct sg_table *sgt; /* keep 'page' <-> 'da' mapping */
4787 + void *va; /* mpu side mapped address */
4788 +};
4789 +
4790 +/*
4791 + * IOVMF_FLAGS: attribute for iommu virtual memory area(iovma)
4792 + *
4793 + * lower 16 bit is used for h/w and upper 16 bit is for s/w.
4794 + */
4795 +#define IOVMF_SW_SHIFT 16
4796 +#define IOVMF_HW_SIZE (1 << IOVMF_SW_SHIFT)
4797 +#define IOVMF_HW_MASK (IOVMF_HW_SIZE - 1)
4798 +#define IOVMF_SW_MASK (~IOVMF_HW_MASK)UL
4799 +
4800 +/*
4801 + * iovma: h/w flags derived from cam and ram attribute
4802 + */
4803 +#define IOVMF_CAM_MASK (~((1 << 10) - 1))
4804 +#define IOVMF_RAM_MASK (~IOVMF_CAM_MASK)
4805 +
4806 +#define IOVMF_PGSZ_MASK (3 << 0)
4807 +#define IOVMF_PGSZ_1M MMU_CAM_PGSZ_1M
4808 +#define IOVMF_PGSZ_64K MMU_CAM_PGSZ_64K
4809 +#define IOVMF_PGSZ_4K MMU_CAM_PGSZ_4K
4810 +#define IOVMF_PGSZ_16M MMU_CAM_PGSZ_16M
4811 +
4812 +#define IOVMF_ENDIAN_MASK (1 << 9)
4813 +#define IOVMF_ENDIAN_BIG MMU_RAM_ENDIAN_BIG
4814 +#define IOVMF_ENDIAN_LITTLE MMU_RAM_ENDIAN_LITTLE
4815 +
4816 +#define IOVMF_ELSZ_MASK (3 << 7)
4817 +#define IOVMF_ELSZ_8 MMU_RAM_ELSZ_8
4818 +#define IOVMF_ELSZ_16 MMU_RAM_ELSZ_16
4819 +#define IOVMF_ELSZ_32 MMU_RAM_ELSZ_32
4820 +#define IOVMF_ELSZ_NONE MMU_RAM_ELSZ_NONE
4821 +
4822 +#define IOVMF_MIXED_MASK (1 << 6)
4823 +#define IOVMF_MIXED MMU_RAM_MIXED
4824 +
4825 +/*
4826 + * iovma: s/w flags, used for mapping and umapping internally.
4827 + */
4828 +#define IOVMF_MMIO (1 << IOVMF_SW_SHIFT)
4829 +#define IOVMF_ALLOC (2 << IOVMF_SW_SHIFT)
4830 +#define IOVMF_ALLOC_MASK (3 << IOVMF_SW_SHIFT)
4831 +
4832 +/* "superpages" is supported just with physically linear pages */
4833 +#define IOVMF_DISCONT (1 << (2 + IOVMF_SW_SHIFT))
4834 +#define IOVMF_LINEAR (2 << (2 + IOVMF_SW_SHIFT))
4835 +#define IOVMF_LINEAR_MASK (3 << (2 + IOVMF_SW_SHIFT))
4836 +
4837 +#define IOVMF_DA_FIXED (1 << (4 + IOVMF_SW_SHIFT))
4838 +#define IOVMF_DA_ANON (2 << (4 + IOVMF_SW_SHIFT))
4839 +#define IOVMF_DA_MASK (3 << (4 + IOVMF_SW_SHIFT))
4840 +
4841 +
4842 +extern struct iovm_struct *find_iovm_area(struct iommu *obj, u32 da);
4843 +extern u32 iommu_vmap(struct iommu *obj, u32 da,
4844 + const struct sg_table *sgt, u32 flags);
4845 +extern struct sg_table *iommu_vunmap(struct iommu *obj, u32 da);
4846 +extern u32 iommu_vmalloc(struct iommu *obj, u32 da, size_t bytes,
4847 + u32 flags);
4848 +extern void iommu_vfree(struct iommu *obj, const u32 da);
4849 +extern u32 iommu_kmap(struct iommu *obj, u32 da, u32 pa, size_t bytes,
4850 + u32 flags);
4851 +extern void iommu_kunmap(struct iommu *obj, u32 da);
4852 +extern u32 iommu_kmalloc(struct iommu *obj, u32 da, size_t bytes,
4853 + u32 flags);
4854 +extern void iommu_kfree(struct iommu *obj, u32 da);
4855 +
4856 +extern void *da_to_va(struct iommu *obj, u32 da);
4857 +
4858 +#endif /* __IOMMU_MMAP_H */
4859 Index: linux-2.6.35/arch/arm/plat-omap/include/mach/irda.h
4860 ===================================================================
4861 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
4862 +++ linux-2.6.35/arch/arm/plat-omap/include/mach/irda.h 2010-08-08 12:56:57.000000000 +0200
4863 @@ -0,0 +1,33 @@
4864 +/*
4865 + * arch/arm/plat-omap/include/mach/irda.h
4866 + *
4867 + * Copyright (C) 2005-2006 Komal Shah <komal_shah802003@yahoo.com>
4868 + *
4869 + * This program is free software; you can redistribute it and/or modify
4870 + * it under the terms of the GNU General Public License version 2 as
4871 + * published by the Free Software Foundation.
4872 + */
4873 +#ifndef ASMARM_ARCH_IRDA_H
4874 +#define ASMARM_ARCH_IRDA_H
4875 +
4876 +/* board specific transceiver capabilities */
4877 +
4878 +#define IR_SEL 1 /* Selects IrDA */
4879 +#define IR_SIRMODE 2
4880 +#define IR_FIRMODE 4
4881 +#define IR_MIRMODE 8
4882 +
4883 +struct omap_irda_config {
4884 + int transceiver_cap;
4885 + int (*transceiver_mode)(struct device *dev, int mode);
4886 + int (*select_irda)(struct device *dev, int state);
4887 + int rx_channel;
4888 + int tx_channel;
4889 + unsigned long dest_start;
4890 + unsigned long src_start;
4891 + int tx_trigger;
4892 + int rx_trigger;
4893 + int mode;
4894 +};
4895 +
4896 +#endif
4897 Index: linux-2.6.35/arch/arm/plat-omap/include/mach/irqs.h
4898 ===================================================================
4899 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
4900 +++ linux-2.6.35/arch/arm/plat-omap/include/mach/irqs.h 2010-08-08 12:56:57.000000000 +0200
4901 @@ -0,0 +1,506 @@
4902 +/*
4903 + * arch/arm/plat-omap/include/mach/irqs.h
4904 + *
4905 + * Copyright (C) Greg Lonnon 2001
4906 + * Updated for OMAP-1610 by Tony Lindgren <tony@atomide.com>
4907 + *
4908 + * Copyright (C) 2009 Texas Instruments
4909 + * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
4910 + *
4911 + * This program is free software; you can redistribute it and/or modify
4912 + * it under the terms of the GNU General Public License as published by
4913 + * the Free Software Foundation; either version 2 of the License, or
4914 + * (at your option) any later version.
4915 + *
4916 + * This program is distributed in the hope that it will be useful,
4917 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4918 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4919 + * GNU General Public License for more details.
4920 + *
4921 + * You should have received a copy of the GNU General Public License
4922 + * along with this program; if not, write to the Free Software
4923 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
4924 + *
4925 + * NOTE: The interrupt vectors for the OMAP-1509, OMAP-1510, and OMAP-1610
4926 + * are different.
4927 + */
4928 +
4929 +#ifndef __ASM_ARCH_OMAP15XX_IRQS_H
4930 +#define __ASM_ARCH_OMAP15XX_IRQS_H
4931 +
4932 +/*
4933 + * IRQ numbers for interrupt handler 1
4934 + *
4935 + * NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below
4936 + *
4937 + */
4938 +#define INT_CAMERA 1
4939 +#define INT_FIQ 3
4940 +#define INT_RTDX 6
4941 +#define INT_DSP_MMU_ABORT 7
4942 +#define INT_HOST 8
4943 +#define INT_ABORT 9
4944 +#define INT_BRIDGE_PRIV 13
4945 +#define INT_GPIO_BANK1 14
4946 +#define INT_UART3 15
4947 +#define INT_TIMER3 16
4948 +#define INT_DMA_CH0_6 19
4949 +#define INT_DMA_CH1_7 20
4950 +#define INT_DMA_CH2_8 21
4951 +#define INT_DMA_CH3 22
4952 +#define INT_DMA_CH4 23
4953 +#define INT_DMA_CH5 24
4954 +#define INT_DMA_LCD 25
4955 +#define INT_TIMER1 26
4956 +#define INT_WD_TIMER 27
4957 +#define INT_BRIDGE_PUB 28
4958 +#define INT_TIMER2 30
4959 +#define INT_LCD_CTRL 31
4960 +
4961 +/*
4962 + * OMAP-1510 specific IRQ numbers for interrupt handler 1
4963 + */
4964 +#define INT_1510_IH2_IRQ 0
4965 +#define INT_1510_RES2 2
4966 +#define INT_1510_SPI_TX 4
4967 +#define INT_1510_SPI_RX 5
4968 +#define INT_1510_DSP_MAILBOX1 10
4969 +#define INT_1510_DSP_MAILBOX2 11
4970 +#define INT_1510_RES12 12
4971 +#define INT_1510_LB_MMU 17
4972 +#define INT_1510_RES18 18
4973 +#define INT_1510_LOCAL_BUS 29
4974 +
4975 +/*
4976 + * OMAP-1610 specific IRQ numbers for interrupt handler 1
4977 + */
4978 +#define INT_1610_IH2_IRQ 0
4979 +#define INT_1610_IH2_FIQ 2
4980 +#define INT_1610_McBSP2_TX 4
4981 +#define INT_1610_McBSP2_RX 5
4982 +#define INT_1610_DSP_MAILBOX1 10
4983 +#define INT_1610_DSP_MAILBOX2 11
4984 +#define INT_1610_LCD_LINE 12
4985 +#define INT_1610_GPTIMER1 17
4986 +#define INT_1610_GPTIMER2 18
4987 +#define INT_1610_SSR_FIFO_0 29
4988 +
4989 +/*
4990 + * OMAP-7xx specific IRQ numbers for interrupt handler 1
4991 + */
4992 +#define INT_7XX_IH2_FIQ 0
4993 +#define INT_7XX_IH2_IRQ 1
4994 +#define INT_7XX_USB_NON_ISO 2
4995 +#define INT_7XX_USB_ISO 3
4996 +#define INT_7XX_ICR 4
4997 +#define INT_7XX_EAC 5
4998 +#define INT_7XX_GPIO_BANK1 6
4999 +#define INT_7XX_GPIO_BANK2 7
5000 +#define INT_7XX_GPIO_BANK3 8
5001 +#define INT_7XX_McBSP2TX 10
5002 +#define INT_7XX_McBSP2RX 11
5003 +#define INT_7XX_McBSP2RX_OVF 12
5004 +#define INT_7XX_LCD_LINE 14
5005 +#define INT_7XX_GSM_PROTECT 15
5006 +#define INT_7XX_TIMER3 16
5007 +#define INT_7XX_GPIO_BANK5 17
5008 +#define INT_7XX_GPIO_BANK6 18
5009 +#define INT_7XX_SPGIO_WR 29
5010 +
5011 +/*
5012 + * IRQ numbers for interrupt handler 2
5013 + *
5014 + * NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below
5015 + */
5016 +#define IH2_BASE 32
5017 +
5018 +#define INT_KEYBOARD (1 + IH2_BASE)
5019 +#define INT_uWireTX (2 + IH2_BASE)
5020 +#define INT_uWireRX (3 + IH2_BASE)
5021 +#define INT_I2C (4 + IH2_BASE)
5022 +#define INT_MPUIO (5 + IH2_BASE)
5023 +#define INT_USB_HHC_1 (6 + IH2_BASE)
5024 +#define INT_McBSP3TX (10 + IH2_BASE)
5025 +#define INT_McBSP3RX (11 + IH2_BASE)
5026 +#define INT_McBSP1TX (12 + IH2_BASE)
5027 +#define INT_McBSP1RX (13 + IH2_BASE)
5028 +#define INT_UART1 (14 + IH2_BASE)
5029 +#define INT_UART2 (15 + IH2_BASE)
5030 +#define INT_BT_MCSI1TX (16 + IH2_BASE)
5031 +#define INT_BT_MCSI1RX (17 + IH2_BASE)
5032 +#define INT_SOSSI_MATCH (19 + IH2_BASE)
5033 +#define INT_USB_W2FC (20 + IH2_BASE)
5034 +#define INT_1WIRE (21 + IH2_BASE)
5035 +#define INT_OS_TIMER (22 + IH2_BASE)
5036 +#define INT_MMC (23 + IH2_BASE)
5037 +#define INT_GAUGE_32K (24 + IH2_BASE)
5038 +#define INT_RTC_TIMER (25 + IH2_BASE)
5039 +#define INT_RTC_ALARM (26 + IH2_BASE)
5040 +#define INT_MEM_STICK (27 + IH2_BASE)
5041 +
5042 +/*
5043 + * OMAP-1510 specific IRQ numbers for interrupt handler 2
5044 + */
5045 +#define INT_1510_DSP_MMU (28 + IH2_BASE)
5046 +#define INT_1510_COM_SPI_RO (31 + IH2_BASE)
5047 +
5048 +/*
5049 + * OMAP-1610 specific IRQ numbers for interrupt handler 2
5050 + */
5051 +#define INT_1610_FAC (0 + IH2_BASE)
5052 +#define INT_1610_USB_HHC_2 (7 + IH2_BASE)
5053 +#define INT_1610_USB_OTG (8 + IH2_BASE)
5054 +#define INT_1610_SoSSI (9 + IH2_BASE)
5055 +#define INT_1610_SoSSI_MATCH (19 + IH2_BASE)
5056 +#define INT_1610_DSP_MMU (28 + IH2_BASE)
5057 +#define INT_1610_McBSP2RX_OF (31 + IH2_BASE)
5058 +#define INT_1610_STI (32 + IH2_BASE)
5059 +#define INT_1610_STI_WAKEUP (33 + IH2_BASE)
5060 +#define INT_1610_GPTIMER3 (34 + IH2_BASE)
5061 +#define INT_1610_GPTIMER4 (35 + IH2_BASE)
5062 +#define INT_1610_GPTIMER5 (36 + IH2_BASE)
5063 +#define INT_1610_GPTIMER6 (37 + IH2_BASE)
5064 +#define INT_1610_GPTIMER7 (38 + IH2_BASE)
5065 +#define INT_1610_GPTIMER8 (39 + IH2_BASE)
5066 +#define INT_1610_GPIO_BANK2 (40 + IH2_BASE)
5067 +#define INT_1610_GPIO_BANK3 (41 + IH2_BASE)
5068 +#define INT_1610_MMC2 (42 + IH2_BASE)
5069 +#define INT_1610_CF (43 + IH2_BASE)
5070 +#define INT_1610_WAKE_UP_REQ (46 + IH2_BASE)
5071 +#define INT_1610_GPIO_BANK4 (48 + IH2_BASE)
5072 +#define INT_1610_SPI (49 + IH2_BASE)
5073 +#define INT_1610_DMA_CH6 (53 + IH2_BASE)
5074 +#define INT_1610_DMA_CH7 (54 + IH2_BASE)
5075 +#define INT_1610_DMA_CH8 (55 + IH2_BASE)
5076 +#define INT_1610_DMA_CH9 (56 + IH2_BASE)
5077 +#define INT_1610_DMA_CH10 (57 + IH2_BASE)
5078 +#define INT_1610_DMA_CH11 (58 + IH2_BASE)
5079 +#define INT_1610_DMA_CH12 (59 + IH2_BASE)
5080 +#define INT_1610_DMA_CH13 (60 + IH2_BASE)
5081 +#define INT_1610_DMA_CH14 (61 + IH2_BASE)
5082 +#define INT_1610_DMA_CH15 (62 + IH2_BASE)
5083 +#define INT_1610_NAND (63 + IH2_BASE)
5084 +#define INT_1610_SHA1MD5 (91 + IH2_BASE)
5085 +
5086 +/*
5087 + * OMAP-7xx specific IRQ numbers for interrupt handler 2
5088 + */
5089 +#define INT_7XX_HW_ERRORS (0 + IH2_BASE)
5090 +#define INT_7XX_NFIQ_PWR_FAIL (1 + IH2_BASE)
5091 +#define INT_7XX_CFCD (2 + IH2_BASE)
5092 +#define INT_7XX_CFIREQ (3 + IH2_BASE)
5093 +#define INT_7XX_I2C (4 + IH2_BASE)
5094 +#define INT_7XX_PCC (5 + IH2_BASE)
5095 +#define INT_7XX_MPU_EXT_NIRQ (6 + IH2_BASE)
5096 +#define INT_7XX_SPI_100K_1 (7 + IH2_BASE)
5097 +#define INT_7XX_SYREN_SPI (8 + IH2_BASE)
5098 +#define INT_7XX_VLYNQ (9 + IH2_BASE)
5099 +#define INT_7XX_GPIO_BANK4 (10 + IH2_BASE)
5100 +#define INT_7XX_McBSP1TX (11 + IH2_BASE)
5101 +#define INT_7XX_McBSP1RX (12 + IH2_BASE)
5102 +#define INT_7XX_McBSP1RX_OF (13 + IH2_BASE)
5103 +#define INT_7XX_UART_MODEM_IRDA_2 (14 + IH2_BASE)
5104 +#define INT_7XX_UART_MODEM_1 (15 + IH2_BASE)
5105 +#define INT_7XX_MCSI (16 + IH2_BASE)
5106 +#define INT_7XX_uWireTX (17 + IH2_BASE)
5107 +#define INT_7XX_uWireRX (18 + IH2_BASE)
5108 +#define INT_7XX_SMC_CD (19 + IH2_BASE)
5109 +#define INT_7XX_SMC_IREQ (20 + IH2_BASE)
5110 +#define INT_7XX_HDQ_1WIRE (21 + IH2_BASE)
5111 +#define INT_7XX_TIMER32K (22 + IH2_BASE)
5112 +#define INT_7XX_MMC_SDIO (23 + IH2_BASE)
5113 +#define INT_7XX_UPLD (24 + IH2_BASE)
5114 +#define INT_7XX_USB_HHC_1 (27 + IH2_BASE)
5115 +#define INT_7XX_USB_HHC_2 (28 + IH2_BASE)
5116 +#define INT_7XX_USB_GENI (29 + IH2_BASE)
5117 +#define INT_7XX_USB_OTG (30 + IH2_BASE)
5118 +#define INT_7XX_CAMERA_IF (31 + IH2_BASE)
5119 +#define INT_7XX_RNG (32 + IH2_BASE)
5120 +#define INT_7XX_DUAL_MODE_TIMER (33 + IH2_BASE)
5121 +#define INT_7XX_DBB_RF_EN (34 + IH2_BASE)
5122 +#define INT_7XX_MPUIO_KEYPAD (35 + IH2_BASE)
5123 +#define INT_7XX_SHA1_MD5 (36 + IH2_BASE)
5124 +#define INT_7XX_SPI_100K_2 (37 + IH2_BASE)
5125 +#define INT_7XX_RNG_IDLE (38 + IH2_BASE)
5126 +#define INT_7XX_MPUIO (39 + IH2_BASE)
5127 +#define INT_7XX_LLPC_LCD_CTRL_CAN_BE_OFF (40 + IH2_BASE)
5128 +#define INT_7XX_LLPC_OE_FALLING (41 + IH2_BASE)
5129 +#define INT_7XX_LLPC_OE_RISING (42 + IH2_BASE)
5130 +#define INT_7XX_LLPC_VSYNC (43 + IH2_BASE)
5131 +#define INT_7XX_WAKE_UP_REQ (46 + IH2_BASE)
5132 +#define INT_7XX_DMA_CH6 (53 + IH2_BASE)
5133 +#define INT_7XX_DMA_CH7 (54 + IH2_BASE)
5134 +#define INT_7XX_DMA_CH8 (55 + IH2_BASE)
5135 +#define INT_7XX_DMA_CH9 (56 + IH2_BASE)
5136 +#define INT_7XX_DMA_CH10 (57 + IH2_BASE)
5137 +#define INT_7XX_DMA_CH11 (58 + IH2_BASE)
5138 +#define INT_7XX_DMA_CH12 (59 + IH2_BASE)
5139 +#define INT_7XX_DMA_CH13 (60 + IH2_BASE)
5140 +#define INT_7XX_DMA_CH14 (61 + IH2_BASE)
5141 +#define INT_7XX_DMA_CH15 (62 + IH2_BASE)
5142 +#define INT_7XX_NAND (63 + IH2_BASE)
5143 +
5144 +#define INT_24XX_SYS_NIRQ 7
5145 +#define INT_24XX_SDMA_IRQ0 12
5146 +#define INT_24XX_SDMA_IRQ1 13
5147 +#define INT_24XX_SDMA_IRQ2 14
5148 +#define INT_24XX_SDMA_IRQ3 15
5149 +#define INT_24XX_CAM_IRQ 24
5150 +#define INT_24XX_DSS_IRQ 25
5151 +#define INT_24XX_MAIL_U0_MPU 26
5152 +#define INT_24XX_DSP_UMA 27
5153 +#define INT_24XX_DSP_MMU 28
5154 +#define INT_24XX_GPIO_BANK1 29
5155 +#define INT_24XX_GPIO_BANK2 30
5156 +#define INT_24XX_GPIO_BANK3 31
5157 +#define INT_24XX_GPIO_BANK4 32
5158 +#define INT_24XX_GPIO_BANK5 33
5159 +#define INT_24XX_MAIL_U3_MPU 34
5160 +#define INT_24XX_GPTIMER1 37
5161 +#define INT_24XX_GPTIMER2 38
5162 +#define INT_24XX_GPTIMER3 39
5163 +#define INT_24XX_GPTIMER4 40
5164 +#define INT_24XX_GPTIMER5 41
5165 +#define INT_24XX_GPTIMER6 42
5166 +#define INT_24XX_GPTIMER7 43
5167 +#define INT_24XX_GPTIMER8 44
5168 +#define INT_24XX_GPTIMER9 45
5169 +#define INT_24XX_GPTIMER10 46
5170 +#define INT_24XX_GPTIMER11 47
5171 +#define INT_24XX_GPTIMER12 48
5172 +#define INT_24XX_SHA1MD5 51
5173 +#define INT_24XX_MCBSP4_IRQ_TX 54
5174 +#define INT_24XX_MCBSP4_IRQ_RX 55
5175 +#define INT_24XX_I2C1_IRQ 56
5176 +#define INT_24XX_I2C2_IRQ 57
5177 +#define INT_24XX_HDQ_IRQ 58
5178 +#define INT_24XX_MCBSP1_IRQ_TX 59
5179 +#define INT_24XX_MCBSP1_IRQ_RX 60
5180 +#define INT_24XX_MCBSP2_IRQ_TX 62
5181 +#define INT_24XX_MCBSP2_IRQ_RX 63
5182 +#define INT_24XX_SPI1_IRQ 65
5183 +#define INT_24XX_SPI2_IRQ 66
5184 +#define INT_24XX_UART1_IRQ 72
5185 +#define INT_24XX_UART2_IRQ 73
5186 +#define INT_24XX_UART3_IRQ 74
5187 +#define INT_24XX_USB_IRQ_GEN 75
5188 +#define INT_24XX_USB_IRQ_NISO 76
5189 +#define INT_24XX_USB_IRQ_ISO 77
5190 +#define INT_24XX_USB_IRQ_HGEN 78
5191 +#define INT_24XX_USB_IRQ_HSOF 79
5192 +#define INT_24XX_USB_IRQ_OTG 80
5193 +#define INT_24XX_MCBSP5_IRQ_TX 81
5194 +#define INT_24XX_MCBSP5_IRQ_RX 82
5195 +#define INT_24XX_MMC_IRQ 83
5196 +#define INT_24XX_MMC2_IRQ 86
5197 +#define INT_24XX_MCBSP3_IRQ_TX 89
5198 +#define INT_24XX_MCBSP3_IRQ_RX 90
5199 +#define INT_24XX_SPI3_IRQ 91
5200 +
5201 +#define INT_243X_MCBSP2_IRQ 16
5202 +#define INT_243X_MCBSP3_IRQ 17
5203 +#define INT_243X_MCBSP4_IRQ 18
5204 +#define INT_243X_MCBSP5_IRQ 19
5205 +#define INT_243X_MCBSP1_IRQ 64
5206 +#define INT_243X_HS_USB_MC 92
5207 +#define INT_243X_HS_USB_DMA 93
5208 +#define INT_243X_CARKIT_IRQ 94
5209 +
5210 +#define INT_34XX_BENCH_MPU_EMUL 3
5211 +#define INT_34XX_ST_MCBSP2_IRQ 4
5212 +#define INT_34XX_ST_MCBSP3_IRQ 5
5213 +#define INT_34XX_SSM_ABORT_IRQ 6
5214 +#define INT_34XX_SYS_NIRQ 7
5215 +#define INT_34XX_D2D_FW_IRQ 8
5216 +#define INT_34XX_PRCM_MPU_IRQ 11
5217 +#define INT_34XX_MCBSP1_IRQ 16
5218 +#define INT_34XX_MCBSP2_IRQ 17
5219 +#define INT_34XX_MCBSP3_IRQ 22
5220 +#define INT_34XX_MCBSP4_IRQ 23
5221 +#define INT_34XX_CAM_IRQ 24
5222 +#define INT_34XX_MCBSP5_IRQ 27
5223 +#define INT_34XX_GPIO_BANK1 29
5224 +#define INT_34XX_GPIO_BANK2 30
5225 +#define INT_34XX_GPIO_BANK3 31
5226 +#define INT_34XX_GPIO_BANK4 32
5227 +#define INT_34XX_GPIO_BANK5 33
5228 +#define INT_34XX_GPIO_BANK6 34
5229 +#define INT_34XX_USIM_IRQ 35
5230 +#define INT_34XX_WDT3_IRQ 36
5231 +#define INT_34XX_SPI4_IRQ 48
5232 +#define INT_34XX_SHA1MD52_IRQ 49
5233 +#define INT_34XX_FPKA_READY_IRQ 50
5234 +#define INT_34XX_SHA1MD51_IRQ 51
5235 +#define INT_34XX_RNG_IRQ 52
5236 +#define INT_34XX_I2C3_IRQ 61
5237 +#define INT_34XX_FPKA_ERROR_IRQ 64
5238 +#define INT_34XX_PBIAS_IRQ 75
5239 +#define INT_34XX_OHCI_IRQ 76
5240 +#define INT_34XX_EHCI_IRQ 77
5241 +#define INT_34XX_TLL_IRQ 78
5242 +#define INT_34XX_PARTHASH_IRQ 79
5243 +#define INT_34XX_MMC3_IRQ 94
5244 +#define INT_34XX_GPT12_IRQ 95
5245 +
5246 +#define INT_34XX_BENCH_MPU_EMUL 3
5247 +
5248 +
5249 +#define IRQ_GIC_START 32
5250 +#define INT_44XX_LOCALTIMER_IRQ 29
5251 +#define INT_44XX_LOCALWDT_IRQ 30
5252 +
5253 +#define INT_44XX_BENCH_MPU_EMUL (3 + IRQ_GIC_START)
5254 +#define INT_44XX_SSM_ABORT_IRQ (6 + IRQ_GIC_START)
5255 +#define INT_44XX_SYS_NIRQ (7 + IRQ_GIC_START)
5256 +#define INT_44XX_D2D_FW_IRQ (8 + IRQ_GIC_START)
5257 +#define INT_44XX_PRCM_MPU_IRQ (11 + IRQ_GIC_START)
5258 +#define INT_44XX_SDMA_IRQ0 (12 + IRQ_GIC_START)
5259 +#define INT_44XX_SDMA_IRQ1 (13 + IRQ_GIC_START)
5260 +#define INT_44XX_SDMA_IRQ2 (14 + IRQ_GIC_START)
5261 +#define INT_44XX_SDMA_IRQ3 (15 + IRQ_GIC_START)
5262 +#define INT_44XX_ISS_IRQ (24 + IRQ_GIC_START)
5263 +#define INT_44XX_DSS_IRQ (25 + IRQ_GIC_START)
5264 +#define INT_44XX_MAIL_U0_MPU (26 + IRQ_GIC_START)
5265 +#define INT_44XX_DSP_MMU (28 + IRQ_GIC_START)
5266 +#define INT_44XX_GPTIMER1 (37 + IRQ_GIC_START)
5267 +#define INT_44XX_GPTIMER2 (38 + IRQ_GIC_START)
5268 +#define INT_44XX_GPTIMER3 (39 + IRQ_GIC_START)
5269 +#define INT_44XX_GPTIMER4 (40 + IRQ_GIC_START)
5270 +#define INT_44XX_GPTIMER5 (41 + IRQ_GIC_START)
5271 +#define INT_44XX_GPTIMER6 (42 + IRQ_GIC_START)
5272 +#define INT_44XX_GPTIMER7 (43 + IRQ_GIC_START)
5273 +#define INT_44XX_GPTIMER8 (44 + IRQ_GIC_START)
5274 +#define INT_44XX_GPTIMER9 (45 + IRQ_GIC_START)
5275 +#define INT_44XX_GPTIMER10 (46 + IRQ_GIC_START)
5276 +#define INT_44XX_GPTIMER11 (47 + IRQ_GIC_START)
5277 +#define INT_44XX_GPTIMER12 (95 + IRQ_GIC_START)
5278 +#define INT_44XX_SHA1MD5 (51 + IRQ_GIC_START)
5279 +#define INT_44XX_I2C1_IRQ (56 + IRQ_GIC_START)
5280 +#define INT_44XX_I2C2_IRQ (57 + IRQ_GIC_START)
5281 +#define INT_44XX_HDQ_IRQ (58 + IRQ_GIC_START)
5282 +#define INT_44XX_SPI1_IRQ (65 + IRQ_GIC_START)
5283 +#define INT_44XX_SPI2_IRQ (66 + IRQ_GIC_START)
5284 +#define INT_44XX_HSI_1_IRQ0 (67 + IRQ_GIC_START)
5285 +#define INT_44XX_HSI_2_IRQ1 (68 + IRQ_GIC_START)
5286 +#define INT_44XX_HSI_1_DMAIRQ (71 + IRQ_GIC_START)
5287 +#define INT_44XX_UART1_IRQ (72 + IRQ_GIC_START)
5288 +#define INT_44XX_UART2_IRQ (73 + IRQ_GIC_START)
5289 +#define INT_44XX_UART3_IRQ (74 + IRQ_GIC_START)
5290 +#define INT_44XX_UART4_IRQ (70 + IRQ_GIC_START)
5291 +#define INT_44XX_USB_IRQ_NISO (76 + IRQ_GIC_START)
5292 +#define INT_44XX_USB_IRQ_ISO (77 + IRQ_GIC_START)
5293 +#define INT_44XX_USB_IRQ_HGEN (78 + IRQ_GIC_START)
5294 +#define INT_44XX_USB_IRQ_HSOF (79 + IRQ_GIC_START)
5295 +#define INT_44XX_USB_IRQ_OTG (80 + IRQ_GIC_START)
5296 +#define INT_44XX_MCBSP4_IRQ_TX (81 + IRQ_GIC_START)
5297 +#define INT_44XX_MCBSP4_IRQ_RX (82 + IRQ_GIC_START)
5298 +#define INT_44XX_MMC_IRQ (83 + IRQ_GIC_START)
5299 +#define INT_44XX_MMC2_IRQ (86 + IRQ_GIC_START)
5300 +#define INT_44XX_MCBSP2_IRQ_TX (89 + IRQ_GIC_START)
5301 +#define INT_44XX_MCBSP2_IRQ_RX (90 + IRQ_GIC_START)
5302 +#define INT_44XX_SPI3_IRQ (91 + IRQ_GIC_START)
5303 +#define INT_44XX_SPI5_IRQ (69 + IRQ_GIC_START)
5304 +
5305 +#define INT_44XX_MCBSP5_IRQ (16 + IRQ_GIC_START)
5306 +#define INT_44xX_MCBSP1_IRQ (17 + IRQ_GIC_START)
5307 +#define INT_44XX_MCBSP2_IRQ (22 + IRQ_GIC_START)
5308 +#define INT_44XX_MCBSP3_IRQ (23 + IRQ_GIC_START)
5309 +#define INT_44XX_MCBSP4_IRQ (27 + IRQ_GIC_START)
5310 +#define INT_44XX_HS_USB_MC (92 + IRQ_GIC_START)
5311 +#define INT_44XX_HS_USB_DMA (93 + IRQ_GIC_START)
5312 +
5313 +#define INT_44XX_GPIO_BANK1 (29 + IRQ_GIC_START)
5314 +#define INT_44XX_GPIO_BANK2 (30 + IRQ_GIC_START)
5315 +#define INT_44XX_GPIO_BANK3 (31 + IRQ_GIC_START)
5316 +#define INT_44XX_GPIO_BANK4 (32 + IRQ_GIC_START)
5317 +#define INT_44XX_GPIO_BANK5 (33 + IRQ_GIC_START)
5318 +#define INT_44XX_GPIO_BANK6 (34 + IRQ_GIC_START)
5319 +#define INT_44XX_USIM_IRQ (35 + IRQ_GIC_START)
5320 +#define INT_44XX_WDT3_IRQ (36 + IRQ_GIC_START)
5321 +#define INT_44XX_SPI4_IRQ (48 + IRQ_GIC_START)
5322 +#define INT_44XX_SHA1MD52_IRQ (49 + IRQ_GIC_START)
5323 +#define INT_44XX_FPKA_READY_IRQ (50 + IRQ_GIC_START)
5324 +#define INT_44XX_SHA1MD51_IRQ (51 + IRQ_GIC_START)
5325 +#define INT_44XX_RNG_IRQ (52 + IRQ_GIC_START)
5326 +#define INT_44XX_MMC5_IRQ (59 + IRQ_GIC_START)
5327 +#define INT_44XX_I2C3_IRQ (61 + IRQ_GIC_START)
5328 +#define INT_44XX_FPKA_ERROR_IRQ (64 + IRQ_GIC_START)
5329 +#define INT_44XX_PBIAS_IRQ (75 + IRQ_GIC_START)
5330 +#define INT_44XX_OHCI_IRQ (76 + IRQ_GIC_START)
5331 +#define INT_44XX_EHCI_IRQ (77 + IRQ_GIC_START)
5332 +#define INT_44XX_TLL_IRQ (78 + IRQ_GIC_START)
5333 +#define INT_44XX_PARTHASH_IRQ (79 + IRQ_GIC_START)
5334 +#define INT_44XX_MMC3_IRQ (94 + IRQ_GIC_START)
5335 +#define INT_44XX_MMC4_IRQ (96 + IRQ_GIC_START)
5336 +
5337 +
5338 +/* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730/850) and
5339 + * 16 MPUIO lines */
5340 +#define OMAP_MAX_GPIO_LINES 192
5341 +#define IH_GPIO_BASE (128 + IH2_BASE)
5342 +#define IH_MPUIO_BASE (OMAP_MAX_GPIO_LINES + IH_GPIO_BASE)
5343 +#define OMAP_IRQ_END (IH_MPUIO_BASE + 16)
5344 +
5345 +/* External FPGA handles interrupts on Innovator boards */
5346 +#define OMAP_FPGA_IRQ_BASE (OMAP_IRQ_END)
5347 +#ifdef CONFIG_MACH_OMAP_INNOVATOR
5348 +#define OMAP_FPGA_NR_IRQS 24
5349 +#else
5350 +#define OMAP_FPGA_NR_IRQS 0
5351 +#endif
5352 +#define OMAP_FPGA_IRQ_END (OMAP_FPGA_IRQ_BASE + OMAP_FPGA_NR_IRQS)
5353 +
5354 +/* External TWL4030 can handle interrupts on 2430 and 34xx boards */
5355 +#define TWL4030_IRQ_BASE (OMAP_FPGA_IRQ_END)
5356 +#ifdef CONFIG_TWL4030_CORE
5357 +#define TWL4030_BASE_NR_IRQS 8
5358 +#define TWL4030_PWR_NR_IRQS 8
5359 +#else
5360 +#define TWL4030_BASE_NR_IRQS 0
5361 +#define TWL4030_PWR_NR_IRQS 0
5362 +#endif
5363 +#define TWL4030_IRQ_END (TWL4030_IRQ_BASE + TWL4030_BASE_NR_IRQS)
5364 +#define TWL4030_PWR_IRQ_BASE TWL4030_IRQ_END
5365 +#define TWL4030_PWR_IRQ_END (TWL4030_PWR_IRQ_BASE + TWL4030_PWR_NR_IRQS)
5366 +
5367 +/* External TWL4030 gpio interrupts are optional */
5368 +#define TWL4030_GPIO_IRQ_BASE TWL4030_PWR_IRQ_END
5369 +#ifdef CONFIG_GPIO_TWL4030
5370 +#define TWL4030_GPIO_NR_IRQS 18
5371 +#else
5372 +#define TWL4030_GPIO_NR_IRQS 0
5373 +#endif
5374 +#define TWL4030_GPIO_IRQ_END (TWL4030_GPIO_IRQ_BASE + TWL4030_GPIO_NR_IRQS)
5375 +
5376 +#define TWL6030_IRQ_BASE (OMAP_FPGA_IRQ_END)
5377 +#ifdef CONFIG_TWL4030_CORE
5378 +#define TWL6030_BASE_NR_IRQS 20
5379 +#else
5380 +#define TWL6030_BASE_NR_IRQS 0
5381 +#endif
5382 +#define TWL6030_IRQ_END (TWL6030_IRQ_BASE + TWL6030_BASE_NR_IRQS)
5383 +
5384 +/* Total number of interrupts depends on the enabled blocks above */
5385 +#if (TWL4030_GPIO_IRQ_END > TWL6030_IRQ_END)
5386 +#define TWL_IRQ_END TWL4030_GPIO_IRQ_END
5387 +#else
5388 +#define TWL_IRQ_END TWL6030_IRQ_END
5389 +#endif
5390 +
5391 +#define NR_IRQS TWL_IRQ_END
5392 +
5393 +#define OMAP_IRQ_BIT(irq) (1 << ((irq) % 32))
5394 +
5395 +#define INTCPS_NR_MIR_REGS 3
5396 +#define INTCPS_NR_IRQS 96
5397 +
5398 +#ifndef __ASSEMBLY__
5399 +extern void omap_init_irq(void);
5400 +extern int omap_irq_pending(void);
5401 +void omap_intc_save_context(void);
5402 +void omap_intc_restore_context(void);
5403 +#endif
5404 +
5405 +#include <mach/hardware.h>
5406 +
5407 +#endif
5408 Index: linux-2.6.35/arch/arm/plat-omap/include/mach/keypad.h
5409 ===================================================================
5410 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
5411 +++ linux-2.6.35/arch/arm/plat-omap/include/mach/keypad.h 2010-08-08 12:56:58.000000000 +0200
5412 @@ -0,0 +1,45 @@
5413 +/*
5414 + * arch/arm/plat-omap/include/mach/keypad.h
5415 + *
5416 + * Copyright (C) 2006 Komal Shah <komal_shah802003@yahoo.com>
5417 + *
5418 + * This program is free software; you can redistribute it and/or modify
5419 + * it under the terms of the GNU General Public License version 2 as
5420 + * published by the Free Software Foundation.
5421 + */
5422 +#ifndef ASMARM_ARCH_KEYPAD_H
5423 +#define ASMARM_ARCH_KEYPAD_H
5424 +
5425 +#warning: Please update the board to use matrix_keypad.h instead
5426 +
5427 +struct omap_kp_platform_data {
5428 + int rows;
5429 + int cols;
5430 + int *keymap;
5431 + unsigned int keymapsize;
5432 + unsigned int rep:1;
5433 + unsigned long delay;
5434 + unsigned int dbounce:1;
5435 + /* specific to OMAP242x*/
5436 + unsigned int *row_gpios;
5437 + unsigned int *col_gpios;
5438 +};
5439 +
5440 +/* Group (0..3) -- when multiple keys are pressed, only the
5441 + * keys pressed in the same group are considered as pressed. This is
5442 + * in order to workaround certain crappy HW designs that produce ghost
5443 + * keypresses. */
5444 +#define GROUP_0 (0 << 16)
5445 +#define GROUP_1 (1 << 16)
5446 +#define GROUP_2 (2 << 16)
5447 +#define GROUP_3 (3 << 16)
5448 +#define GROUP_MASK GROUP_3
5449 +
5450 +#define KEY_PERSISTENT 0x00800000
5451 +#define KEYNUM_MASK 0x00EFFFFF
5452 +#define KEY(col, row, val) (((col) << 28) | ((row) << 24) | (val))
5453 +#define PERSISTENT_KEY(col, row) (((col) << 28) | ((row) << 24) | \
5454 + KEY_PERSISTENT)
5455 +
5456 +#endif
5457 +
5458 Index: linux-2.6.35/arch/arm/plat-omap/include/mach/lcd_mipid.h
5459 ===================================================================
5460 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
5461 +++ linux-2.6.35/arch/arm/plat-omap/include/mach/lcd_mipid.h 2010-08-08 12:56:59.000000000 +0200
5462 @@ -0,0 +1,29 @@
5463 +#ifndef __LCD_MIPID_H
5464 +#define __LCD_MIPID_H
5465 +
5466 +enum mipid_test_num {
5467 + MIPID_TEST_RGB_LINES,
5468 +};
5469 +
5470 +enum mipid_test_result {
5471 + MIPID_TEST_SUCCESS,
5472 + MIPID_TEST_INVALID,
5473 + MIPID_TEST_FAILED,
5474 +};
5475 +
5476 +#ifdef __KERNEL__
5477 +
5478 +struct mipid_platform_data {
5479 + int nreset_gpio;
5480 + int data_lines;
5481 +
5482 + void (*shutdown)(struct mipid_platform_data *pdata);
5483 + void (*set_bklight_level)(struct mipid_platform_data *pdata,
5484 + int level);
5485 + int (*get_bklight_level)(struct mipid_platform_data *pdata);
5486 + int (*get_bklight_max)(struct mipid_platform_data *pdata);
5487 +};
5488 +
5489 +#endif
5490 +
5491 +#endif
5492 Index: linux-2.6.35/arch/arm/plat-omap/include/mach/led.h
5493 ===================================================================
5494 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
5495 +++ linux-2.6.35/arch/arm/plat-omap/include/mach/led.h 2010-08-08 12:56:59.000000000 +0200
5496 @@ -0,0 +1,24 @@
5497 +/*
5498 + * arch/arm/plat-omap/include/mach/led.h
5499 + *
5500 + * Copyright (C) 2006 Samsung Electronics
5501 + * Kyungmin Park <kyungmin.park@samsung.com>
5502 + *
5503 + * This program is free software; you can redistribute it and/or modify
5504 + * it under the terms of the GNU General Public License version 2 as
5505 + * published by the Free Software Foundation.
5506 + */
5507 +#ifndef ASMARM_ARCH_LED_H
5508 +#define ASMARM_ARCH_LED_H
5509 +
5510 +struct omap_led_config {
5511 + struct led_classdev cdev;
5512 + s16 gpio;
5513 +};
5514 +
5515 +struct omap_led_platform_data {
5516 + s16 nr_leds;
5517 + struct omap_led_config *leds;
5518 +};
5519 +
5520 +#endif
5521 Index: linux-2.6.35/arch/arm/plat-omap/include/mach/mailbox.h
5522 ===================================================================
5523 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
5524 +++ linux-2.6.35/arch/arm/plat-omap/include/mach/mailbox.h 2010-08-08 12:57:00.000000000 +0200
5525 @@ -0,0 +1,111 @@
5526 +/* mailbox.h */
5527 +
5528 +#ifndef MAILBOX_H
5529 +#define MAILBOX_H
5530 +
5531 +#include <linux/wait.h>
5532 +#include <linux/workqueue.h>
5533 +#include <linux/blkdev.h>
5534 +#include <linux/interrupt.h>
5535 +
5536 +typedef u32 mbox_msg_t;
5537 +struct omap_mbox;
5538 +
5539 +typedef int __bitwise omap_mbox_irq_t;
5540 +#define IRQ_TX ((__force omap_mbox_irq_t) 1)
5541 +#define IRQ_RX ((__force omap_mbox_irq_t) 2)
5542 +
5543 +typedef int __bitwise omap_mbox_type_t;
5544 +#define OMAP_MBOX_TYPE1 ((__force omap_mbox_type_t) 1)
5545 +#define OMAP_MBOX_TYPE2 ((__force omap_mbox_type_t) 2)
5546 +
5547 +struct omap_mbox_ops {
5548 + omap_mbox_type_t type;
5549 + int (*startup)(struct omap_mbox *mbox);
5550 + void (*shutdown)(struct omap_mbox *mbox);
5551 + /* fifo */
5552 + mbox_msg_t (*fifo_read)(struct omap_mbox *mbox);
5553 + void (*fifo_write)(struct omap_mbox *mbox, mbox_msg_t msg);
5554 + int (*fifo_empty)(struct omap_mbox *mbox);
5555 + int (*fifo_full)(struct omap_mbox *mbox);
5556 + /* irq */
5557 + void (*enable_irq)(struct omap_mbox *mbox,
5558 + omap_mbox_irq_t irq);
5559 + void (*disable_irq)(struct omap_mbox *mbox,
5560 + omap_mbox_irq_t irq);
5561 + void (*ack_irq)(struct omap_mbox *mbox, omap_mbox_irq_t irq);
5562 + int (*is_irq)(struct omap_mbox *mbox, omap_mbox_irq_t irq);
5563 + /* ctx */
5564 + void (*save_ctx)(struct omap_mbox *mbox);
5565 + void (*restore_ctx)(struct omap_mbox *mbox);
5566 +};
5567 +
5568 +struct omap_mbox_queue {
5569 + spinlock_t lock;
5570 + struct request_queue *queue;
5571 + struct work_struct work;
5572 + struct tasklet_struct tasklet;
5573 + int (*callback)(void *);
5574 + struct omap_mbox *mbox;
5575 +};
5576 +
5577 +struct omap_mbox {
5578 + char *name;
5579 + unsigned int irq;
5580 +
5581 + struct omap_mbox_queue *txq, *rxq;
5582 +
5583 + struct omap_mbox_ops *ops;
5584 +
5585 + mbox_msg_t seq_snd, seq_rcv;
5586 +
5587 + struct device *dev;
5588 +
5589 + struct omap_mbox *next;
5590 + void *priv;
5591 +
5592 + void (*err_notify)(void);
5593 +};
5594 +
5595 +int omap_mbox_msg_send(struct omap_mbox *, mbox_msg_t msg);
5596 +void omap_mbox_init_seq(struct omap_mbox *);
5597 +
5598 +struct omap_mbox *omap_mbox_get(const char *);
5599 +void omap_mbox_put(struct omap_mbox *);
5600 +
5601 +int omap_mbox_register(struct device *parent, struct omap_mbox *);
5602 +int omap_mbox_unregister(struct omap_mbox *);
5603 +
5604 +static inline void omap_mbox_save_ctx(struct omap_mbox *mbox)
5605 +{
5606 + if (!mbox->ops->save_ctx) {
5607 + dev_err(mbox->dev, "%s:\tno save\n", __func__);
5608 + return;
5609 + }
5610 +
5611 + mbox->ops->save_ctx(mbox);
5612 +}
5613 +
5614 +static inline void omap_mbox_restore_ctx(struct omap_mbox *mbox)
5615 +{
5616 + if (!mbox->ops->restore_ctx) {
5617 + dev_err(mbox->dev, "%s:\tno restore\n", __func__);
5618 + return;
5619 + }
5620 +
5621 + mbox->ops->restore_ctx(mbox);
5622 +}
5623 +
5624 +static inline void omap_mbox_enable_irq(struct omap_mbox *mbox,
5625 + omap_mbox_irq_t irq)
5626 +{
5627 + mbox->ops->enable_irq(mbox, irq);
5628 +}
5629 +
5630 +static inline void omap_mbox_disable_irq(struct omap_mbox *mbox,
5631 + omap_mbox_irq_t irq)
5632 +{
5633 + mbox->ops->disable_irq(mbox, irq);
5634 +}
5635 +
5636 +#endif /* MAILBOX_H */
5637 Index: linux-2.6.35/arch/arm/plat-omap/include/mach/mcbsp.h
5638 ===================================================================
5639 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
5640 +++ linux-2.6.35/arch/arm/plat-omap/include/mach/mcbsp.h 2010-08-08 12:57:01.000000000 +0200
5641 @@ -0,0 +1,462 @@
5642 +/*
5643 + * arch/arm/plat-omap/include/mach/mcbsp.h
5644 + *
5645 + * Defines for Multi-Channel Buffered Serial Port
5646 + *
5647 + * Copyright (C) 2002 RidgeRun, Inc.
5648 + * Author: Steve Johnson
5649 + *
5650 + * This program is free software; you can redistribute it and/or modify
5651 + * it under the terms of the GNU General Public License as published by
5652 + * the Free Software Foundation; either version 2 of the License, or
5653 + * (at your option) any later version.
5654 + *
5655 + * This program is distributed in the hope that it will be useful,
5656 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
5657 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
5658 + * GNU General Public License for more details.
5659 + *
5660 + * You should have received a copy of the GNU General Public License
5661 + * along with this program; if not, write to the Free Software
5662 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
5663 + *
5664 + */
5665 +#ifndef __ASM_ARCH_OMAP_MCBSP_H
5666 +#define __ASM_ARCH_OMAP_MCBSP_H
5667 +
5668 +#include <linux/completion.h>
5669 +#include <linux/spinlock.h>
5670 +
5671 +#include <mach/hardware.h>
5672 +#include <plat/clock.h>
5673 +
5674 +#define OMAP7XX_MCBSP1_BASE 0xfffb1000
5675 +#define OMAP7XX_MCBSP2_BASE 0xfffb1800
5676 +
5677 +#define OMAP1510_MCBSP1_BASE 0xe1011800
5678 +#define OMAP1510_MCBSP2_BASE 0xfffb1000
5679 +#define OMAP1510_MCBSP3_BASE 0xe1017000
5680 +
5681 +#define OMAP1610_MCBSP1_BASE 0xe1011800
5682 +#define OMAP1610_MCBSP2_BASE 0xfffb1000
5683 +#define OMAP1610_MCBSP3_BASE 0xe1017000
5684 +
5685 +#define OMAP24XX_MCBSP1_BASE 0x48074000
5686 +#define OMAP24XX_MCBSP2_BASE 0x48076000
5687 +#define OMAP2430_MCBSP3_BASE 0x4808c000
5688 +#define OMAP2430_MCBSP4_BASE 0x4808e000
5689 +#define OMAP2430_MCBSP5_BASE 0x48096000
5690 +
5691 +#define OMAP34XX_MCBSP1_BASE 0x48074000
5692 +#define OMAP34XX_MCBSP2_BASE 0x49022000
5693 +#define OMAP34XX_MCBSP3_BASE 0x49024000
5694 +#define OMAP34XX_MCBSP4_BASE 0x49026000
5695 +#define OMAP34XX_MCBSP5_BASE 0x48096000
5696 +
5697 +#define OMAP44XX_MCBSP1_BASE 0x49022000
5698 +#define OMAP44XX_MCBSP2_BASE 0x49024000
5699 +#define OMAP44XX_MCBSP3_BASE 0x49026000
5700 +#define OMAP44XX_MCBSP4_BASE 0x48074000
5701 +
5702 +#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
5703 +
5704 +#define OMAP_MCBSP_REG_DRR2 0x00
5705 +#define OMAP_MCBSP_REG_DRR1 0x02
5706 +#define OMAP_MCBSP_REG_DXR2 0x04
5707 +#define OMAP_MCBSP_REG_DXR1 0x06
5708 +#define OMAP_MCBSP_REG_SPCR2 0x08
5709 +#define OMAP_MCBSP_REG_SPCR1 0x0a
5710 +#define OMAP_MCBSP_REG_RCR2 0x0c
5711 +#define OMAP_MCBSP_REG_RCR1 0x0e
5712 +#define OMAP_MCBSP_REG_XCR2 0x10
5713 +#define OMAP_MCBSP_REG_XCR1 0x12
5714 +#define OMAP_MCBSP_REG_SRGR2 0x14
5715 +#define OMAP_MCBSP_REG_SRGR1 0x16
5716 +#define OMAP_MCBSP_REG_MCR2 0x18
5717 +#define OMAP_MCBSP_REG_MCR1 0x1a
5718 +#define OMAP_MCBSP_REG_RCERA 0x1c
5719 +#define OMAP_MCBSP_REG_RCERB 0x1e
5720 +#define OMAP_MCBSP_REG_XCERA 0x20
5721 +#define OMAP_MCBSP_REG_XCERB 0x22
5722 +#define OMAP_MCBSP_REG_PCR0 0x24
5723 +#define OMAP_MCBSP_REG_RCERC 0x26
5724 +#define OMAP_MCBSP_REG_RCERD 0x28
5725 +#define OMAP_MCBSP_REG_XCERC 0x2A
5726 +#define OMAP_MCBSP_REG_XCERD 0x2C
5727 +#define OMAP_MCBSP_REG_RCERE 0x2E
5728 +#define OMAP_MCBSP_REG_RCERF 0x30
5729 +#define OMAP_MCBSP_REG_XCERE 0x32
5730 +#define OMAP_MCBSP_REG_XCERF 0x34
5731 +#define OMAP_MCBSP_REG_RCERG 0x36
5732 +#define OMAP_MCBSP_REG_RCERH 0x38
5733 +#define OMAP_MCBSP_REG_XCERG 0x3A
5734 +#define OMAP_MCBSP_REG_XCERH 0x3C
5735 +
5736 +/* Dummy defines, these are not available on omap1 */
5737 +#define OMAP_MCBSP_REG_XCCR 0x00
5738 +#define OMAP_MCBSP_REG_RCCR 0x00
5739 +
5740 +#define AUDIO_MCBSP_DATAWRITE (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1)
5741 +#define AUDIO_MCBSP_DATAREAD (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1)
5742 +
5743 +#define AUDIO_MCBSP OMAP_MCBSP1
5744 +#define AUDIO_DMA_TX OMAP_DMA_MCBSP1_TX
5745 +#define AUDIO_DMA_RX OMAP_DMA_MCBSP1_RX
5746 +
5747 +#elif defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
5748 + defined(CONFIG_ARCH_OMAP4)
5749 +
5750 +#define OMAP_MCBSP_REG_DRR2 0x00
5751 +#define OMAP_MCBSP_REG_DRR1 0x04
5752 +#define OMAP_MCBSP_REG_DXR2 0x08
5753 +#define OMAP_MCBSP_REG_DXR1 0x0C
5754 +#define OMAP_MCBSP_REG_DRR 0x00
5755 +#define OMAP_MCBSP_REG_DXR 0x08
5756 +#define OMAP_MCBSP_REG_SPCR2 0x10
5757 +#define OMAP_MCBSP_REG_SPCR1 0x14
5758 +#define OMAP_MCBSP_REG_RCR2 0x18
5759 +#define OMAP_MCBSP_REG_RCR1 0x1C
5760 +#define OMAP_MCBSP_REG_XCR2 0x20
5761 +#define OMAP_MCBSP_REG_XCR1 0x24
5762 +#define OMAP_MCBSP_REG_SRGR2 0x28
5763 +#define OMAP_MCBSP_REG_SRGR1 0x2C
5764 +#define OMAP_MCBSP_REG_MCR2 0x30
5765 +#define OMAP_MCBSP_REG_MCR1 0x34
5766 +#define OMAP_MCBSP_REG_RCERA 0x38
5767 +#define OMAP_MCBSP_REG_RCERB 0x3C
5768 +#define OMAP_MCBSP_REG_XCERA 0x40
5769 +#define OMAP_MCBSP_REG_XCERB 0x44
5770 +#define OMAP_MCBSP_REG_PCR0 0x48
5771 +#define OMAP_MCBSP_REG_RCERC 0x4C
5772 +#define OMAP_MCBSP_REG_RCERD 0x50
5773 +#define OMAP_MCBSP_REG_XCERC 0x54
5774 +#define OMAP_MCBSP_REG_XCERD 0x58
5775 +#define OMAP_MCBSP_REG_RCERE 0x5C
5776 +#define OMAP_MCBSP_REG_RCERF 0x60
5777 +#define OMAP_MCBSP_REG_XCERE 0x64
5778 +#define OMAP_MCBSP_REG_XCERF 0x68
5779 +#define OMAP_MCBSP_REG_RCERG 0x6C
5780 +#define OMAP_MCBSP_REG_RCERH 0x70
5781 +#define OMAP_MCBSP_REG_XCERG 0x74
5782 +#define OMAP_MCBSP_REG_XCERH 0x78
5783 +#define OMAP_MCBSP_REG_SYSCON 0x8C
5784 +#define OMAP_MCBSP_REG_THRSH2 0x90
5785 +#define OMAP_MCBSP_REG_THRSH1 0x94
5786 +#define OMAP_MCBSP_REG_IRQST 0xA0
5787 +#define OMAP_MCBSP_REG_IRQEN 0xA4
5788 +#define OMAP_MCBSP_REG_WAKEUPEN 0xA8
5789 +#define OMAP_MCBSP_REG_XCCR 0xAC
5790 +#define OMAP_MCBSP_REG_RCCR 0xB0
5791 +
5792 +#define AUDIO_MCBSP_DATAWRITE (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1)
5793 +#define AUDIO_MCBSP_DATAREAD (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1)
5794 +
5795 +#define AUDIO_MCBSP OMAP_MCBSP2
5796 +#define AUDIO_DMA_TX OMAP24XX_DMA_MCBSP2_TX
5797 +#define AUDIO_DMA_RX OMAP24XX_DMA_MCBSP2_RX
5798 +
5799 +#endif
5800 +
5801 +/************************** McBSP SPCR1 bit definitions ***********************/
5802 +#define RRST 0x0001
5803 +#define RRDY 0x0002
5804 +#define RFULL 0x0004
5805 +#define RSYNC_ERR 0x0008
5806 +#define RINTM(value) ((value)<<4) /* bits 4:5 */
5807 +#define ABIS 0x0040
5808 +#define DXENA 0x0080
5809 +#define CLKSTP(value) ((value)<<11) /* bits 11:12 */
5810 +#define RJUST(value) ((value)<<13) /* bits 13:14 */
5811 +#define ALB 0x8000
5812 +#define DLB 0x8000
5813 +
5814 +/************************** McBSP SPCR2 bit definitions ***********************/
5815 +#define XRST 0x0001
5816 +#define XRDY 0x0002
5817 +#define XEMPTY 0x0004
5818 +#define XSYNC_ERR 0x0008
5819 +#define XINTM(value) ((value)<<4) /* bits 4:5 */
5820 +#define GRST 0x0040
5821 +#define FRST 0x0080
5822 +#define SOFT 0x0100
5823 +#define FREE 0x0200
5824 +
5825 +/************************** McBSP PCR bit definitions *************************/
5826 +#define CLKRP 0x0001
5827 +#define CLKXP 0x0002
5828 +#define FSRP 0x0004
5829 +#define FSXP 0x0008
5830 +#define DR_STAT 0x0010
5831 +#define DX_STAT 0x0020
5832 +#define CLKS_STAT 0x0040
5833 +#define SCLKME 0x0080
5834 +#define CLKRM 0x0100
5835 +#define CLKXM 0x0200
5836 +#define FSRM 0x0400
5837 +#define FSXM 0x0800
5838 +#define RIOEN 0x1000
5839 +#define XIOEN 0x2000
5840 +#define IDLE_EN 0x4000
5841 +
5842 +/************************** McBSP RCR1 bit definitions ************************/
5843 +#define RWDLEN1(value) ((value)<<5) /* Bits 5:7 */
5844 +#define RFRLEN1(value) ((value)<<8) /* Bits 8:14 */
5845 +
5846 +/************************** McBSP XCR1 bit definitions ************************/
5847 +#define XWDLEN1(value) ((value)<<5) /* Bits 5:7 */
5848 +#define XFRLEN1(value) ((value)<<8) /* Bits 8:14 */
5849 +
5850 +/*************************** McBSP RCR2 bit definitions ***********************/
5851 +#define RDATDLY(value) (value) /* Bits 0:1 */
5852 +#define RFIG 0x0004
5853 +#define RCOMPAND(value) ((value)<<3) /* Bits 3:4 */
5854 +#define RWDLEN2(value) ((value)<<5) /* Bits 5:7 */
5855 +#define RFRLEN2(value) ((value)<<8) /* Bits 8:14 */
5856 +#define RPHASE 0x8000
5857 +
5858 +/*************************** McBSP XCR2 bit definitions ***********************/
5859 +#define XDATDLY(value) (value) /* Bits 0:1 */
5860 +#define XFIG 0x0004
5861 +#define XCOMPAND(value) ((value)<<3) /* Bits 3:4 */
5862 +#define XWDLEN2(value) ((value)<<5) /* Bits 5:7 */
5863 +#define XFRLEN2(value) ((value)<<8) /* Bits 8:14 */
5864 +#define XPHASE 0x8000
5865 +
5866 +/************************* McBSP SRGR1 bit definitions ************************/
5867 +#define CLKGDV(value) (value) /* Bits 0:7 */
5868 +#define FWID(value) ((value)<<8) /* Bits 8:15 */
5869 +
5870 +/************************* McBSP SRGR2 bit definitions ************************/
5871 +#define FPER(value) (value) /* Bits 0:11 */
5872 +#define FSGM 0x1000
5873 +#define CLKSM 0x2000
5874 +#define CLKSP 0x4000
5875 +#define GSYNC 0x8000
5876 +
5877 +/************************* McBSP MCR1 bit definitions *************************/
5878 +#define RMCM 0x0001
5879 +#define RCBLK(value) ((value)<<2) /* Bits 2:4 */
5880 +#define RPABLK(value) ((value)<<5) /* Bits 5:6 */
5881 +#define RPBBLK(value) ((value)<<7) /* Bits 7:8 */
5882 +
5883 +/************************* McBSP MCR2 bit definitions *************************/
5884 +#define XMCM(value) (value) /* Bits 0:1 */
5885 +#define XCBLK(value) ((value)<<2) /* Bits 2:4 */
5886 +#define XPABLK(value) ((value)<<5) /* Bits 5:6 */
5887 +#define XPBBLK(value) ((value)<<7) /* Bits 7:8 */
5888 +
5889 +/*********************** McBSP XCCR bit definitions *************************/
5890 +#define EXTCLKGATE 0x8000
5891 +#define PPCONNECT 0x4000
5892 +#define DXENDLY(value) ((value)<<12) /* Bits 12:13 */
5893 +#define XFULL_CYCLE 0x0800
5894 +#define DILB 0x0020
5895 +#define XDMAEN 0x0008
5896 +#define XDISABLE 0x0001
5897 +
5898 +/********************** McBSP RCCR bit definitions *************************/
5899 +#define RFULL_CYCLE 0x0800
5900 +#define RDMAEN 0x0008
5901 +#define RDISABLE 0x0001
5902 +
5903 +/********************** McBSP SYSCONFIG bit definitions ********************/
5904 +#define CLOCKACTIVITY(value) ((value)<<8)
5905 +#define SIDLEMODE(value) ((value)<<3)
5906 +#define ENAWAKEUP 0x0004
5907 +#define SOFTRST 0x0002
5908 +
5909 +/********************** McBSP DMA operating modes **************************/
5910 +#define MCBSP_DMA_MODE_ELEMENT 0
5911 +#define MCBSP_DMA_MODE_THRESHOLD 1
5912 +#define MCBSP_DMA_MODE_FRAME 2
5913 +
5914 +/********************** McBSP WAKEUPEN bit definitions *********************/
5915 +#define XEMPTYEOFEN 0x4000
5916 +#define XRDYEN 0x0400
5917 +#define XEOFEN 0x0200
5918 +#define XFSXEN 0x0100
5919 +#define XSYNCERREN 0x0080
5920 +#define RRDYEN 0x0008
5921 +#define REOFEN 0x0004
5922 +#define RFSREN 0x0002
5923 +#define RSYNCERREN 0x0001
5924 +
5925 +/* we don't do multichannel for now */
5926 +struct omap_mcbsp_reg_cfg {
5927 + u16 spcr2;
5928 + u16 spcr1;
5929 + u16 rcr2;
5930 + u16 rcr1;
5931 + u16 xcr2;
5932 + u16 xcr1;
5933 + u16 srgr2;
5934 + u16 srgr1;
5935 + u16 mcr2;
5936 + u16 mcr1;
5937 + u16 pcr0;
5938 + u16 rcerc;
5939 + u16 rcerd;
5940 + u16 xcerc;
5941 + u16 xcerd;
5942 + u16 rcere;
5943 + u16 rcerf;
5944 + u16 xcere;
5945 + u16 xcerf;
5946 + u16 rcerg;
5947 + u16 rcerh;
5948 + u16 xcerg;
5949 + u16 xcerh;
5950 + u16 xccr;
5951 + u16 rccr;
5952 +};
5953 +
5954 +typedef enum {
5955 + OMAP_MCBSP1 = 0,
5956 + OMAP_MCBSP2,
5957 + OMAP_MCBSP3,
5958 + OMAP_MCBSP4,
5959 + OMAP_MCBSP5
5960 +} omap_mcbsp_id;
5961 +
5962 +typedef int __bitwise omap_mcbsp_io_type_t;
5963 +#define OMAP_MCBSP_IRQ_IO ((__force omap_mcbsp_io_type_t) 1)
5964 +#define OMAP_MCBSP_POLL_IO ((__force omap_mcbsp_io_type_t) 2)
5965 +
5966 +typedef enum {
5967 + OMAP_MCBSP_WORD_8 = 0,
5968 + OMAP_MCBSP_WORD_12,
5969 + OMAP_MCBSP_WORD_16,
5970 + OMAP_MCBSP_WORD_20,
5971 + OMAP_MCBSP_WORD_24,
5972 + OMAP_MCBSP_WORD_32,
5973 +} omap_mcbsp_word_length;
5974 +
5975 +typedef enum {
5976 + OMAP_MCBSP_CLK_RISING = 0,
5977 + OMAP_MCBSP_CLK_FALLING,
5978 +} omap_mcbsp_clk_polarity;
5979 +
5980 +typedef enum {
5981 + OMAP_MCBSP_FS_ACTIVE_HIGH = 0,
5982 + OMAP_MCBSP_FS_ACTIVE_LOW,
5983 +} omap_mcbsp_fs_polarity;
5984 +
5985 +typedef enum {
5986 + OMAP_MCBSP_CLK_STP_MODE_NO_DELAY = 0,
5987 + OMAP_MCBSP_CLK_STP_MODE_DELAY,
5988 +} omap_mcbsp_clk_stp_mode;
5989 +
5990 +
5991 +/******* SPI specific mode **********/
5992 +typedef enum {
5993 + OMAP_MCBSP_SPI_MASTER = 0,
5994 + OMAP_MCBSP_SPI_SLAVE,
5995 +} omap_mcbsp_spi_mode;
5996 +
5997 +struct omap_mcbsp_spi_cfg {
5998 + omap_mcbsp_spi_mode spi_mode;
5999 + omap_mcbsp_clk_polarity rx_clock_polarity;
6000 + omap_mcbsp_clk_polarity tx_clock_polarity;
6001 + omap_mcbsp_fs_polarity fsx_polarity;
6002 + u8 clk_div;
6003 + omap_mcbsp_clk_stp_mode clk_stp_mode;
6004 + omap_mcbsp_word_length word_length;
6005 +};
6006 +
6007 +/* Platform specific configuration */
6008 +struct omap_mcbsp_ops {
6009 + void (*request)(unsigned int);
6010 + void (*free)(unsigned int);
6011 +};
6012 +
6013 +struct omap_mcbsp_platform_data {
6014 + unsigned long phys_base;
6015 + u8 dma_rx_sync, dma_tx_sync;
6016 + u16 rx_irq, tx_irq;
6017 + struct omap_mcbsp_ops *ops;
6018 +#ifdef CONFIG_ARCH_OMAP34XX
6019 + u16 buffer_size;
6020 +#endif
6021 +};
6022 +
6023 +struct omap_mcbsp {
6024 + struct device *dev;
6025 + unsigned long phys_base;
6026 + void __iomem *io_base;
6027 + u8 id;
6028 + u8 free;
6029 + omap_mcbsp_word_length rx_word_length;
6030 + omap_mcbsp_word_length tx_word_length;
6031 +
6032 + omap_mcbsp_io_type_t io_type; /* IRQ or poll */
6033 + /* IRQ based TX/RX */
6034 + int rx_irq;
6035 + int tx_irq;
6036 +
6037 + /* DMA stuff */
6038 + u8 dma_rx_sync;
6039 + short dma_rx_lch;
6040 + u8 dma_tx_sync;
6041 + short dma_tx_lch;
6042 +
6043 + /* Completion queues */
6044 + struct completion tx_irq_completion;
6045 + struct completion rx_irq_completion;
6046 + struct completion tx_dma_completion;
6047 + struct completion rx_dma_completion;
6048 +
6049 + /* Protect the field .free, while checking if the mcbsp is in use */
6050 + spinlock_t lock;
6051 + struct omap_mcbsp_platform_data *pdata;
6052 + struct clk *iclk;
6053 + struct clk *fclk;
6054 +#ifdef CONFIG_ARCH_OMAP34XX
6055 + int dma_op_mode;
6056 + u16 max_tx_thres;
6057 + u16 max_rx_thres;
6058 +#endif
6059 +};
6060 +extern struct omap_mcbsp **mcbsp_ptr;
6061 +extern int omap_mcbsp_count;
6062 +
6063 +int omap_mcbsp_init(void);
6064 +void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config,
6065 + int size);
6066 +void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config);
6067 +#ifdef CONFIG_ARCH_OMAP34XX
6068 +void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold);
6069 +void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold);
6070 +u16 omap_mcbsp_get_max_tx_threshold(unsigned int id);
6071 +u16 omap_mcbsp_get_max_rx_threshold(unsigned int id);
6072 +int omap_mcbsp_get_dma_op_mode(unsigned int id);
6073 +#else
6074 +static inline void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold)
6075 +{ }
6076 +static inline void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold)
6077 +{ }
6078 +static inline u16 omap_mcbsp_get_max_tx_threshold(unsigned int id) { return 0; }
6079 +static inline u16 omap_mcbsp_get_max_rx_threshold(unsigned int id) { return 0; }
6080 +static inline int omap_mcbsp_get_dma_op_mode(unsigned int id) { return 0; }
6081 +#endif
6082 +int omap_mcbsp_request(unsigned int id);
6083 +void omap_mcbsp_free(unsigned int id);
6084 +void omap_mcbsp_start(unsigned int id, int tx, int rx);
6085 +void omap_mcbsp_stop(unsigned int id, int tx, int rx);
6086 +void omap_mcbsp_xmit_word(unsigned int id, u32 word);
6087 +u32 omap_mcbsp_recv_word(unsigned int id);
6088 +
6089 +int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer, unsigned int length);
6090 +int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer, unsigned int length);
6091 +int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word);
6092 +int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 * word);
6093 +
6094 +
6095 +/* SPI specific API */
6096 +void omap_mcbsp_set_spi_mode(unsigned int id, const struct omap_mcbsp_spi_cfg * spi_cfg);
6097 +
6098 +/* Polled read/write functions */
6099 +int omap_mcbsp_pollread(unsigned int id, u16 * buf);
6100 +int omap_mcbsp_pollwrite(unsigned int id, u16 buf);
6101 +int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type);
6102 +
6103 +#endif
6104 Index: linux-2.6.35/arch/arm/plat-omap/include/mach/mcspi.h
6105 ===================================================================
6106 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
6107 +++ linux-2.6.35/arch/arm/plat-omap/include/mach/mcspi.h 2010-08-08 12:57:01.000000000 +0200
6108 @@ -0,0 +1,15 @@
6109 +#ifndef _OMAP2_MCSPI_H
6110 +#define _OMAP2_MCSPI_H
6111 +
6112 +struct omap2_mcspi_platform_config {
6113 + unsigned short num_cs;
6114 +};
6115 +
6116 +struct omap2_mcspi_device_config {
6117 + unsigned turbo_mode:1;
6118 +
6119 + /* Do we want one channel enabled at the same time? */
6120 + unsigned single_channel:1;
6121 +};
6122 +
6123 +#endif
6124 Index: linux-2.6.35/arch/arm/plat-omap/include/mach/memory.h
6125 ===================================================================
6126 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
6127 +++ linux-2.6.35/arch/arm/plat-omap/include/mach/memory.h 2010-08-08 12:57:02.000000000 +0200
6128 @@ -0,0 +1,103 @@
6129 +/*
6130 + * arch/arm/plat-omap/include/mach/memory.h
6131 + *
6132 + * Memory map for OMAP-1510 and 1610
6133 + *
6134 + * Copyright (C) 2000 RidgeRun, Inc.
6135 + * Author: Greg Lonnon <glonnon@ridgerun.com>
6136 + *
6137 + * This file was derived from arch/arm/mach-intergrator/include/mach/memory.h
6138 + * Copyright (C) 1999 ARM Limited
6139 + *
6140 + * This program is free software; you can redistribute it and/or modify it
6141 + * under the terms of the GNU General Public License as published by the
6142 + * Free Software Foundation; either version 2 of the License, or (at your
6143 + * option) any later version.
6144 + *
6145 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
6146 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
6147 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
6148 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
6149 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
6150 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
6151 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
6152 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
6153 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
6154 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
6155 + *
6156 + * You should have received a copy of the GNU General Public License along
6157 + * with this program; if not, write to the Free Software Foundation, Inc.,
6158 + * 675 Mass Ave, Cambridge, MA 02139, USA.
6159 + */
6160 +
6161 +#ifndef __ASM_ARCH_MEMORY_H
6162 +#define __ASM_ARCH_MEMORY_H
6163 +
6164 +/*
6165 + * Physical DRAM offset.
6166 + */
6167 +#if defined(CONFIG_ARCH_OMAP1)
6168 +#define PHYS_OFFSET UL(0x10000000)
6169 +#elif defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
6170 + defined(CONFIG_ARCH_OMAP4)
6171 +#define PHYS_OFFSET UL(0x80000000)
6172 +#endif
6173 +
6174 +/*
6175 + * Bus address is physical address, except for OMAP-1510 Local Bus.
6176 + * OMAP-1510 bus address is translated into a Local Bus address if the
6177 + * OMAP bus type is lbus. We do the address translation based on the
6178 + * device overriding the defaults used in the dma-mapping API.
6179 + * Note that the is_lbus_device() test is not very efficient on 1510
6180 + * because of the strncmp().
6181 + */
6182 +#ifdef CONFIG_ARCH_OMAP15XX
6183 +
6184 +/*
6185 + * OMAP-1510 Local Bus address offset
6186 + */
6187 +#define OMAP1510_LB_OFFSET UL(0x30000000)
6188 +
6189 +#define virt_to_lbus(x) ((x) - PAGE_OFFSET + OMAP1510_LB_OFFSET)
6190 +#define lbus_to_virt(x) ((x) - OMAP1510_LB_OFFSET + PAGE_OFFSET)
6191 +#define is_lbus_device(dev) (cpu_is_omap15xx() && dev && (strncmp(dev_name(dev), "ohci", 4) == 0))
6192 +
6193 +#define __arch_page_to_dma(dev, page) \
6194 + ({ dma_addr_t __dma = page_to_phys(page); \
6195 + if (is_lbus_device(dev)) \
6196 + __dma = __dma - PHYS_OFFSET + OMAP1510_LB_OFFSET; \
6197 + __dma; })
6198 +
6199 +#define __arch_dma_to_page(dev, addr) \
6200 + ({ dma_addr_t __dma = addr; \
6201 + if (is_lbus_device(dev)) \
6202 + __dma += PHYS_OFFSET - OMAP1510_LB_OFFSET; \
6203 + phys_to_page(__dma); \
6204 + })
6205 +
6206 +#define __arch_dma_to_virt(dev, addr) ({ (void *) (is_lbus_device(dev) ? \
6207 + lbus_to_virt(addr) : \
6208 + __phys_to_virt(addr)); })
6209 +
6210 +#define __arch_virt_to_dma(dev, addr) ({ unsigned long __addr = (unsigned long)(addr); \
6211 + (dma_addr_t) (is_lbus_device(dev) ? \
6212 + virt_to_lbus(__addr) : \
6213 + __virt_to_phys(__addr)); })
6214 +
6215 +#endif /* CONFIG_ARCH_OMAP15XX */
6216 +
6217 +/* Override the ARM default */
6218 +#ifdef CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE
6219 +
6220 +#if (CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE == 0)
6221 +#undef CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE
6222 +#define CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE 2
6223 +#endif
6224 +
6225 +#define CONSISTENT_DMA_SIZE \
6226 + (((CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE + 1) & ~1) * 1024 * 1024)
6227 +
6228 +#endif
6229 +
6230 +#endif
6231 +
6232 Index: linux-2.6.35/arch/arm/plat-omap/include/mach/menelaus.h
6233 ===================================================================
6234 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
6235 +++ linux-2.6.35/arch/arm/plat-omap/include/mach/menelaus.h 2010-08-08 12:57:02.000000000 +0200
6236 @@ -0,0 +1,49 @@
6237 +/*
6238 + * arch/arm/plat-omap/include/mach/menelaus.h
6239 + *
6240 + * Functions to access Menelaus power management chip
6241 + */
6242 +
6243 +#ifndef __ASM_ARCH_MENELAUS_H
6244 +#define __ASM_ARCH_MENELAUS_H
6245 +
6246 +struct device;
6247 +
6248 +struct menelaus_platform_data {
6249 + int (* late_init)(struct device *dev);
6250 +};
6251 +
6252 +extern int menelaus_register_mmc_callback(void (*callback)(void *data, u8 card_mask),
6253 + void *data);
6254 +extern void menelaus_unregister_mmc_callback(void);
6255 +extern int menelaus_set_mmc_opendrain(int slot, int enable);
6256 +extern int menelaus_set_mmc_slot(int slot, int enable, int power, int cd_on);
6257 +
6258 +extern int menelaus_set_vmem(unsigned int mV);
6259 +extern int menelaus_set_vio(unsigned int mV);
6260 +extern int menelaus_set_vmmc(unsigned int mV);
6261 +extern int menelaus_set_vaux(unsigned int mV);
6262 +extern int menelaus_set_vdcdc(int dcdc, unsigned int mV);
6263 +extern int menelaus_set_slot_sel(int enable);
6264 +extern int menelaus_get_slot_pin_states(void);
6265 +extern int menelaus_set_vcore_sw(unsigned int mV);
6266 +extern int menelaus_set_vcore_hw(unsigned int roof_mV, unsigned int floor_mV);
6267 +
6268 +#define EN_VPLL_SLEEP (1 << 7)
6269 +#define EN_VMMC_SLEEP (1 << 6)
6270 +#define EN_VAUX_SLEEP (1 << 5)
6271 +#define EN_VIO_SLEEP (1 << 4)
6272 +#define EN_VMEM_SLEEP (1 << 3)
6273 +#define EN_DC3_SLEEP (1 << 2)
6274 +#define EN_DC2_SLEEP (1 << 1)
6275 +#define EN_VC_SLEEP (1 << 0)
6276 +
6277 +extern int menelaus_set_regulator_sleep(int enable, u32 val);
6278 +
6279 +#if defined(CONFIG_ARCH_OMAP24XX) && defined(CONFIG_MENELAUS)
6280 +#define omap_has_menelaus() 1
6281 +#else
6282 +#define omap_has_menelaus() 0
6283 +#endif
6284 +
6285 +#endif
6286 Index: linux-2.6.35/arch/arm/plat-omap/include/mach/mmc.h
6287 ===================================================================
6288 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
6289 +++ linux-2.6.35/arch/arm/plat-omap/include/mach/mmc.h 2010-08-08 12:57:03.000000000 +0200
6290 @@ -0,0 +1,157 @@
6291 +/*
6292 + * MMC definitions for OMAP2
6293 + *
6294 + * Copyright (C) 2006 Nokia Corporation
6295 + *
6296 + * This program is free software; you can redistribute it and/or modify
6297 + * it under the terms of the GNU General Public License version 2 as
6298 + * published by the Free Software Foundation.
6299 + */
6300 +
6301 +#ifndef __OMAP2_MMC_H
6302 +#define __OMAP2_MMC_H
6303 +
6304 +#include <linux/types.h>
6305 +#include <linux/device.h>
6306 +#include <linux/mmc/host.h>
6307 +
6308 +#include <plat/board.h>
6309 +
6310 +#define OMAP15XX_NR_MMC 1
6311 +#define OMAP16XX_NR_MMC 2
6312 +#define OMAP1_MMC_SIZE 0x080
6313 +#define OMAP1_MMC1_BASE 0xfffb7800
6314 +#define OMAP1_MMC2_BASE 0xfffb7c00 /* omap16xx only */
6315 +
6316 +#define OMAP24XX_NR_MMC 2
6317 +#define OMAP34XX_NR_MMC 3
6318 +#define OMAP44XX_NR_MMC 5
6319 +#define OMAP2420_MMC_SIZE OMAP1_MMC_SIZE
6320 +#define OMAP3_HSMMC_SIZE 0x200
6321 +#define OMAP4_HSMMC_SIZE 0x1000
6322 +#define OMAP2_MMC1_BASE 0x4809c000
6323 +#define OMAP2_MMC2_BASE 0x480b4000
6324 +#define OMAP3_MMC3_BASE 0x480ad000
6325 +#define OMAP4_MMC4_BASE 0x480d1000
6326 +#define OMAP4_MMC5_BASE 0x480d5000
6327 +#define OMAP4_MMC_REG_OFFSET 0x100
6328 +#define HSMMC5 (1 << 4)
6329 +#define HSMMC4 (1 << 3)
6330 +#define HSMMC3 (1 << 2)
6331 +#define HSMMC2 (1 << 1)
6332 +#define HSMMC1 (1 << 0)
6333 +
6334 +#define OMAP_MMC_MAX_SLOTS 2
6335 +
6336 +struct omap_mmc_platform_data {
6337 + /* back-link to device */
6338 + struct device *dev;
6339 +
6340 + /* number of slots per controller */
6341 + unsigned nr_slots:2;
6342 +
6343 + /* set if your board has components or wiring that limits the
6344 + * maximum frequency on the MMC bus */
6345 + unsigned int max_freq;
6346 +
6347 + /* switch the bus to a new slot */
6348 + int (* switch_slot)(struct device *dev, int slot);
6349 + /* initialize board-specific MMC functionality, can be NULL if
6350 + * not supported */
6351 + int (* init)(struct device *dev);
6352 + void (* cleanup)(struct device *dev);
6353 + void (* shutdown)(struct device *dev);
6354 +
6355 + /* To handle board related suspend/resume functionality for MMC */
6356 + int (*suspend)(struct device *dev, int slot);
6357 + int (*resume)(struct device *dev, int slot);
6358 +
6359 + /* Return context loss count due to PM states changing */
6360 + int (*get_context_loss_count)(struct device *dev);
6361 +
6362 + u64 dma_mask;
6363 +
6364 + struct omap_mmc_slot_data {
6365 +
6366 + /* 4 wire signaling is optional, and is used for SD/SDIO/HSMMC;
6367 + * 8 wire signaling is also optional, and is used with HSMMC
6368 + */
6369 + u8 wires;
6370 +
6371 + /*
6372 + * nomux means "standard" muxing is wrong on this board, and
6373 + * that board-specific code handled it before common init logic.
6374 + */
6375 + unsigned nomux:1;
6376 +
6377 + /* switch pin can be for card detect (default) or card cover */
6378 + unsigned cover:1;
6379 +
6380 + /* use the internal clock */
6381 + unsigned internal_clock:1;
6382 +
6383 + /* nonremovable e.g. eMMC */
6384 + unsigned nonremovable:1;
6385 +
6386 + /* Try to sleep or power off when possible */
6387 + unsigned power_saving:1;
6388 +
6389 + int switch_pin; /* gpio (card detect) */
6390 + int gpio_wp; /* gpio (write protect) */
6391 +
6392 + int (* set_bus_mode)(struct device *dev, int slot, int bus_mode);
6393 + int (* set_power)(struct device *dev, int slot, int power_on, int vdd);
6394 + int (* get_ro)(struct device *dev, int slot);
6395 + int (*set_sleep)(struct device *dev, int slot, int sleep,
6396 + int vdd, int cardsleep);
6397 +
6398 + /* return MMC cover switch state, can be NULL if not supported.
6399 + *
6400 + * possible return values:
6401 + * 0 - closed
6402 + * 1 - open
6403 + */
6404 + int (* get_cover_state)(struct device *dev, int slot);
6405 +
6406 + const char *name;
6407 + u32 ocr_mask;
6408 +
6409 + /* Card detection IRQs */
6410 + int card_detect_irq;
6411 + int (* card_detect)(int irq);
6412 +
6413 + unsigned int ban_openended:1;
6414 +
6415 + } slots[OMAP_MMC_MAX_SLOTS];
6416 +};
6417 +
6418 +/* called from board-specific card detection service routine */
6419 +extern void omap_mmc_notify_cover_event(struct device *dev, int slot, int is_closed);
6420 +
6421 +#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) || \
6422 + defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
6423 +void omap1_init_mmc(struct omap_mmc_platform_data **mmc_data,
6424 + int nr_controllers);
6425 +void omap2_init_mmc(struct omap_mmc_platform_data **mmc_data,
6426 + int nr_controllers);
6427 +int omap_mmc_add(const char *name, int id, unsigned long base,
6428 + unsigned long size, unsigned int irq,
6429 + struct omap_mmc_platform_data *data);
6430 +#else
6431 +static inline void omap1_init_mmc(struct omap_mmc_platform_data **mmc_data,
6432 + int nr_controllers)
6433 +{
6434 +}
6435 +static inline void omap2_init_mmc(struct omap_mmc_platform_data **mmc_data,
6436 + int nr_controllers)
6437 +{
6438 +}
6439 +static inline int omap_mmc_add(const char *name, int id, unsigned long base,
6440 + unsigned long size, unsigned int irq,
6441 + struct omap_mmc_platform_data *data)
6442 +{
6443 + return 0;
6444 +}
6445 +
6446 +#endif
6447 +#endif
6448 Index: linux-2.6.35/arch/arm/plat-omap/include/mach/mux.h
6449 ===================================================================
6450 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
6451 +++ linux-2.6.35/arch/arm/plat-omap/include/mach/mux.h 2010-08-08 12:57:04.000000000 +0200
6452 @@ -0,0 +1,662 @@
6453 +/*
6454 + * arch/arm/plat-omap/include/mach/mux.h
6455 + *
6456 + * Table of the Omap register configurations for the FUNC_MUX and
6457 + * PULL_DWN combinations.
6458 + *
6459 + * Copyright (C) 2004 - 2008 Texas Instruments Inc.
6460 + * Copyright (C) 2003 - 2008 Nokia Corporation
6461 + *
6462 + * Written by Tony Lindgren
6463 + *
6464 + * This program is free software; you can redistribute it and/or modify
6465 + * it under the terms of the GNU General Public License as published by
6466 + * the Free Software Foundation; either version 2 of the License, or
6467 + * (at your option) any later version.
6468 + *
6469 + * This program is distributed in the hope that it will be useful,
6470 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
6471 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
6472 + * GNU General Public License for more details.
6473 + *
6474 + * You should have received a copy of the GNU General Public License
6475 + * along with this program; if not, write to the Free Software
6476 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
6477 + *
6478 + * NOTE: Please use the following naming style for new pin entries.
6479 + * For example, W8_1610_MMC2_DAT0, where:
6480 + * - W8 = ball
6481 + * - 1610 = 1510 or 1610, none if common for both 1510 and 1610
6482 + * - MMC2_DAT0 = function
6483 + */
6484 +
6485 +#ifndef __ASM_ARCH_MUX_H
6486 +#define __ASM_ARCH_MUX_H
6487 +
6488 +#define PU_PD_SEL_NA 0 /* No pu_pd reg available */
6489 +#define PULL_DWN_CTRL_NA 0 /* No pull-down control needed */
6490 +
6491 +#ifdef CONFIG_OMAP_MUX_DEBUG
6492 +#define MUX_REG(reg, mode_offset, mode) .mux_reg_name = "FUNC_MUX_CTRL_"#reg, \
6493 + .mux_reg = FUNC_MUX_CTRL_##reg, \
6494 + .mask_offset = mode_offset, \
6495 + .mask = mode,
6496 +
6497 +#define PULL_REG(reg, bit, status) .pull_name = "PULL_DWN_CTRL_"#reg, \
6498 + .pull_reg = PULL_DWN_CTRL_##reg, \
6499 + .pull_bit = bit, \
6500 + .pull_val = status,
6501 +
6502 +#define PU_PD_REG(reg, status) .pu_pd_name = "PU_PD_SEL_"#reg, \
6503 + .pu_pd_reg = PU_PD_SEL_##reg, \
6504 + .pu_pd_val = status,
6505 +
6506 +#define MUX_REG_7XX(reg, mode_offset, mode) .mux_reg_name = "OMAP7XX_IO_CONF_"#reg, \
6507 + .mux_reg = OMAP7XX_IO_CONF_##reg, \
6508 + .mask_offset = mode_offset, \
6509 + .mask = mode,
6510 +
6511 +#define PULL_REG_7XX(reg, bit, status) .pull_name = "OMAP7XX_IO_CONF_"#reg, \
6512 + .pull_reg = OMAP7XX_IO_CONF_##reg, \
6513 + .pull_bit = bit, \
6514 + .pull_val = status,
6515 +
6516 +#else
6517 +
6518 +#define MUX_REG(reg, mode_offset, mode) .mux_reg = FUNC_MUX_CTRL_##reg, \
6519 + .mask_offset = mode_offset, \
6520 + .mask = mode,
6521 +
6522 +#define PULL_REG(reg, bit, status) .pull_reg = PULL_DWN_CTRL_##reg, \
6523 + .pull_bit = bit, \
6524 + .pull_val = status,
6525 +
6526 +#define PU_PD_REG(reg, status) .pu_pd_reg = PU_PD_SEL_##reg, \
6527 + .pu_pd_val = status,
6528 +
6529 +#define MUX_REG_7XX(reg, mode_offset, mode) \
6530 + .mux_reg = OMAP7XX_IO_CONF_##reg, \
6531 + .mask_offset = mode_offset, \
6532 + .mask = mode,
6533 +
6534 +#define PULL_REG_7XX(reg, bit, status) .pull_reg = OMAP7XX_IO_CONF_##reg, \
6535 + .pull_bit = bit, \
6536 + .pull_val = status,
6537 +
6538 +#endif /* CONFIG_OMAP_MUX_DEBUG */
6539 +
6540 +#define MUX_CFG(desc, mux_reg, mode_offset, mode, \
6541 + pull_reg, pull_bit, pull_status, \
6542 + pu_pd_reg, pu_pd_status, debug_status) \
6543 +{ \
6544 + .name = desc, \
6545 + .debug = debug_status, \
6546 + MUX_REG(mux_reg, mode_offset, mode) \
6547 + PULL_REG(pull_reg, pull_bit, pull_status) \
6548 + PU_PD_REG(pu_pd_reg, pu_pd_status) \
6549 +},
6550 +
6551 +
6552 +/*
6553 + * OMAP730/850 has a slightly different config for the pin mux.
6554 + * - config regs are the OMAP7XX_IO_CONF_x regs (see omap730.h) regs and
6555 + * not the FUNC_MUX_CTRL_x regs from hardware.h
6556 + * - for pull-up/down, only has one enable bit which is is in the same register
6557 + * as mux config
6558 + */
6559 +#define MUX_CFG_7XX(desc, mux_reg, mode_offset, mode, \
6560 + pull_bit, pull_status, debug_status)\
6561 +{ \
6562 + .name = desc, \
6563 + .debug = debug_status, \
6564 + MUX_REG_7XX(mux_reg, mode_offset, mode) \
6565 + PULL_REG_7XX(mux_reg, pull_bit, pull_status) \
6566 + PU_PD_REG(NA, 0) \
6567 +},
6568 +
6569 +#define MUX_CFG_24XX(desc, reg_offset, mode, \
6570 + pull_en, pull_mode, dbg) \
6571 +{ \
6572 + .name = desc, \
6573 + .debug = dbg, \
6574 + .mux_reg = reg_offset, \
6575 + .mask = mode, \
6576 + .pull_val = pull_en, \
6577 + .pu_pd_val = pull_mode, \
6578 +},
6579 +
6580 +/* 24xx/34xx mux bit defines */
6581 +#define OMAP2_PULL_ENA (1 << 3)
6582 +#define OMAP2_PULL_UP (1 << 4)
6583 +#define OMAP2_ALTELECTRICALSEL (1 << 5)
6584 +
6585 +struct pin_config {
6586 + char *name;
6587 + const unsigned int mux_reg;
6588 + unsigned char debug;
6589 +
6590 +#if defined(CONFIG_ARCH_OMAP1) || defined(CONFIG_ARCH_OMAP24XX)
6591 + const unsigned char mask_offset;
6592 + const unsigned char mask;
6593 +
6594 + const char *pull_name;
6595 + const unsigned int pull_reg;
6596 + const unsigned char pull_val;
6597 + const unsigned char pull_bit;
6598 +
6599 + const char *pu_pd_name;
6600 + const unsigned int pu_pd_reg;
6601 + const unsigned char pu_pd_val;
6602 +#endif
6603 +
6604 +#if defined(CONFIG_OMAP_MUX_DEBUG) || defined(CONFIG_OMAP_MUX_WARNINGS)
6605 + const char *mux_reg_name;
6606 +#endif
6607 +
6608 +};
6609 +
6610 +enum omap7xx_index {
6611 + /* OMAP 730 keyboard */
6612 + E2_7XX_KBR0,
6613 + J7_7XX_KBR1,
6614 + E1_7XX_KBR2,
6615 + F3_7XX_KBR3,
6616 + D2_7XX_KBR4,
6617 + C2_7XX_KBC0,
6618 + D3_7XX_KBC1,
6619 + E4_7XX_KBC2,
6620 + F4_7XX_KBC3,
6621 + E3_7XX_KBC4,
6622 +
6623 + /* USB */
6624 + AA17_7XX_USB_DM,
6625 + W16_7XX_USB_PU_EN,
6626 + W17_7XX_USB_VBUSI,
6627 + W18_7XX_USB_DMCK_OUT,
6628 + W19_7XX_USB_DCRST,
6629 +
6630 + /* MMC */
6631 + MMC_7XX_CMD,
6632 + MMC_7XX_CLK,
6633 + MMC_7XX_DAT0,
6634 +
6635 + /* I2C */
6636 + I2C_7XX_SCL,
6637 + I2C_7XX_SDA,
6638 +};
6639 +
6640 +enum omap1xxx_index {
6641 + /* UART1 (BT_UART_GATING)*/
6642 + UART1_TX = 0,
6643 + UART1_RTS,
6644 +
6645 + /* UART2 (COM_UART_GATING)*/
6646 + UART2_TX,
6647 + UART2_RX,
6648 + UART2_CTS,
6649 + UART2_RTS,
6650 +
6651 + /* UART3 (GIGA_UART_GATING) */
6652 + UART3_TX,
6653 + UART3_RX,
6654 + UART3_CTS,
6655 + UART3_RTS,
6656 + UART3_CLKREQ,
6657 + UART3_BCLK, /* 12MHz clock out */
6658 + Y15_1610_UART3_RTS,
6659 +
6660 + /* PWT & PWL */
6661 + PWT,
6662 + PWL,
6663 +
6664 + /* USB master generic */
6665 + R18_USB_VBUS,
6666 + R18_1510_USB_GPIO0,
6667 + W4_USB_PUEN,
6668 + W4_USB_CLKO,
6669 + W4_USB_HIGHZ,
6670 + W4_GPIO58,
6671 +
6672 + /* USB1 master */
6673 + USB1_SUSP,
6674 + USB1_SEO,
6675 + W13_1610_USB1_SE0,
6676 + USB1_TXEN,
6677 + USB1_TXD,
6678 + USB1_VP,
6679 + USB1_VM,
6680 + USB1_RCV,
6681 + USB1_SPEED,
6682 + R13_1610_USB1_SPEED,
6683 + R13_1710_USB1_SE0,
6684 +
6685 + /* USB2 master */
6686 + USB2_SUSP,
6687 + USB2_VP,
6688 + USB2_TXEN,
6689 + USB2_VM,
6690 + USB2_RCV,
6691 + USB2_SEO,
6692 + USB2_TXD,
6693 +
6694 + /* OMAP-1510 GPIO */
6695 + R18_1510_GPIO0,
6696 + R19_1510_GPIO1,
6697 + M14_1510_GPIO2,
6698 +
6699 + /* OMAP1610 GPIO */
6700 + P18_1610_GPIO3,
6701 + Y15_1610_GPIO17,
6702 +
6703 + /* OMAP-1710 GPIO */
6704 + R18_1710_GPIO0,
6705 + V2_1710_GPIO10,
6706 + N21_1710_GPIO14,
6707 + W15_1710_GPIO40,
6708 +
6709 + /* MPUIO */
6710 + MPUIO2,
6711 + N15_1610_MPUIO2,
6712 + MPUIO4,
6713 + MPUIO5,
6714 + T20_1610_MPUIO5,
6715 + W11_1610_MPUIO6,
6716 + V10_1610_MPUIO7,
6717 + W11_1610_MPUIO9,
6718 + V10_1610_MPUIO10,
6719 + W10_1610_MPUIO11,
6720 + E20_1610_MPUIO13,
6721 + U20_1610_MPUIO14,
6722 + E19_1610_MPUIO15,
6723 +
6724 + /* MCBSP2 */
6725 + MCBSP2_CLKR,
6726 + MCBSP2_CLKX,
6727 + MCBSP2_DR,
6728 + MCBSP2_DX,
6729 + MCBSP2_FSR,
6730 + MCBSP2_FSX,
6731 +
6732 + /* MCBSP3 */
6733 + MCBSP3_CLKX,
6734 +
6735 + /* Misc ballouts */
6736 + BALLOUT_V8_ARMIO3,
6737 + N20_HDQ,
6738 +
6739 + /* OMAP-1610 MMC2 */
6740 + W8_1610_MMC2_DAT0,
6741 + V8_1610_MMC2_DAT1,
6742 + W15_1610_MMC2_DAT2,
6743 + R10_1610_MMC2_DAT3,
6744 + Y10_1610_MMC2_CLK,
6745 + Y8_1610_MMC2_CMD,
6746 + V9_1610_MMC2_CMDDIR,
6747 + V5_1610_MMC2_DATDIR0,
6748 + W19_1610_MMC2_DATDIR1,
6749 + R18_1610_MMC2_CLKIN,
6750 +
6751 + /* OMAP-1610 External Trace Interface */
6752 + M19_1610_ETM_PSTAT0,
6753 + L15_1610_ETM_PSTAT1,
6754 + L18_1610_ETM_PSTAT2,
6755 + L19_1610_ETM_D0,
6756 + J19_1610_ETM_D6,
6757 + J18_1610_ETM_D7,
6758 +
6759 + /* OMAP16XX GPIO */
6760 + P20_1610_GPIO4,
6761 + V9_1610_GPIO7,
6762 + W8_1610_GPIO9,
6763 + N20_1610_GPIO11,
6764 + N19_1610_GPIO13,
6765 + P10_1610_GPIO22,
6766 + V5_1610_GPIO24,
6767 + AA20_1610_GPIO_41,
6768 + W19_1610_GPIO48,
6769 + M7_1610_GPIO62,
6770 + V14_16XX_GPIO37,
6771 + R9_16XX_GPIO18,
6772 + L14_16XX_GPIO49,
6773 +
6774 + /* OMAP-1610 uWire */
6775 + V19_1610_UWIRE_SCLK,
6776 + U18_1610_UWIRE_SDI,
6777 + W21_1610_UWIRE_SDO,
6778 + N14_1610_UWIRE_CS0,
6779 + P15_1610_UWIRE_CS3,
6780 + N15_1610_UWIRE_CS1,
6781 +
6782 + /* OMAP-1610 SPI */
6783 + U19_1610_SPIF_SCK,
6784 + U18_1610_SPIF_DIN,
6785 + P20_1610_SPIF_DIN,
6786 + W21_1610_SPIF_DOUT,
6787 + R18_1610_SPIF_DOUT,
6788 + N14_1610_SPIF_CS0,
6789 + N15_1610_SPIF_CS1,
6790 + T19_1610_SPIF_CS2,
6791 + P15_1610_SPIF_CS3,
6792 +
6793 + /* OMAP-1610 Flash */
6794 + L3_1610_FLASH_CS2B_OE,
6795 + M8_1610_FLASH_CS2B_WE,
6796 +
6797 + /* First MMC */
6798 + MMC_CMD,
6799 + MMC_DAT1,
6800 + MMC_DAT2,
6801 + MMC_DAT0,
6802 + MMC_CLK,
6803 + MMC_DAT3,
6804 +
6805 + /* OMAP-1710 MMC CMDDIR and DATDIR0 */
6806 + M15_1710_MMC_CLKI,
6807 + P19_1710_MMC_CMDDIR,
6808 + P20_1710_MMC_DATDIR0,
6809 +
6810 + /* OMAP-1610 USB0 alternate pin configuration */
6811 + W9_USB0_TXEN,
6812 + AA9_USB0_VP,
6813 + Y5_USB0_RCV,
6814 + R9_USB0_VM,
6815 + V6_USB0_TXD,
6816 + W5_USB0_SE0,
6817 + V9_USB0_SPEED,
6818 + V9_USB0_SUSP,
6819 +
6820 + /* USB2 */
6821 + W9_USB2_TXEN,
6822 + AA9_USB2_VP,
6823 + Y5_USB2_RCV,
6824 + R9_USB2_VM,
6825 + V6_USB2_TXD,
6826 + W5_USB2_SE0,
6827 +
6828 + /* 16XX UART */
6829 + R13_1610_UART1_TX,
6830 + V14_16XX_UART1_RX,
6831 + R14_1610_UART1_CTS,
6832 + AA15_1610_UART1_RTS,
6833 + R9_16XX_UART2_RX,
6834 + L14_16XX_UART3_RX,
6835 +
6836 + /* I2C OMAP-1610 */
6837 + I2C_SCL,
6838 + I2C_SDA,
6839 +
6840 + /* Keypad */
6841 + F18_1610_KBC0,
6842 + D20_1610_KBC1,
6843 + D19_1610_KBC2,
6844 + E18_1610_KBC3,
6845 + C21_1610_KBC4,
6846 + G18_1610_KBR0,
6847 + F19_1610_KBR1,
6848 + H14_1610_KBR2,
6849 + E20_1610_KBR3,
6850 + E19_1610_KBR4,
6851 + N19_1610_KBR5,
6852 +
6853 + /* Power management */
6854 + T20_1610_LOW_PWR,
6855 +
6856 + /* MCLK Settings */
6857 + V5_1710_MCLK_ON,
6858 + V5_1710_MCLK_OFF,
6859 + R10_1610_MCLK_ON,
6860 + R10_1610_MCLK_OFF,
6861 +
6862 + /* CompactFlash controller */
6863 + P11_1610_CF_CD2,
6864 + R11_1610_CF_IOIS16,
6865 + V10_1610_CF_IREQ,
6866 + W10_1610_CF_RESET,
6867 + W11_1610_CF_CD1,
6868 +
6869 + /* parallel camera */
6870 + J15_1610_CAM_LCLK,
6871 + J18_1610_CAM_D7,
6872 + J19_1610_CAM_D6,
6873 + J14_1610_CAM_D5,
6874 + K18_1610_CAM_D4,
6875 + K19_1610_CAM_D3,
6876 + K15_1610_CAM_D2,
6877 + K14_1610_CAM_D1,
6878 + L19_1610_CAM_D0,
6879 + L18_1610_CAM_VS,
6880 + L15_1610_CAM_HS,
6881 + M19_1610_CAM_RSTZ,
6882 + Y15_1610_CAM_OUTCLK,
6883 +
6884 + /* serial camera */
6885 + H19_1610_CAM_EXCLK,
6886 + Y12_1610_CCP_CLKP,
6887 + W13_1610_CCP_CLKM,
6888 + W14_1610_CCP_DATAP,
6889 + Y14_1610_CCP_DATAM,
6890 +
6891 +};
6892 +
6893 +enum omap24xx_index {
6894 + /* 24xx I2C */
6895 + M19_24XX_I2C1_SCL,
6896 + L15_24XX_I2C1_SDA,
6897 + J15_24XX_I2C2_SCL,
6898 + H19_24XX_I2C2_SDA,
6899 +
6900 + /* 24xx Menelaus interrupt */
6901 + W19_24XX_SYS_NIRQ,
6902 +
6903 + /* 24xx clock */
6904 + W14_24XX_SYS_CLKOUT,
6905 +
6906 + /* 24xx GPMC chipselects, wait pin monitoring */
6907 + E2_GPMC_NCS2,
6908 + L2_GPMC_NCS7,
6909 + L3_GPMC_WAIT0,
6910 + N7_GPMC_WAIT1,
6911 + M1_GPMC_WAIT2,
6912 + P1_GPMC_WAIT3,
6913 +
6914 + /* 242X McBSP */
6915 + Y15_24XX_MCBSP2_CLKX,
6916 + R14_24XX_MCBSP2_FSX,
6917 + W15_24XX_MCBSP2_DR,
6918 + V15_24XX_MCBSP2_DX,
6919 +
6920 + /* 24xx GPIO */
6921 + M21_242X_GPIO11,
6922 + P21_242X_GPIO12,
6923 + AA10_242X_GPIO13,
6924 + AA6_242X_GPIO14,
6925 + AA4_242X_GPIO15,
6926 + Y11_242X_GPIO16,
6927 + AA12_242X_GPIO17,
6928 + AA8_242X_GPIO58,
6929 + Y20_24XX_GPIO60,
6930 + W4__24XX_GPIO74,
6931 + N15_24XX_GPIO85,
6932 + M15_24XX_GPIO92,
6933 + P20_24XX_GPIO93,
6934 + P18_24XX_GPIO95,
6935 + M18_24XX_GPIO96,
6936 + L14_24XX_GPIO97,
6937 + J15_24XX_GPIO99,
6938 + V14_24XX_GPIO117,
6939 + P14_24XX_GPIO125,
6940 +
6941 + /* 242x DBG GPIO */
6942 + V4_242X_GPIO49,
6943 + W2_242X_GPIO50,
6944 + U4_242X_GPIO51,
6945 + V3_242X_GPIO52,
6946 + V2_242X_GPIO53,
6947 + V6_242X_GPIO53,
6948 + T4_242X_GPIO54,
6949 + Y4_242X_GPIO54,
6950 + T3_242X_GPIO55,
6951 + U2_242X_GPIO56,
6952 +
6953 + /* 24xx external DMA requests */
6954 + AA10_242X_DMAREQ0,
6955 + AA6_242X_DMAREQ1,
6956 + E4_242X_DMAREQ2,
6957 + G4_242X_DMAREQ3,
6958 + D3_242X_DMAREQ4,
6959 + E3_242X_DMAREQ5,
6960 +
6961 + /* UART3 */
6962 + K15_24XX_UART3_TX,
6963 + K14_24XX_UART3_RX,
6964 +
6965 + /* MMC/SDIO */
6966 + G19_24XX_MMC_CLKO,
6967 + H18_24XX_MMC_CMD,
6968 + F20_24XX_MMC_DAT0,
6969 + H14_24XX_MMC_DAT1,
6970 + E19_24XX_MMC_DAT2,
6971 + D19_24XX_MMC_DAT3,
6972 + F19_24XX_MMC_DAT_DIR0,
6973 + E20_24XX_MMC_DAT_DIR1,
6974 + F18_24XX_MMC_DAT_DIR2,
6975 + E18_24XX_MMC_DAT_DIR3,
6976 + G18_24XX_MMC_CMD_DIR,
6977 + H15_24XX_MMC_CLKI,
6978 +
6979 + /* Full speed USB */
6980 + J20_24XX_USB0_PUEN,
6981 + J19_24XX_USB0_VP,
6982 + K20_24XX_USB0_VM,
6983 + J18_24XX_USB0_RCV,
6984 + K19_24XX_USB0_TXEN,
6985 + J14_24XX_USB0_SE0,
6986 + K18_24XX_USB0_DAT,
6987 +
6988 + N14_24XX_USB1_SE0,
6989 + W12_24XX_USB1_SE0,
6990 + P15_24XX_USB1_DAT,
6991 + R13_24XX_USB1_DAT,
6992 + W20_24XX_USB1_TXEN,
6993 + P13_24XX_USB1_TXEN,
6994 + V19_24XX_USB1_RCV,
6995 + V12_24XX_USB1_RCV,
6996 +
6997 + AA10_24XX_USB2_SE0,
6998 + Y11_24XX_USB2_DAT,
6999 + AA12_24XX_USB2_TXEN,
7000 + AA6_24XX_USB2_RCV,
7001 + AA4_24XX_USB2_TLLSE0,
7002 +
7003 + /* Keypad GPIO*/
7004 + T19_24XX_KBR0,
7005 + R19_24XX_KBR1,
7006 + V18_24XX_KBR2,
7007 + M21_24XX_KBR3,
7008 + E5__24XX_KBR4,
7009 + M18_24XX_KBR5,
7010 + R20_24XX_KBC0,
7011 + M14_24XX_KBC1,
7012 + H19_24XX_KBC2,
7013 + V17_24XX_KBC3,
7014 + P21_24XX_KBC4,
7015 + L14_24XX_KBC5,
7016 + N19_24XX_KBC6,
7017 +
7018 + /* 24xx Menelaus Keypad GPIO */
7019 + B3__24XX_KBR5,
7020 + AA4_24XX_KBC2,
7021 + B13_24XX_KBC6,
7022 +
7023 + /* 2430 USB */
7024 + AD9_2430_USB0_PUEN,
7025 + Y11_2430_USB0_VP,
7026 + AD7_2430_USB0_VM,
7027 + AE7_2430_USB0_RCV,
7028 + AD4_2430_USB0_TXEN,
7029 + AF9_2430_USB0_SE0,
7030 + AE6_2430_USB0_DAT,
7031 + AD24_2430_USB1_SE0,
7032 + AB24_2430_USB1_RCV,
7033 + Y25_2430_USB1_TXEN,
7034 + AA26_2430_USB1_DAT,
7035 +
7036 + /* 2430 HS-USB */
7037 + AD9_2430_USB0HS_DATA3,
7038 + Y11_2430_USB0HS_DATA4,
7039 + AD7_2430_USB0HS_DATA5,
7040 + AE7_2430_USB0HS_DATA6,
7041 + AD4_2430_USB0HS_DATA2,
7042 + AF9_2430_USB0HS_DATA0,
7043 + AE6_2430_USB0HS_DATA1,
7044 + AE8_2430_USB0HS_CLK,
7045 + AD8_2430_USB0HS_DIR,
7046 + AE5_2430_USB0HS_STP,
7047 + AE9_2430_USB0HS_NXT,
7048 + AC7_2430_USB0HS_DATA7,
7049 +
7050 + /* 2430 McBSP */
7051 + AD6_2430_MCBSP_CLKS,
7052 +
7053 + AB2_2430_MCBSP1_CLKR,
7054 + AD5_2430_MCBSP1_FSR,
7055 + AA1_2430_MCBSP1_DX,
7056 + AF3_2430_MCBSP1_DR,
7057 + AB3_2430_MCBSP1_FSX,
7058 + Y9_2430_MCBSP1_CLKX,
7059 +
7060 + AC10_2430_MCBSP2_FSX,
7061 + AD16_2430_MCBSP2_CLX,
7062 + AE13_2430_MCBSP2_DX,
7063 + AD13_2430_MCBSP2_DR,
7064 + AC10_2430_MCBSP2_FSX_OFF,
7065 + AD16_2430_MCBSP2_CLX_OFF,
7066 + AE13_2430_MCBSP2_DX_OFF,
7067 + AD13_2430_MCBSP2_DR_OFF,
7068 +
7069 + AC9_2430_MCBSP3_CLKX,
7070 + AE4_2430_MCBSP3_FSX,
7071 + AE2_2430_MCBSP3_DR,
7072 + AF4_2430_MCBSP3_DX,
7073 +
7074 + N3_2430_MCBSP4_CLKX,
7075 + AD23_2430_MCBSP4_DR,
7076 + AB25_2430_MCBSP4_DX,
7077 + AC25_2430_MCBSP4_FSX,
7078 +
7079 + AE16_2430_MCBSP5_CLKX,
7080 + AF12_2430_MCBSP5_FSX,
7081 + K7_2430_MCBSP5_DX,
7082 + M1_2430_MCBSP5_DR,
7083 +
7084 + /* 2430 McSPI*/
7085 + Y18_2430_MCSPI1_CLK,
7086 + AD15_2430_MCSPI1_SIMO,
7087 + AE17_2430_MCSPI1_SOMI,
7088 + U1_2430_MCSPI1_CS0,
7089 +
7090 + /* Touchscreen GPIO */
7091 + AF19_2430_GPIO_85,
7092 +
7093 +};
7094 +
7095 +struct omap_mux_cfg {
7096 + struct pin_config *pins;
7097 + unsigned long size;
7098 + int (*cfg_reg)(const struct pin_config *cfg);
7099 +};
7100 +
7101 +#ifdef CONFIG_OMAP_MUX
7102 +/* setup pin muxing in Linux */
7103 +extern int omap1_mux_init(void);
7104 +extern int omap_mux_register(struct omap_mux_cfg *);
7105 +extern int omap_cfg_reg(unsigned long reg_cfg);
7106 +#else
7107 +/* boot loader does it all (no warnings from CONFIG_OMAP_MUX_WARNINGS) */
7108 +static inline int omap1_mux_init(void) { return 0; }
7109 +static inline int omap_cfg_reg(unsigned long reg_cfg) { return 0; }
7110 +#endif
7111 +
7112 +extern int omap2_mux_init(void);
7113 +
7114 +#endif
7115 Index: linux-2.6.35/arch/arm/plat-omap/include/mach/nand.h
7116 ===================================================================
7117 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
7118 +++ linux-2.6.35/arch/arm/plat-omap/include/mach/nand.h 2010-08-08 12:57:04.000000000 +0200
7119 @@ -0,0 +1,24 @@
7120 +/*
7121 + * arch/arm/plat-omap/include/mach/nand.h
7122 + *
7123 + * Copyright (C) 2006 Micron Technology Inc.
7124 + *
7125 + * This program is free software; you can redistribute it and/or modify
7126 + * it under the terms of the GNU General Public License version 2 as
7127 + * published by the Free Software Foundation.
7128 + */
7129 +
7130 +#include <linux/mtd/partitions.h>
7131 +
7132 +struct omap_nand_platform_data {
7133 + unsigned int options;
7134 + int cs;
7135 + int gpio_irq;
7136 + struct mtd_partition *parts;
7137 + int nr_parts;
7138 + int (*nand_setup)(void __iomem *);
7139 + int (*dev_ready)(struct omap_nand_platform_data *);
7140 + int dma_channel;
7141 + void __iomem *gpmc_cs_baseaddr;
7142 + void __iomem *gpmc_baseaddr;
7143 +};
7144 Index: linux-2.6.35/arch/arm/plat-omap/include/mach/omap1510.h
7145 ===================================================================
7146 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
7147 +++ linux-2.6.35/arch/arm/plat-omap/include/mach/omap1510.h 2010-08-08 12:57:05.000000000 +0200
7148 @@ -0,0 +1,50 @@
7149 +/* arch/arm/plat-omap/include/mach/omap1510.h
7150 + *
7151 + * Hardware definitions for TI OMAP1510 processor.
7152 + *
7153 + * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com>
7154 + *
7155 + * This program is free software; you can redistribute it and/or modify it
7156 + * under the terms of the GNU General Public License as published by the
7157 + * Free Software Foundation; either version 2 of the License, or (at your
7158 + * option) any later version.
7159 + *
7160 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
7161 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
7162 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
7163 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
7164 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
7165 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
7166 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
7167 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
7168 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
7169 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
7170 + *
7171 + * You should have received a copy of the GNU General Public License along
7172 + * with this program; if not, write to the Free Software Foundation, Inc.,
7173 + * 675 Mass Ave, Cambridge, MA 02139, USA.
7174 + */
7175 +
7176 +#ifndef __ASM_ARCH_OMAP15XX_H
7177 +#define __ASM_ARCH_OMAP15XX_H
7178 +
7179 +/*
7180 + * ----------------------------------------------------------------------------
7181 + * Base addresses
7182 + * ----------------------------------------------------------------------------
7183 + */
7184 +
7185 +/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
7186 +
7187 +#define OMAP1510_DSP_BASE 0xE0000000
7188 +#define OMAP1510_DSP_SIZE 0x28000
7189 +#define OMAP1510_DSP_START 0xE0000000
7190 +
7191 +#define OMAP1510_DSPREG_BASE 0xE1000000
7192 +#define OMAP1510_DSPREG_SIZE SZ_128K
7193 +#define OMAP1510_DSPREG_START 0xE1000000
7194 +
7195 +#define OMAP1510_DSP_MMU_BASE (0xfffed200)
7196 +
7197 +#endif /* __ASM_ARCH_OMAP15XX_H */
7198 +
7199 Index: linux-2.6.35/arch/arm/plat-omap/include/mach/omap16xx.h
7200 ===================================================================
7201 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
7202 +++ linux-2.6.35/arch/arm/plat-omap/include/mach/omap16xx.h 2010-08-08 12:57:06.000000000 +0200
7203 @@ -0,0 +1,202 @@
7204 +/* arch/arm/plat-omap/include/mach/omap16xx.h
7205 + *
7206 + * Hardware definitions for TI OMAP1610/5912/1710 processors.
7207 + *
7208 + * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com>
7209 + *
7210 + * This program is free software; you can redistribute it and/or modify it
7211 + * under the terms of the GNU General Public License as published by the
7212 + * Free Software Foundation; either version 2 of the License, or (at your
7213 + * option) any later version.
7214 + *
7215 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
7216 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
7217 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
7218 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
7219 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
7220 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
7221 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
7222 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
7223 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
7224 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
7225 + *
7226 + * You should have received a copy of the GNU General Public License along
7227 + * with this program; if not, write to the Free Software Foundation, Inc.,
7228 + * 675 Mass Ave, Cambridge, MA 02139, USA.
7229 + */
7230 +
7231 +#ifndef __ASM_ARCH_OMAP16XX_H
7232 +#define __ASM_ARCH_OMAP16XX_H
7233 +
7234 +/*
7235 + * ----------------------------------------------------------------------------
7236 + * Base addresses
7237 + * ----------------------------------------------------------------------------
7238 + */
7239 +
7240 +/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
7241 +
7242 +#define OMAP16XX_DSP_BASE 0xE0000000
7243 +#define OMAP16XX_DSP_SIZE 0x28000
7244 +#define OMAP16XX_DSP_START 0xE0000000
7245 +
7246 +#define OMAP16XX_DSPREG_BASE 0xE1000000
7247 +#define OMAP16XX_DSPREG_SIZE SZ_128K
7248 +#define OMAP16XX_DSPREG_START 0xE1000000
7249 +
7250 +#define OMAP16XX_SEC_BASE 0xFFFE4000
7251 +#define OMAP16XX_SEC_DES (OMAP16XX_SEC_BASE + 0x0000)
7252 +#define OMAP16XX_SEC_SHA1MD5 (OMAP16XX_SEC_BASE + 0x0800)
7253 +#define OMAP16XX_SEC_RNG (OMAP16XX_SEC_BASE + 0x1000)
7254 +
7255 +/*
7256 + * ---------------------------------------------------------------------------
7257 + * Interrupts
7258 + * ---------------------------------------------------------------------------
7259 + */
7260 +#define OMAP_IH2_0_BASE (0xfffe0000)
7261 +#define OMAP_IH2_1_BASE (0xfffe0100)
7262 +#define OMAP_IH2_2_BASE (0xfffe0200)
7263 +#define OMAP_IH2_3_BASE (0xfffe0300)
7264 +
7265 +#define OMAP_IH2_0_ITR (OMAP_IH2_0_BASE + 0x00)
7266 +#define OMAP_IH2_0_MIR (OMAP_IH2_0_BASE + 0x04)
7267 +#define OMAP_IH2_0_SIR_IRQ (OMAP_IH2_0_BASE + 0x10)
7268 +#define OMAP_IH2_0_SIR_FIQ (OMAP_IH2_0_BASE + 0x14)
7269 +#define OMAP_IH2_0_CONTROL (OMAP_IH2_0_BASE + 0x18)
7270 +#define OMAP_IH2_0_ILR0 (OMAP_IH2_0_BASE + 0x1c)
7271 +#define OMAP_IH2_0_ISR (OMAP_IH2_0_BASE + 0x9c)
7272 +
7273 +#define OMAP_IH2_1_ITR (OMAP_IH2_1_BASE + 0x00)
7274 +#define OMAP_IH2_1_MIR (OMAP_IH2_1_BASE + 0x04)
7275 +#define OMAP_IH2_1_SIR_IRQ (OMAP_IH2_1_BASE + 0x10)
7276 +#define OMAP_IH2_1_SIR_FIQ (OMAP_IH2_1_BASE + 0x14)
7277 +#define OMAP_IH2_1_CONTROL (OMAP_IH2_1_BASE + 0x18)
7278 +#define OMAP_IH2_1_ILR1 (OMAP_IH2_1_BASE + 0x1c)
7279 +#define OMAP_IH2_1_ISR (OMAP_IH2_1_BASE + 0x9c)
7280 +
7281 +#define OMAP_IH2_2_ITR (OMAP_IH2_2_BASE + 0x00)
7282 +#define OMAP_IH2_2_MIR (OMAP_IH2_2_BASE + 0x04)
7283 +#define OMAP_IH2_2_SIR_IRQ (OMAP_IH2_2_BASE + 0x10)
7284 +#define OMAP_IH2_2_SIR_FIQ (OMAP_IH2_2_BASE + 0x14)
7285 +#define OMAP_IH2_2_CONTROL (OMAP_IH2_2_BASE + 0x18)
7286 +#define OMAP_IH2_2_ILR2 (OMAP_IH2_2_BASE + 0x1c)
7287 +#define OMAP_IH2_2_ISR (OMAP_IH2_2_BASE + 0x9c)
7288 +
7289 +#define OMAP_IH2_3_ITR (OMAP_IH2_3_BASE + 0x00)
7290 +#define OMAP_IH2_3_MIR (OMAP_IH2_3_BASE + 0x04)
7291 +#define OMAP_IH2_3_SIR_IRQ (OMAP_IH2_3_BASE + 0x10)
7292 +#define OMAP_IH2_3_SIR_FIQ (OMAP_IH2_3_BASE + 0x14)
7293 +#define OMAP_IH2_3_CONTROL (OMAP_IH2_3_BASE + 0x18)
7294 +#define OMAP_IH2_3_ILR3 (OMAP_IH2_3_BASE + 0x1c)
7295 +#define OMAP_IH2_3_ISR (OMAP_IH2_3_BASE + 0x9c)
7296 +
7297 +/*
7298 + * ----------------------------------------------------------------------------
7299 + * Clocks
7300 + * ----------------------------------------------------------------------------
7301 + */
7302 +#define OMAP16XX_ARM_IDLECT3 (CLKGEN_REG_BASE + 0x24)
7303 +
7304 +/*
7305 + * ----------------------------------------------------------------------------
7306 + * Pin configuration registers
7307 + * ----------------------------------------------------------------------------
7308 + */
7309 +#define OMAP16XX_CONF_VOLTAGE_VDDSHV6 (1 << 8)
7310 +#define OMAP16XX_CONF_VOLTAGE_VDDSHV7 (1 << 9)
7311 +#define OMAP16XX_CONF_VOLTAGE_VDDSHV8 (1 << 10)
7312 +#define OMAP16XX_CONF_VOLTAGE_VDDSHV9 (1 << 11)
7313 +#define OMAP16XX_SUBLVDS_CONF_VALID (1 << 13)
7314 +
7315 +/*
7316 + * ----------------------------------------------------------------------------
7317 + * System control registers
7318 + * ----------------------------------------------------------------------------
7319 + */
7320 +#define OMAP1610_RESET_CONTROL 0xfffe1140
7321 +
7322 +/*
7323 + * ---------------------------------------------------------------------------
7324 + * TIPB bus interface
7325 + * ---------------------------------------------------------------------------
7326 + */
7327 +#define TIPB_SWITCH_BASE (0xfffbc800)
7328 +#define OMAP16XX_MMCSD2_SSW_MPU_CONF (TIPB_SWITCH_BASE + 0x160)
7329 +
7330 +/* UART3 Registers Mapping through MPU bus */
7331 +#define UART3_RHR (OMAP_UART3_BASE + 0)
7332 +#define UART3_THR (OMAP_UART3_BASE + 0)
7333 +#define UART3_DLL (OMAP_UART3_BASE + 0)
7334 +#define UART3_IER (OMAP_UART3_BASE + 4)
7335 +#define UART3_DLH (OMAP_UART3_BASE + 4)
7336 +#define UART3_IIR (OMAP_UART3_BASE + 8)
7337 +#define UART3_FCR (OMAP_UART3_BASE + 8)
7338 +#define UART3_EFR (OMAP_UART3_BASE + 8)
7339 +#define UART3_LCR (OMAP_UART3_BASE + 0x0C)
7340 +#define UART3_MCR (OMAP_UART3_BASE + 0x10)
7341 +#define UART3_XON1_ADDR1 (OMAP_UART3_BASE + 0x10)
7342 +#define UART3_XON2_ADDR2 (OMAP_UART3_BASE + 0x14)
7343 +#define UART3_LSR (OMAP_UART3_BASE + 0x14)
7344 +#define UART3_TCR (OMAP_UART3_BASE + 0x18)
7345 +#define UART3_MSR (OMAP_UART3_BASE + 0x18)
7346 +#define UART3_XOFF1 (OMAP_UART3_BASE + 0x18)
7347 +#define UART3_XOFF2 (OMAP_UART3_BASE + 0x1C)
7348 +#define UART3_SPR (OMAP_UART3_BASE + 0x1C)
7349 +#define UART3_TLR (OMAP_UART3_BASE + 0x1C)
7350 +#define UART3_MDR1 (OMAP_UART3_BASE + 0x20)
7351 +#define UART3_MDR2 (OMAP_UART3_BASE + 0x24)
7352 +#define UART3_SFLSR (OMAP_UART3_BASE + 0x28)
7353 +#define UART3_TXFLL (OMAP_UART3_BASE + 0x28)
7354 +#define UART3_RESUME (OMAP_UART3_BASE + 0x2C)
7355 +#define UART3_TXFLH (OMAP_UART3_BASE + 0x2C)
7356 +#define UART3_SFREGL (OMAP_UART3_BASE + 0x30)
7357 +#define UART3_RXFLL (OMAP_UART3_BASE + 0x30)
7358 +#define UART3_SFREGH (OMAP_UART3_BASE + 0x34)
7359 +#define UART3_RXFLH (OMAP_UART3_BASE + 0x34)
7360 +#define UART3_BLR (OMAP_UART3_BASE + 0x38)
7361 +#define UART3_ACREG (OMAP_UART3_BASE + 0x3C)
7362 +#define UART3_DIV16 (OMAP_UART3_BASE + 0x3C)
7363 +#define UART3_SCR (OMAP_UART3_BASE + 0x40)
7364 +#define UART3_SSR (OMAP_UART3_BASE + 0x44)
7365 +#define UART3_EBLR (OMAP_UART3_BASE + 0x48)
7366 +#define UART3_OSC_12M_SEL (OMAP_UART3_BASE + 0x4C)
7367 +#define UART3_MVR (OMAP_UART3_BASE + 0x50)
7368 +
7369 +/*
7370 + * ---------------------------------------------------------------------------
7371 + * Watchdog timer
7372 + * ---------------------------------------------------------------------------
7373 + */
7374 +
7375 +/* 32-bit Watchdog timer in OMAP 16XX */
7376 +#define OMAP_16XX_WATCHDOG_BASE (0xfffeb000)
7377 +#define OMAP_16XX_WIDR (OMAP_16XX_WATCHDOG_BASE + 0x00)
7378 +#define OMAP_16XX_WD_SYSCONFIG (OMAP_16XX_WATCHDOG_BASE + 0x10)
7379 +#define OMAP_16XX_WD_SYSSTATUS (OMAP_16XX_WATCHDOG_BASE + 0x14)
7380 +#define OMAP_16XX_WCLR (OMAP_16XX_WATCHDOG_BASE + 0x24)
7381 +#define OMAP_16XX_WCRR (OMAP_16XX_WATCHDOG_BASE + 0x28)
7382 +#define OMAP_16XX_WLDR (OMAP_16XX_WATCHDOG_BASE + 0x2c)
7383 +#define OMAP_16XX_WTGR (OMAP_16XX_WATCHDOG_BASE + 0x30)
7384 +#define OMAP_16XX_WWPS (OMAP_16XX_WATCHDOG_BASE + 0x34)
7385 +#define OMAP_16XX_WSPR (OMAP_16XX_WATCHDOG_BASE + 0x48)
7386 +
7387 +#define WCLR_PRE_SHIFT 5
7388 +#define WCLR_PTV_SHIFT 2
7389 +
7390 +#define WWPS_W_PEND_WSPR (1 << 4)
7391 +#define WWPS_W_PEND_WTGR (1 << 3)
7392 +#define WWPS_W_PEND_WLDR (1 << 2)
7393 +#define WWPS_W_PEND_WCRR (1 << 1)
7394 +#define WWPS_W_PEND_WCLR (1 << 0)
7395 +
7396 +#define WSPR_ENABLE_0 (0x0000bbbb)
7397 +#define WSPR_ENABLE_1 (0x00004444)
7398 +#define WSPR_DISABLE_0 (0x0000aaaa)
7399 +#define WSPR_DISABLE_1 (0x00005555)
7400 +
7401 +#define OMAP16XX_DSP_MMU_BASE (0xfffed200)
7402 +#define OMAP16XX_MAILBOX_BASE (0xfffcf000)
7403 +
7404 +#endif /* __ASM_ARCH_OMAP16XX_H */
7405 +
7406 Index: linux-2.6.35/arch/arm/plat-omap/include/mach/omap24xx.h
7407 ===================================================================
7408 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
7409 +++ linux-2.6.35/arch/arm/plat-omap/include/mach/omap24xx.h 2010-08-08 12:57:06.000000000 +0200
7410 @@ -0,0 +1,89 @@
7411 +/*
7412 + * arch/arm/plat-omap/include/mach/omap24xx.h
7413 + *
7414 + * This file contains the processor specific definitions
7415 + * of the TI OMAP24XX.
7416 + *
7417 + * Copyright (C) 2007 Texas Instruments.
7418 + * Copyright (C) 2007 Nokia Corporation.
7419 + *
7420 + * This program is free software; you can redistribute it and/or modify
7421 + * it under the terms of the GNU General Public License as published by
7422 + * the Free Software Foundation; either version 2 of the License, or
7423 + * (at your option) any later version.
7424 + *
7425 + * This program is distributed in the hope that it will be useful,
7426 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
7427 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
7428 + * GNU General Public License for more details.
7429 + *
7430 + * You should have received a copy of the GNU General Public License
7431 + * along with this program; if not, write to the Free Software
7432 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
7433 + *
7434 + */
7435 +
7436 +#ifndef __ASM_ARCH_OMAP24XX_H
7437 +#define __ASM_ARCH_OMAP24XX_H
7438 +
7439 +/*
7440 + * Please place only base defines here and put the rest in device
7441 + * specific headers. Note also that some of these defines are needed
7442 + * for omap1 to compile without adding ifdefs.
7443 + */
7444 +
7445 +#define L4_24XX_BASE 0x48000000
7446 +#define L4_WK_243X_BASE 0x49000000
7447 +#define L3_24XX_BASE 0x68000000
7448 +
7449 +/* interrupt controller */
7450 +#define OMAP24XX_IC_BASE (L4_24XX_BASE + 0xfe000)
7451 +#define OMAP24XX_IVA_INTC_BASE 0x40000000
7452 +
7453 +#define OMAP2420_CTRL_BASE L4_24XX_BASE
7454 +#define OMAP2420_32KSYNCT_BASE (L4_24XX_BASE + 0x4000)
7455 +#define OMAP2420_PRCM_BASE (L4_24XX_BASE + 0x8000)
7456 +#define OMAP2420_CM_BASE (L4_24XX_BASE + 0x8000)
7457 +#define OMAP2420_PRM_BASE OMAP2420_CM_BASE
7458 +#define OMAP2420_SDRC_BASE (L3_24XX_BASE + 0x9000)
7459 +#define OMAP2420_SMS_BASE 0x68008000
7460 +#define OMAP2420_GPMC_BASE 0x6800a000
7461 +
7462 +#define OMAP2430_32KSYNCT_BASE (L4_WK_243X_BASE + 0x20000)
7463 +#define OMAP2430_PRCM_BASE (L4_WK_243X_BASE + 0x6000)
7464 +#define OMAP2430_CM_BASE (L4_WK_243X_BASE + 0x6000)
7465 +#define OMAP2430_PRM_BASE OMAP2430_CM_BASE
7466 +
7467 +#define OMAP243X_SMS_BASE 0x6C000000
7468 +#define OMAP243X_SDRC_BASE 0x6D000000
7469 +#define OMAP243X_GPMC_BASE 0x6E000000
7470 +#define OMAP243X_SCM_BASE (L4_WK_243X_BASE + 0x2000)
7471 +#define OMAP243X_CTRL_BASE OMAP243X_SCM_BASE
7472 +#define OMAP243X_HS_BASE (L4_24XX_BASE + 0x000ac000)
7473 +
7474 +/* DSP SS */
7475 +#define OMAP2420_DSP_BASE 0x58000000
7476 +#define OMAP2420_DSP_MEM_BASE (OMAP2420_DSP_BASE + 0x0)
7477 +#define OMAP2420_DSP_IPI_BASE (OMAP2420_DSP_BASE + 0x1000000)
7478 +#define OMAP2420_DSP_MMU_BASE (OMAP2420_DSP_BASE + 0x2000000)
7479 +
7480 +#define OMAP243X_DSP_BASE 0x5C000000
7481 +#define OMAP243X_DSP_MEM_BASE (OMAP243X_DSP_BASE + 0x0)
7482 +#define OMAP243X_DSP_MMU_BASE (OMAP243X_DSP_BASE + 0x1000000)
7483 +
7484 +/* Mailbox */
7485 +#define OMAP24XX_MAILBOX_BASE (L4_24XX_BASE + 0x94000)
7486 +
7487 +/* Camera */
7488 +#define OMAP24XX_CAMERA_BASE (L4_24XX_BASE + 0x52000)
7489 +
7490 +/* Security */
7491 +#define OMAP24XX_SEC_BASE (L4_24XX_BASE + 0xA0000)
7492 +#define OMAP24XX_SEC_RNG_BASE (OMAP24XX_SEC_BASE + 0x0000)
7493 +#define OMAP24XX_SEC_DES_BASE (OMAP24XX_SEC_BASE + 0x2000)
7494 +#define OMAP24XX_SEC_SHA1MD5_BASE (OMAP24XX_SEC_BASE + 0x4000)
7495 +#define OMAP24XX_SEC_AES_BASE (OMAP24XX_SEC_BASE + 0x6000)
7496 +#define OMAP24XX_SEC_PKA_BASE (OMAP24XX_SEC_BASE + 0x8000)
7497 +
7498 +#endif /* __ASM_ARCH_OMAP24XX_H */
7499 +
7500 Index: linux-2.6.35/arch/arm/plat-omap/include/mach/omap34xx.h
7501 ===================================================================
7502 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
7503 +++ linux-2.6.35/arch/arm/plat-omap/include/mach/omap34xx.h 2010-08-08 12:57:07.000000000 +0200
7504 @@ -0,0 +1,86 @@
7505 +/*
7506 + * arch/arm/plat-omap/include/mach/omap34xx.h
7507 + *
7508 + * This file contains the processor specific definitions of the TI OMAP34XX.
7509 + *
7510 + * Copyright (C) 2007 Texas Instruments.
7511 + * Copyright (C) 2007 Nokia Corporation.
7512 + *
7513 + * This program is free software; you can redistribute it and/or modify
7514 + * it under the terms of the GNU General Public License as published by
7515 + * the Free Software Foundation; either version 2 of the License, or
7516 + * (at your option) any later version.
7517 + *
7518 + * This program is distributed in the hope that it will be useful,
7519 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
7520 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
7521 + * GNU General Public License for more details.
7522 + *
7523 + * You should have received a copy of the GNU General Public License
7524 + * along with this program; if not, write to the Free Software
7525 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
7526 + */
7527 +
7528 +#ifndef __ASM_ARCH_OMAP34XX_H
7529 +#define __ASM_ARCH_OMAP34XX_H
7530 +
7531 +/*
7532 + * Please place only base defines here and put the rest in device
7533 + * specific headers.
7534 + */
7535 +
7536 +#define L4_34XX_BASE 0x48000000
7537 +#define L4_WK_34XX_BASE 0x48300000
7538 +#define L4_PER_34XX_BASE 0x49000000
7539 +#define L4_EMU_34XX_BASE 0x54000000
7540 +#define L3_34XX_BASE 0x68000000
7541 +
7542 +#define OMAP3430_32KSYNCT_BASE 0x48320000
7543 +#define OMAP3430_CM_BASE 0x48004800
7544 +#define OMAP3430_PRM_BASE 0x48306800
7545 +#define OMAP343X_SMS_BASE 0x6C000000
7546 +#define OMAP343X_SDRC_BASE 0x6D000000
7547 +#define OMAP34XX_GPMC_BASE 0x6E000000
7548 +#define OMAP343X_SCM_BASE 0x48002000
7549 +#define OMAP343X_CTRL_BASE OMAP343X_SCM_BASE
7550 +
7551 +#define OMAP34XX_IC_BASE 0x48200000
7552 +
7553 +#define OMAP3430_ISP_BASE (L4_34XX_BASE + 0xBC000)
7554 +#define OMAP3430_ISP_CBUFF_BASE (OMAP3430_ISP_BASE + 0x0100)
7555 +#define OMAP3430_ISP_CCP2_BASE (OMAP3430_ISP_BASE + 0x0400)
7556 +#define OMAP3430_ISP_CCDC_BASE (OMAP3430_ISP_BASE + 0x0600)
7557 +#define OMAP3430_ISP_HIST_BASE (OMAP3430_ISP_BASE + 0x0A00)
7558 +#define OMAP3430_ISP_H3A_BASE (OMAP3430_ISP_BASE + 0x0C00)
7559 +#define OMAP3430_ISP_PREV_BASE (OMAP3430_ISP_BASE + 0x0E00)
7560 +#define OMAP3430_ISP_RESZ_BASE (OMAP3430_ISP_BASE + 0x1000)
7561 +#define OMAP3430_ISP_SBL_BASE (OMAP3430_ISP_BASE + 0x1200)
7562 +#define OMAP3430_ISP_MMU_BASE (OMAP3430_ISP_BASE + 0x1400)
7563 +#define OMAP3430_ISP_CSI2A_BASE (OMAP3430_ISP_BASE + 0x1800)
7564 +#define OMAP3430_ISP_CSI2PHY_BASE (OMAP3430_ISP_BASE + 0x1970)
7565 +
7566 +#define OMAP3430_ISP_END (OMAP3430_ISP_BASE + 0x06F)
7567 +#define OMAP3430_ISP_CBUFF_END (OMAP3430_ISP_CBUFF_BASE + 0x077)
7568 +#define OMAP3430_ISP_CCP2_END (OMAP3430_ISP_CCP2_BASE + 0x1EF)
7569 +#define OMAP3430_ISP_CCDC_END (OMAP3430_ISP_CCDC_BASE + 0x0A7)
7570 +#define OMAP3430_ISP_HIST_END (OMAP3430_ISP_HIST_BASE + 0x047)
7571 +#define OMAP3430_ISP_H3A_END (OMAP3430_ISP_H3A_BASE + 0x05F)
7572 +#define OMAP3430_ISP_PREV_END (OMAP3430_ISP_PREV_BASE + 0x09F)
7573 +#define OMAP3430_ISP_RESZ_END (OMAP3430_ISP_RESZ_BASE + 0x0AB)
7574 +#define OMAP3430_ISP_SBL_END (OMAP3430_ISP_SBL_BASE + 0x0FB)
7575 +#define OMAP3430_ISP_MMU_END (OMAP3430_ISP_MMU_BASE + 0x06F)
7576 +#define OMAP3430_ISP_CSI2A_END (OMAP3430_ISP_CSI2A_BASE + 0x16F)
7577 +#define OMAP3430_ISP_CSI2PHY_END (OMAP3430_ISP_CSI2PHY_BASE + 0x007)
7578 +
7579 +#define OMAP34XX_HSUSB_OTG_BASE (L4_34XX_BASE + 0xAB000)
7580 +#define OMAP34XX_USBTLL_BASE (L4_34XX_BASE + 0x62000)
7581 +#define OMAP34XX_UHH_CONFIG_BASE (L4_34XX_BASE + 0x64000)
7582 +#define OMAP34XX_OHCI_BASE (L4_34XX_BASE + 0x64400)
7583 +#define OMAP34XX_EHCI_BASE (L4_34XX_BASE + 0x64800)
7584 +#define OMAP34XX_SR1_BASE 0x480C9000
7585 +#define OMAP34XX_SR2_BASE 0x480CB000
7586 +
7587 +#define OMAP34XX_MAILBOX_BASE (L4_34XX_BASE + 0x94000)
7588 +
7589 +#endif /* __ASM_ARCH_OMAP34XX_H */
7590 +
7591 Index: linux-2.6.35/arch/arm/plat-omap/include/mach/omap44xx.h
7592 ===================================================================
7593 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
7594 +++ linux-2.6.35/arch/arm/plat-omap/include/mach/omap44xx.h 2010-08-08 12:57:07.000000000 +0200
7595 @@ -0,0 +1,48 @@
7596 +/*:
7597 + * Address mappings and base address for OMAP4 interconnects
7598 + * and peripherals.
7599 + *
7600 + * Copyright (C) 2009 Texas Instruments
7601 + *
7602 + * Author: Santosh Shilimkar <santosh.shilimkar@ti.com>
7603 + *
7604 + * This program is free software; you can redistribute it and/or modify
7605 + * it under the terms of the GNU General Public License version 2 as
7606 + * published by the Free Software Foundation.
7607 + */
7608 +#ifndef __ASM_ARCH_OMAP44XX_H
7609 +#define __ASM_ARCH_OMAP44XX_H
7610 +
7611 +/*
7612 + * Please place only base defines here and put the rest in device
7613 + * specific headers.
7614 + */
7615 +#define L4_44XX_BASE 0x4a000000
7616 +#define L4_WK_44XX_BASE 0x4a300000
7617 +#define L4_PER_44XX_BASE 0x48000000
7618 +#define L4_EMU_44XX_BASE 0x54000000
7619 +#define L3_44XX_BASE 0x44000000
7620 +#define OMAP44XX_EMIF1_BASE 0x4c000000
7621 +#define OMAP44XX_EMIF2_BASE 0x4d000000
7622 +#define OMAP44XX_DMM_BASE 0x4e000000
7623 +#define OMAP4430_32KSYNCT_BASE 0x4a304000
7624 +#define OMAP4430_CM1_BASE 0x4a004000
7625 +#define OMAP4430_CM_BASE OMAP4430_CM1_BASE
7626 +#define OMAP4430_CM2_BASE 0x4a008000
7627 +#define OMAP4430_PRM_BASE 0x4a306000
7628 +#define OMAP44XX_GPMC_BASE 0x50000000
7629 +#define OMAP443X_SCM_BASE 0x4a002000
7630 +#define OMAP443X_CTRL_BASE OMAP443X_SCM_BASE
7631 +#define OMAP44XX_IC_BASE 0x48200000
7632 +#define OMAP44XX_IVA_INTC_BASE 0x40000000
7633 +#define IRQ_SIR_IRQ 0x0040
7634 +#define OMAP44XX_GIC_DIST_BASE 0x48241000
7635 +#define OMAP44XX_GIC_CPU_BASE 0x48240100
7636 +#define OMAP44XX_SCU_BASE 0x48240000
7637 +#define OMAP44XX_LOCAL_TWD_BASE 0x48240600
7638 +#define OMAP44XX_WKUPGEN_BASE 0x48281000
7639 +
7640 +#define OMAP44XX_MAILBOX_BASE (L4_44XX_BASE + 0xF4000)
7641 +
7642 +#endif /* __ASM_ARCH_OMAP44XX_H */
7643 +
7644 Index: linux-2.6.35/arch/arm/plat-omap/include/mach/omap730.h
7645 ===================================================================
7646 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
7647 +++ linux-2.6.35/arch/arm/plat-omap/include/mach/omap730.h 2010-08-08 12:57:08.000000000 +0200
7648 @@ -0,0 +1,102 @@
7649 +/* arch/arm/plat-omap/include/mach/omap730.h
7650 + *
7651 + * Hardware definitions for TI OMAP730 processor.
7652 + *
7653 + * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com>
7654 + *
7655 + * This program is free software; you can redistribute it and/or modify it
7656 + * under the terms of the GNU General Public License as published by the
7657 + * Free Software Foundation; either version 2 of the License, or (at your
7658 + * option) any later version.
7659 + *
7660 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
7661 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
7662 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
7663 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
7664 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
7665 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
7666 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
7667 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
7668 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
7669 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
7670 + *
7671 + * You should have received a copy of the GNU General Public License along
7672 + * with this program; if not, write to the Free Software Foundation, Inc.,
7673 + * 675 Mass Ave, Cambridge, MA 02139, USA.
7674 + */
7675 +
7676 +#ifndef __ASM_ARCH_OMAP730_H
7677 +#define __ASM_ARCH_OMAP730_H
7678 +
7679 +/*
7680 + * ----------------------------------------------------------------------------
7681 + * Base addresses
7682 + * ----------------------------------------------------------------------------
7683 + */
7684 +
7685 +/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
7686 +
7687 +#define OMAP730_DSP_BASE 0xE0000000
7688 +#define OMAP730_DSP_SIZE 0x50000
7689 +#define OMAP730_DSP_START 0xE0000000
7690 +
7691 +#define OMAP730_DSPREG_BASE 0xE1000000
7692 +#define OMAP730_DSPREG_SIZE SZ_128K
7693 +#define OMAP730_DSPREG_START 0xE1000000
7694 +
7695 +/*
7696 + * ----------------------------------------------------------------------------
7697 + * OMAP730 specific configuration registers
7698 + * ----------------------------------------------------------------------------
7699 + */
7700 +#define OMAP730_CONFIG_BASE 0xfffe1000
7701 +#define OMAP730_IO_CONF_0 0xfffe1070
7702 +#define OMAP730_IO_CONF_1 0xfffe1074
7703 +#define OMAP730_IO_CONF_2 0xfffe1078
7704 +#define OMAP730_IO_CONF_3 0xfffe107c
7705 +#define OMAP730_IO_CONF_4 0xfffe1080
7706 +#define OMAP730_IO_CONF_5 0xfffe1084
7707 +#define OMAP730_IO_CONF_6 0xfffe1088
7708 +#define OMAP730_IO_CONF_7 0xfffe108c
7709 +#define OMAP730_IO_CONF_8 0xfffe1090
7710 +#define OMAP730_IO_CONF_9 0xfffe1094
7711 +#define OMAP730_IO_CONF_10 0xfffe1098
7712 +#define OMAP730_IO_CONF_11 0xfffe109c
7713 +#define OMAP730_IO_CONF_12 0xfffe10a0
7714 +#define OMAP730_IO_CONF_13 0xfffe10a4
7715 +
7716 +#define OMAP730_MODE_1 0xfffe1010
7717 +#define OMAP730_MODE_2 0xfffe1014
7718 +
7719 +/* CSMI specials: in terms of base + offset */
7720 +#define OMAP730_MODE2_OFFSET 0x14
7721 +
7722 +/*
7723 + * ----------------------------------------------------------------------------
7724 + * OMAP730 traffic controller configuration registers
7725 + * ----------------------------------------------------------------------------
7726 + */
7727 +#define OMAP730_FLASH_CFG_0 0xfffecc10
7728 +#define OMAP730_FLASH_ACFG_0 0xfffecc50
7729 +#define OMAP730_FLASH_CFG_1 0xfffecc14
7730 +#define OMAP730_FLASH_ACFG_1 0xfffecc54
7731 +
7732 +/*
7733 + * ----------------------------------------------------------------------------
7734 + * OMAP730 DSP control registers
7735 + * ----------------------------------------------------------------------------
7736 + */
7737 +#define OMAP730_ICR_BASE 0xfffbb800
7738 +#define OMAP730_DSP_M_CTL 0xfffbb804
7739 +#define OMAP730_DSP_MMU_BASE 0xfffed200
7740 +
7741 +/*
7742 + * ----------------------------------------------------------------------------
7743 + * OMAP730 PCC_UPLD configuration registers
7744 + * ----------------------------------------------------------------------------
7745 + */
7746 +#define OMAP730_PCC_UPLD_CTRL_BASE (0xfffe0900)
7747 +#define OMAP730_PCC_UPLD_CTRL (OMAP730_PCC_UPLD_CTRL_BASE + 0x00)
7748 +
7749 +#endif /* __ASM_ARCH_OMAP730_H */
7750 +
7751 Index: linux-2.6.35/arch/arm/plat-omap/include/mach/omap7xx.h
7752 ===================================================================
7753 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
7754 +++ linux-2.6.35/arch/arm/plat-omap/include/mach/omap7xx.h 2010-08-08 12:57:09.000000000 +0200
7755 @@ -0,0 +1,104 @@
7756 +/* arch/arm/plat-omap/include/mach/omap7xx.h
7757 + *
7758 + * Hardware definitions for TI OMAP7XX processor.
7759 + *
7760 + * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com>
7761 + * Adapted for omap850 by Zebediah C. McClure <zmc@lurian.net>
7762 + * Adapted for omap7xx by Alistair Buxton <a.j.buxton@gmail.com>
7763 + *
7764 + * This program is free software; you can redistribute it and/or modify it
7765 + * under the terms of the GNU General Public License as published by the
7766 + * Free Software Foundation; either version 2 of the License, or (at your
7767 + * option) any later version.
7768 + *
7769 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
7770 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
7771 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
7772 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
7773 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
7774 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
7775 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
7776 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
7777 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
7778 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
7779 + *
7780 + * You should have received a copy of the GNU General Public License along
7781 + * with this program; if not, write to the Free Software Foundation, Inc.,
7782 + * 675 Mass Ave, Cambridge, MA 02139, USA.
7783 + */
7784 +
7785 +#ifndef __ASM_ARCH_OMAP7XX_H
7786 +#define __ASM_ARCH_OMAP7XX_H
7787 +
7788 +/*
7789 + * ----------------------------------------------------------------------------
7790 + * Base addresses
7791 + * ----------------------------------------------------------------------------
7792 + */
7793 +
7794 +/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
7795 +
7796 +#define OMAP7XX_DSP_BASE 0xE0000000
7797 +#define OMAP7XX_DSP_SIZE 0x50000
7798 +#define OMAP7XX_DSP_START 0xE0000000
7799 +
7800 +#define OMAP7XX_DSPREG_BASE 0xE1000000
7801 +#define OMAP7XX_DSPREG_SIZE SZ_128K
7802 +#define OMAP7XX_DSPREG_START 0xE1000000
7803 +
7804 +/*
7805 + * ----------------------------------------------------------------------------
7806 + * OMAP7XX specific configuration registers
7807 + * ----------------------------------------------------------------------------
7808 + */
7809 +#define OMAP7XX_CONFIG_BASE 0xfffe1000
7810 +#define OMAP7XX_IO_CONF_0 0xfffe1070
7811 +#define OMAP7XX_IO_CONF_1 0xfffe1074
7812 +#define OMAP7XX_IO_CONF_2 0xfffe1078
7813 +#define OMAP7XX_IO_CONF_3 0xfffe107c
7814 +#define OMAP7XX_IO_CONF_4 0xfffe1080
7815 +#define OMAP7XX_IO_CONF_5 0xfffe1084
7816 +#define OMAP7XX_IO_CONF_6 0xfffe1088
7817 +#define OMAP7XX_IO_CONF_7 0xfffe108c
7818 +#define OMAP7XX_IO_CONF_8 0xfffe1090
7819 +#define OMAP7XX_IO_CONF_9 0xfffe1094
7820 +#define OMAP7XX_IO_CONF_10 0xfffe1098
7821 +#define OMAP7XX_IO_CONF_11 0xfffe109c
7822 +#define OMAP7XX_IO_CONF_12 0xfffe10a0
7823 +#define OMAP7XX_IO_CONF_13 0xfffe10a4
7824 +
7825 +#define OMAP7XX_MODE_1 0xfffe1010
7826 +#define OMAP7XX_MODE_2 0xfffe1014
7827 +
7828 +/* CSMI specials: in terms of base + offset */
7829 +#define OMAP7XX_MODE2_OFFSET 0x14
7830 +
7831 +/*
7832 + * ----------------------------------------------------------------------------
7833 + * OMAP7XX traffic controller configuration registers
7834 + * ----------------------------------------------------------------------------
7835 + */
7836 +#define OMAP7XX_FLASH_CFG_0 0xfffecc10
7837 +#define OMAP7XX_FLASH_ACFG_0 0xfffecc50
7838 +#define OMAP7XX_FLASH_CFG_1 0xfffecc14
7839 +#define OMAP7XX_FLASH_ACFG_1 0xfffecc54
7840 +
7841 +/*
7842 + * ----------------------------------------------------------------------------
7843 + * OMAP7XX DSP control registers
7844 + * ----------------------------------------------------------------------------
7845 + */
7846 +#define OMAP7XX_ICR_BASE 0xfffbb800
7847 +#define OMAP7XX_DSP_M_CTL 0xfffbb804
7848 +#define OMAP7XX_DSP_MMU_BASE 0xfffed200
7849 +
7850 +/*
7851 + * ----------------------------------------------------------------------------
7852 + * OMAP7XX PCC_UPLD configuration registers
7853 + * ----------------------------------------------------------------------------
7854 + */
7855 +#define OMAP7XX_PCC_UPLD_CTRL_BASE (0xfffe0900)
7856 +#define OMAP7XX_PCC_UPLD_CTRL (OMAP7XX_PCC_UPLD_CTRL_BASE + 0x00)
7857 +
7858 +#endif /* __ASM_ARCH_OMAP7XX_H */
7859 +
7860 Index: linux-2.6.35/arch/arm/plat-omap/include/mach/omap850.h
7861 ===================================================================
7862 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
7863 +++ linux-2.6.35/arch/arm/plat-omap/include/mach/omap850.h 2010-08-08 12:57:09.000000000 +0200
7864 @@ -0,0 +1,102 @@
7865 +/* arch/arm/plat-omap/include/mach/omap850.h
7866 + *
7867 + * Hardware definitions for TI OMAP850 processor.
7868 + *
7869 + * Derived from omap730.h by Zebediah C. McClure <zmc@lurian.net>
7870 + *
7871 + * This program is free software; you can redistribute it and/or modify it
7872 + * under the terms of the GNU General Public License as published by the
7873 + * Free Software Foundation; either version 2 of the License, or (at your
7874 + * option) any later version.
7875 + *
7876 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
7877 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
7878 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
7879 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
7880 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
7881 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
7882 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
7883 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
7884 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
7885 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
7886 + *
7887 + * You should have received a copy of the GNU General Public License along
7888 + * with this program; if not, write to the Free Software Foundation, Inc.,
7889 + * 675 Mass Ave, Cambridge, MA 02139, USA.
7890 + */
7891 +
7892 +#ifndef __ASM_ARCH_OMAP850_H
7893 +#define __ASM_ARCH_OMAP850_H
7894 +
7895 +/*
7896 + * ----------------------------------------------------------------------------
7897 + * Base addresses
7898 + * ----------------------------------------------------------------------------
7899 + */
7900 +
7901 +/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
7902 +
7903 +#define OMAP850_DSP_BASE 0xE0000000
7904 +#define OMAP850_DSP_SIZE 0x50000
7905 +#define OMAP850_DSP_START 0xE0000000
7906 +
7907 +#define OMAP850_DSPREG_BASE 0xE1000000
7908 +#define OMAP850_DSPREG_SIZE SZ_128K
7909 +#define OMAP850_DSPREG_START 0xE1000000
7910 +
7911 +/*
7912 + * ----------------------------------------------------------------------------
7913 + * OMAP850 specific configuration registers
7914 + * ----------------------------------------------------------------------------
7915 + */
7916 +#define OMAP850_CONFIG_BASE 0xfffe1000
7917 +#define OMAP850_IO_CONF_0 0xfffe1070
7918 +#define OMAP850_IO_CONF_1 0xfffe1074
7919 +#define OMAP850_IO_CONF_2 0xfffe1078
7920 +#define OMAP850_IO_CONF_3 0xfffe107c
7921 +#define OMAP850_IO_CONF_4 0xfffe1080
7922 +#define OMAP850_IO_CONF_5 0xfffe1084
7923 +#define OMAP850_IO_CONF_6 0xfffe1088
7924 +#define OMAP850_IO_CONF_7 0xfffe108c
7925 +#define OMAP850_IO_CONF_8 0xfffe1090
7926 +#define OMAP850_IO_CONF_9 0xfffe1094
7927 +#define OMAP850_IO_CONF_10 0xfffe1098
7928 +#define OMAP850_IO_CONF_11 0xfffe109c
7929 +#define OMAP850_IO_CONF_12 0xfffe10a0
7930 +#define OMAP850_IO_CONF_13 0xfffe10a4
7931 +
7932 +#define OMAP850_MODE_1 0xfffe1010
7933 +#define OMAP850_MODE_2 0xfffe1014
7934 +
7935 +/* CSMI specials: in terms of base + offset */
7936 +#define OMAP850_MODE2_OFFSET 0x14
7937 +
7938 +/*
7939 + * ----------------------------------------------------------------------------
7940 + * OMAP850 traffic controller configuration registers
7941 + * ----------------------------------------------------------------------------
7942 + */
7943 +#define OMAP850_FLASH_CFG_0 0xfffecc10
7944 +#define OMAP850_FLASH_ACFG_0 0xfffecc50
7945 +#define OMAP850_FLASH_CFG_1 0xfffecc14
7946 +#define OMAP850_FLASH_ACFG_1 0xfffecc54
7947 +
7948 +/*
7949 + * ----------------------------------------------------------------------------
7950 + * OMAP850 DSP control registers
7951 + * ----------------------------------------------------------------------------
7952 + */
7953 +#define OMAP850_ICR_BASE 0xfffbb800
7954 +#define OMAP850_DSP_M_CTL 0xfffbb804
7955 +#define OMAP850_DSP_MMU_BASE 0xfffed200
7956 +
7957 +/*
7958 + * ----------------------------------------------------------------------------
7959 + * OMAP850 PCC_UPLD configuration registers
7960 + * ----------------------------------------------------------------------------
7961 + */
7962 +#define OMAP850_PCC_UPLD_CTRL_BASE (0xfffe0900)
7963 +#define OMAP850_PCC_UPLD_CTRL (OMAP850_PCC_UPLD_CTRL_BASE + 0x00)
7964 +
7965 +#endif /* __ASM_ARCH_OMAP850_H */
7966 +
7967 Index: linux-2.6.35/arch/arm/plat-omap/include/mach/omap-alsa.h
7968 ===================================================================
7969 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
7970 +++ linux-2.6.35/arch/arm/plat-omap/include/mach/omap-alsa.h 2010-08-08 12:57:10.000000000 +0200
7971 @@ -0,0 +1,123 @@
7972 +/*
7973 + * arch/arm/plat-omap/include/mach/omap-alsa.h
7974 + *
7975 + * Alsa Driver for AIC23 and TSC2101 codecs on OMAP platform boards.
7976 + *
7977 + * Copyright (C) 2006 Mika Laitio <lamikr@cc.jyu.fi>
7978 + *
7979 + * Copyright (C) 2005 Instituto Nokia de Tecnologia - INdT - Manaus Brazil
7980 + * Written by Daniel Petrini, David Cohen, Anderson Briglia
7981 + * {daniel.petrini, david.cohen, anderson.briglia}@indt.org.br
7982 + *
7983 + * This program is free software; you can redistribute it and/or modify it
7984 + * under the terms of the GNU General Public License as published by the
7985 + * Free Software Foundation; either version 2 of the License, or (at your
7986 + * option) any later version.
7987 + *
7988 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
7989 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
7990 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
7991 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
7992 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
7993 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
7994 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
7995 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
7996 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
7997 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
7998 + *
7999 + * You should have received a copy of the GNU General Public License along
8000 + * with this program; if not, write to the Free Software Foundation, Inc.,
8001 + * 675 Mass Ave, Cambridge, MA 02139, USA.
8002 + *
8003 + * History
8004 + * -------
8005 + *
8006 + * 2005/07/25 INdT-10LE Kernel Team - Alsa driver for omap osk,
8007 + * original version based in sa1100 driver
8008 + * and omap oss driver.
8009 + */
8010 +
8011 +#ifndef __OMAP_ALSA_H
8012 +#define __OMAP_ALSA_H
8013 +
8014 +#include <plat/dma.h>
8015 +#include <sound/core.h>
8016 +#include <sound/pcm.h>
8017 +#include <plat/mcbsp.h>
8018 +#include <linux/platform_device.h>
8019 +
8020 +#define DMA_BUF_SIZE (1024 * 8)
8021 +
8022 +/*
8023 + * Buffer management for alsa and dma
8024 + */
8025 +struct audio_stream {
8026 + char *id; /* identification string */
8027 + int stream_id; /* numeric identification */
8028 + int dma_dev; /* dma number of that device */
8029 + int *lch; /* Chain of channels this stream is linked to */
8030 + char started; /* to store if the chain was started or not */
8031 + int dma_q_head; /* DMA Channel Q Head */
8032 + int dma_q_tail; /* DMA Channel Q Tail */
8033 + char dma_q_count; /* DMA Channel Q Count */
8034 + int active:1; /* we are using this stream for transfer now */
8035 + int period; /* current transfer period */
8036 + int periods; /* current count of periods registerd in the DMA engine */
8037 + spinlock_t dma_lock; /* for locking in DMA operations */
8038 + struct snd_pcm_substream *stream; /* the pcm stream */
8039 + unsigned linked:1; /* dma channels linked */
8040 + int offset; /* store start position of the last period in the alsa buffer */
8041 + int (*hw_start)(void); /* interface to start HW interface, e.g. McBSP */
8042 + int (*hw_stop)(void); /* interface to stop HW interface, e.g. McBSP */
8043 +};
8044 +
8045 +/*
8046 + * Alsa card structure for aic23
8047 + */
8048 +struct snd_card_omap_codec {
8049 + struct snd_card *card;
8050 + struct snd_pcm *pcm;
8051 + long samplerate;
8052 + struct audio_stream s[2]; /* playback & capture */
8053 +};
8054 +
8055 +/* Codec specific information and function pointers.
8056 + * Codec (omap-alsa-aic23.c and omap-alsa-tsc2101.c)
8057 + * are responsible for defining the function pointers.
8058 + */
8059 +struct omap_alsa_codec_config {
8060 + char *name;
8061 + struct omap_mcbsp_reg_cfg *mcbsp_regs_alsa;
8062 + struct snd_pcm_hw_constraint_list *hw_constraints_rates;
8063 + struct snd_pcm_hardware *snd_omap_alsa_playback;
8064 + struct snd_pcm_hardware *snd_omap_alsa_capture;
8065 + void (*codec_configure_dev)(void);
8066 + void (*codec_set_samplerate)(long);
8067 + void (*codec_clock_setup)(void);
8068 + int (*codec_clock_on)(void);
8069 + int (*codec_clock_off)(void);
8070 + int (*get_default_samplerate)(void);
8071 +};
8072 +
8073 +/*********** Mixer function prototypes *************************/
8074 +int snd_omap_mixer(struct snd_card_omap_codec *);
8075 +void snd_omap_init_mixer(void);
8076 +
8077 +#ifdef CONFIG_PM
8078 +void snd_omap_suspend_mixer(void);
8079 +void snd_omap_resume_mixer(void);
8080 +#endif
8081 +
8082 +int snd_omap_alsa_post_probe(struct platform_device *pdev, struct omap_alsa_codec_config *config);
8083 +int snd_omap_alsa_remove(struct platform_device *pdev);
8084 +#ifdef CONFIG_PM
8085 +int snd_omap_alsa_suspend(struct platform_device *pdev, pm_message_t state);
8086 +int snd_omap_alsa_resume(struct platform_device *pdev);
8087 +#else
8088 +#define snd_omap_alsa_suspend NULL
8089 +#define snd_omap_alsa_resume NULL
8090 +#endif
8091 +
8092 +void callback_omap_alsa_sound_dma(void *);
8093 +
8094 +#endif
8095 Index: linux-2.6.35/arch/arm/plat-omap/include/mach/omap_device.h
8096 ===================================================================
8097 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
8098 +++ linux-2.6.35/arch/arm/plat-omap/include/mach/omap_device.h 2010-08-08 12:57:10.000000000 +0200
8099 @@ -0,0 +1,143 @@
8100 +/*
8101 + * omap_device headers
8102 + *
8103 + * Copyright (C) 2009 Nokia Corporation
8104 + * Paul Walmsley
8105 + *
8106 + * Developed in collaboration with (alphabetical order): Benoit
8107 + * Cousson, Kevin Hilman, Tony Lindgren, Rajendra Nayak, Vikram
8108 + * Pandita, Sakari Poussa, Anand Sawant, Santosh Shilimkar, Richard
8109 + * Woodruff
8110 + *
8111 + * This program is free software; you can redistribute it and/or modify
8112 + * it under the terms of the GNU General Public License version 2 as
8113 + * published by the Free Software Foundation.
8114 + *
8115 + * Eventually this type of functionality should either be
8116 + * a) implemented via arch-specific pointers in platform_device
8117 + * or
8118 + * b) implemented as a proper omap_bus/omap_device in Linux, no more
8119 + * platform_device
8120 + *
8121 + * omap_device differs from omap_hwmod in that it includes external
8122 + * (e.g., board- and system-level) integration details. omap_hwmod
8123 + * stores hardware data that is invariant for a given OMAP chip.
8124 + *
8125 + * To do:
8126 + * - GPIO integration
8127 + * - regulator integration
8128 + *
8129 + */
8130 +#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_DEVICE_H
8131 +#define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_DEVICE_H
8132 +
8133 +#include <linux/kernel.h>
8134 +#include <linux/platform_device.h>
8135 +
8136 +#include <plat/omap_hwmod.h>
8137 +
8138 +/* omap_device._state values */
8139 +#define OMAP_DEVICE_STATE_UNKNOWN 0
8140 +#define OMAP_DEVICE_STATE_ENABLED 1
8141 +#define OMAP_DEVICE_STATE_IDLE 2
8142 +#define OMAP_DEVICE_STATE_SHUTDOWN 3
8143 +
8144 +/**
8145 + * struct omap_device - omap_device wrapper for platform_devices
8146 + * @pdev: platform_device
8147 + * @hwmods: (one .. many per omap_device)
8148 + * @hwmods_cnt: ARRAY_SIZE() of @hwmods
8149 + * @pm_lats: ptr to an omap_device_pm_latency table
8150 + * @pm_lats_cnt: ARRAY_SIZE() of what is passed to @pm_lats
8151 + * @pm_lat_level: array index of the last odpl entry executed - -1 if never
8152 + * @dev_wakeup_lat: dev wakeup latency in nanoseconds
8153 + * @_dev_wakeup_lat_limit: dev wakeup latency limit in nsec - set by OMAP PM
8154 + * @_state: one of OMAP_DEVICE_STATE_* (see above)
8155 + * @flags: device flags
8156 + *
8157 + * Integrates omap_hwmod data into Linux platform_device.
8158 + *
8159 + * Field names beginning with underscores are for the internal use of
8160 + * the omap_device code.
8161 + *
8162 + */
8163 +struct omap_device {
8164 + struct platform_device pdev;
8165 + struct omap_hwmod **hwmods;
8166 + struct omap_device_pm_latency *pm_lats;
8167 + u32 dev_wakeup_lat;
8168 + u32 _dev_wakeup_lat_limit;
8169 + u8 pm_lats_cnt;
8170 + s8 pm_lat_level;
8171 + u8 hwmods_cnt;
8172 + u8 _state;
8173 +};
8174 +
8175 +/* Device driver interface (call via platform_data fn ptrs) */
8176 +
8177 +int omap_device_enable(struct platform_device *pdev);
8178 +int omap_device_idle(struct platform_device *pdev);
8179 +int omap_device_shutdown(struct platform_device *pdev);
8180 +
8181 +/* Core code interface */
8182 +
8183 +int omap_device_count_resources(struct omap_device *od);
8184 +int omap_device_fill_resources(struct omap_device *od, struct resource *res);
8185 +
8186 +struct omap_device *omap_device_build(const char *pdev_name, int pdev_id,
8187 + struct omap_hwmod *oh, void *pdata,
8188 + int pdata_len,
8189 + struct omap_device_pm_latency *pm_lats,
8190 + int pm_lats_cnt);
8191 +
8192 +struct omap_device *omap_device_build_ss(const char *pdev_name, int pdev_id,
8193 + struct omap_hwmod **oh, int oh_cnt,
8194 + void *pdata, int pdata_len,
8195 + struct omap_device_pm_latency *pm_lats,
8196 + int pm_lats_cnt);
8197 +
8198 +int omap_device_register(struct omap_device *od);
8199 +
8200 +/* OMAP PM interface */
8201 +int omap_device_align_pm_lat(struct platform_device *pdev,
8202 + u32 new_wakeup_lat_limit);
8203 +struct powerdomain *omap_device_get_pwrdm(struct omap_device *od);
8204 +
8205 +/* Other */
8206 +
8207 +int omap_device_idle_hwmods(struct omap_device *od);
8208 +int omap_device_enable_hwmods(struct omap_device *od);
8209 +
8210 +int omap_device_disable_clocks(struct omap_device *od);
8211 +int omap_device_enable_clocks(struct omap_device *od);
8212 +
8213 +
8214 +/*
8215 + * Entries should be kept in latency order ascending
8216 + *
8217 + * deact_lat is the maximum number of microseconds required to complete
8218 + * deactivate_func() at the device's slowest OPP.
8219 + *
8220 + * act_lat is the maximum number of microseconds required to complete
8221 + * activate_func() at the device's slowest OPP.
8222 + *
8223 + * This will result in some suboptimal power management decisions at fast
8224 + * OPPs, but avoids having to recompute all device power management decisions
8225 + * if the system shifts from a fast OPP to a slow OPP (in order to meet
8226 + * latency requirements).
8227 + *
8228 + * XXX should deactivate_func/activate_func() take platform_device pointers
8229 + * rather than omap_device pointers?
8230 + */
8231 +struct omap_device_pm_latency {
8232 + u32 deactivate_lat;
8233 + int (*deactivate_func)(struct omap_device *od);
8234 + u32 activate_lat;
8235 + int (*activate_func)(struct omap_device *od);
8236 +};
8237 +
8238 +
8239 +/* Get omap_device pointer from platform_device pointer */
8240 +#define to_omap_device(x) container_of((x), struct omap_device, pdev)
8241 +
8242 +#endif
8243 Index: linux-2.6.35/arch/arm/plat-omap/include/mach/omap_hwmod.h
8244 ===================================================================
8245 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
8246 +++ linux-2.6.35/arch/arm/plat-omap/include/mach/omap_hwmod.h 2010-08-08 12:57:11.000000000 +0200
8247 @@ -0,0 +1,467 @@
8248 +/*
8249 + * omap_hwmod macros, structures
8250 + *
8251 + * Copyright (C) 2009 Nokia Corporation
8252 + * Paul Walmsley
8253 + *
8254 + * Created in collaboration with (alphabetical order): Benoit Cousson,
8255 + * Kevin Hilman, Tony Lindgren, Rajendra Nayak, Vikram Pandita, Sakari
8256 + * Poussa, Anand Sawant, Santosh Shilimkar, Richard Woodruff
8257 + *
8258 + * This program is free software; you can redistribute it and/or modify
8259 + * it under the terms of the GNU General Public License version 2 as
8260 + * published by the Free Software Foundation.
8261 + *
8262 + * These headers and macros are used to define OMAP on-chip module
8263 + * data and their integration with other OMAP modules and Linux.
8264 + *
8265 + * References:
8266 + * - OMAP2420 Multimedia Processor Silicon Revision 2.1.1, 2.2 (SWPU064)
8267 + * - OMAP2430 Multimedia Device POP Silicon Revision 2.1 (SWPU090)
8268 + * - OMAP34xx Multimedia Device Silicon Revision 3.1 (SWPU108)
8269 + * - OMAP4430 Multimedia Device Silicon Revision 1.0 (SWPU140)
8270 + * - Open Core Protocol Specification 2.2
8271 + *
8272 + * To do:
8273 + * - add interconnect error log structures
8274 + * - add pinmuxing
8275 + * - init_conn_id_bit (CONNID_BIT_VECTOR)
8276 + * - implement default hwmod SMS/SDRC flags?
8277 + *
8278 + */
8279 +#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD_H
8280 +#define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD_H
8281 +
8282 +#include <linux/kernel.h>
8283 +#include <linux/ioport.h>
8284 +
8285 +#include <plat/cpu.h>
8286 +
8287 +struct omap_device;
8288 +
8289 +/* OCP SYSCONFIG bit shifts/masks */
8290 +#define SYSC_MIDLEMODE_SHIFT 12
8291 +#define SYSC_MIDLEMODE_MASK (0x3 << SYSC_MIDLEMODE_SHIFT)
8292 +#define SYSC_CLOCKACTIVITY_SHIFT 8
8293 +#define SYSC_CLOCKACTIVITY_MASK (0x3 << SYSC_CLOCKACTIVITY_SHIFT)
8294 +#define SYSC_SIDLEMODE_SHIFT 3
8295 +#define SYSC_SIDLEMODE_MASK (0x3 << SYSC_SIDLEMODE_SHIFT)
8296 +#define SYSC_ENAWAKEUP_SHIFT 2
8297 +#define SYSC_ENAWAKEUP_MASK (1 << SYSC_ENAWAKEUP_SHIFT)
8298 +#define SYSC_SOFTRESET_SHIFT 1
8299 +#define SYSC_SOFTRESET_MASK (1 << SYSC_SOFTRESET_SHIFT)
8300 +#define SYSC_AUTOIDLE_SHIFT 0
8301 +#define SYSC_AUTOIDLE_MASK (1 << SYSC_AUTOIDLE_SHIFT)
8302 +
8303 +/* OCP SYSSTATUS bit shifts/masks */
8304 +#define SYSS_RESETDONE_SHIFT 0
8305 +#define SYSS_RESETDONE_MASK (1 << SYSS_RESETDONE_SHIFT)
8306 +
8307 +/* Master standby/slave idle mode flags */
8308 +#define HWMOD_IDLEMODE_FORCE (1 << 0)
8309 +#define HWMOD_IDLEMODE_NO (1 << 1)
8310 +#define HWMOD_IDLEMODE_SMART (1 << 2)
8311 +
8312 +
8313 +/**
8314 + * struct omap_hwmod_irq_info - MPU IRQs used by the hwmod
8315 + * @name: name of the IRQ channel (module local name)
8316 + * @irq_ch: IRQ channel ID
8317 + *
8318 + * @name should be something short, e.g., "tx" or "rx". It is for use
8319 + * by platform_get_resource_byname(). It is defined locally to the
8320 + * hwmod.
8321 + */
8322 +struct omap_hwmod_irq_info {
8323 + const char *name;
8324 + u16 irq;
8325 +};
8326 +
8327 +/**
8328 + * struct omap_hwmod_dma_info - DMA channels used by the hwmod
8329 + * @name: name of the DMA channel (module local name)
8330 + * @dma_ch: DMA channel ID
8331 + *
8332 + * @name should be something short, e.g., "tx" or "rx". It is for use
8333 + * by platform_get_resource_byname(). It is defined locally to the
8334 + * hwmod.
8335 + */
8336 +struct omap_hwmod_dma_info {
8337 + const char *name;
8338 + u16 dma_ch;
8339 +};
8340 +
8341 +/**
8342 + * struct omap_hwmod_opt_clk - optional clocks used by this hwmod
8343 + * @role: "sys", "32k", "tv", etc -- for use in clk_get()
8344 + * @clkdev_dev_id: opt clock: clkdev dev_id string
8345 + * @clkdev_con_id: opt clock: clkdev con_id string
8346 + * @_clk: pointer to the struct clk (filled in at runtime)
8347 + *
8348 + * The module's interface clock and main functional clock should not
8349 + * be added as optional clocks.
8350 + */
8351 +struct omap_hwmod_opt_clk {
8352 + const char *role;
8353 + const char *clkdev_dev_id;
8354 + const char *clkdev_con_id;
8355 + struct clk *_clk;
8356 +};
8357 +
8358 +
8359 +/* omap_hwmod_omap2_firewall.flags bits */
8360 +#define OMAP_FIREWALL_L3 (1 << 0)
8361 +#define OMAP_FIREWALL_L4 (1 << 1)
8362 +
8363 +/**
8364 + * struct omap_hwmod_omap2_firewall - OMAP2/3 device firewall data
8365 + * @l3_perm_bit: bit shift for L3_PM_*_PERMISSION_*
8366 + * @l4_fw_region: L4 firewall region ID
8367 + * @l4_prot_group: L4 protection group ID
8368 + * @flags: (see omap_hwmod_omap2_firewall.flags macros above)
8369 + */
8370 +struct omap_hwmod_omap2_firewall {
8371 + u8 l3_perm_bit;
8372 + u8 l4_fw_region;
8373 + u8 l4_prot_group;
8374 + u8 flags;
8375 +};
8376 +
8377 +
8378 +/*
8379 + * omap_hwmod_addr_space.flags bits
8380 + *
8381 + * ADDR_MAP_ON_INIT: Map this address space during omap_hwmod init.
8382 + * ADDR_TYPE_RT: Address space contains module register target data.
8383 + */
8384 +#define ADDR_MAP_ON_INIT (1 << 0)
8385 +#define ADDR_TYPE_RT (1 << 1)
8386 +
8387 +/**
8388 + * struct omap_hwmod_addr_space - MPU address space handled by the hwmod
8389 + * @pa_start: starting physical address
8390 + * @pa_end: ending physical address
8391 + * @flags: (see omap_hwmod_addr_space.flags macros above)
8392 + *
8393 + * Address space doesn't necessarily follow physical interconnect
8394 + * structure. GPMC is one example.
8395 + */
8396 +struct omap_hwmod_addr_space {
8397 + u32 pa_start;
8398 + u32 pa_end;
8399 + u8 flags;
8400 +};
8401 +
8402 +
8403 +/*
8404 + * omap_hwmod_ocp_if.user bits: these indicate the initiators that use this
8405 + * interface to interact with the hwmod. Used to add sleep dependencies
8406 + * when the module is enabled or disabled.
8407 + */
8408 +#define OCP_USER_MPU (1 << 0)
8409 +#define OCP_USER_SDMA (1 << 1)
8410 +
8411 +/* omap_hwmod_ocp_if.flags bits */
8412 +#define OCPIF_HAS_IDLEST (1 << 0)
8413 +#define OCPIF_SWSUP_IDLE (1 << 1)
8414 +#define OCPIF_CAN_BURST (1 << 2)
8415 +
8416 +/**
8417 + * struct omap_hwmod_ocp_if - OCP interface data
8418 + * @master: struct omap_hwmod that initiates OCP transactions on this link
8419 + * @slave: struct omap_hwmod that responds to OCP transactions on this link
8420 + * @addr: address space associated with this link
8421 + * @clkdev_dev_id: interface clock: clkdev dev_id string
8422 + * @clkdev_con_id: interface clock: clkdev con_id string
8423 + * @_clk: pointer to the interface struct clk (filled in at runtime)
8424 + * @fw: interface firewall data
8425 + * @addr_cnt: ARRAY_SIZE(@addr)
8426 + * @width: OCP data width
8427 + * @thread_cnt: number of threads
8428 + * @max_burst_len: maximum burst length in @width sized words (0 if unlimited)
8429 + * @user: initiators using this interface (see OCP_USER_* macros above)
8430 + * @flags: OCP interface flags (see OCPIF_* macros above)
8431 + *
8432 + * It may also be useful to add a tag_cnt field for OCP2.x devices.
8433 + *
8434 + * Parameter names beginning with an underscore are managed internally by
8435 + * the omap_hwmod code and should not be set during initialization.
8436 + */
8437 +struct omap_hwmod_ocp_if {
8438 + struct omap_hwmod *master;
8439 + struct omap_hwmod *slave;
8440 + struct omap_hwmod_addr_space *addr;
8441 + const char *clkdev_dev_id;
8442 + const char *clkdev_con_id;
8443 + struct clk *_clk;
8444 + union {
8445 + struct omap_hwmod_omap2_firewall omap2;
8446 + } fw;
8447 + u8 addr_cnt;
8448 + u8 width;
8449 + u8 thread_cnt;
8450 + u8 max_burst_len;
8451 + u8 user;
8452 + u8 flags;
8453 +};
8454 +
8455 +
8456 +/* Macros for use in struct omap_hwmod_sysconfig */
8457 +
8458 +/* Flags for use in omap_hwmod_sysconfig.idlemodes */
8459 +#define MASTER_STANDBY_SHIFT 2
8460 +#define SLAVE_IDLE_SHIFT 0
8461 +#define SIDLE_FORCE (HWMOD_IDLEMODE_FORCE << SLAVE_IDLE_SHIFT)
8462 +#define SIDLE_NO (HWMOD_IDLEMODE_NO << SLAVE_IDLE_SHIFT)
8463 +#define SIDLE_SMART (HWMOD_IDLEMODE_SMART << SLAVE_IDLE_SHIFT)
8464 +#define MSTANDBY_FORCE (HWMOD_IDLEMODE_FORCE << MASTER_STANDBY_SHIFT)
8465 +#define MSTANDBY_NO (HWMOD_IDLEMODE_NO << MASTER_STANDBY_SHIFT)
8466 +#define MSTANDBY_SMART (HWMOD_IDLEMODE_SMART << MASTER_STANDBY_SHIFT)
8467 +
8468 +/* omap_hwmod_sysconfig.sysc_flags capability flags */
8469 +#define SYSC_HAS_AUTOIDLE (1 << 0)
8470 +#define SYSC_HAS_SOFTRESET (1 << 1)
8471 +#define SYSC_HAS_ENAWAKEUP (1 << 2)
8472 +#define SYSC_HAS_EMUFREE (1 << 3)
8473 +#define SYSC_HAS_CLOCKACTIVITY (1 << 4)
8474 +#define SYSC_HAS_SIDLEMODE (1 << 5)
8475 +#define SYSC_HAS_MIDLEMODE (1 << 6)
8476 +#define SYSS_MISSING (1 << 7)
8477 +
8478 +/* omap_hwmod_sysconfig.clockact flags */
8479 +#define CLOCKACT_TEST_BOTH 0x0
8480 +#define CLOCKACT_TEST_MAIN 0x1
8481 +#define CLOCKACT_TEST_ICLK 0x2
8482 +#define CLOCKACT_TEST_NONE 0x3
8483 +
8484 +/**
8485 + * struct omap_hwmod_sysconfig - hwmod OCP_SYSCONFIG/OCP_SYSSTATUS data
8486 + * @rev_offs: IP block revision register offset (from module base addr)
8487 + * @sysc_offs: OCP_SYSCONFIG register offset (from module base addr)
8488 + * @syss_offs: OCP_SYSSTATUS register offset (from module base addr)
8489 + * @idlemodes: One or more of {SIDLE,MSTANDBY}_{OFF,FORCE,SMART}
8490 + * @sysc_flags: SYS{C,S}_HAS* flags indicating SYSCONFIG bits supported
8491 + * @clockact: the default value of the module CLOCKACTIVITY bits
8492 + *
8493 + * @clockact describes to the module which clocks are likely to be
8494 + * disabled when the PRCM issues its idle request to the module. Some
8495 + * modules have separate clockdomains for the interface clock and main
8496 + * functional clock, and can check whether they should acknowledge the
8497 + * idle request based on the internal module functionality that has
8498 + * been associated with the clocks marked in @clockact. This field is
8499 + * only used if HWMOD_SET_DEFAULT_CLOCKACT is set (see below)
8500 + *
8501 + */
8502 +struct omap_hwmod_sysconfig {
8503 + u16 rev_offs;
8504 + u16 sysc_offs;
8505 + u16 syss_offs;
8506 + u8 idlemodes;
8507 + u8 sysc_flags;
8508 + u8 clockact;
8509 +};
8510 +
8511 +/**
8512 + * struct omap_hwmod_omap2_prcm - OMAP2/3-specific PRCM data
8513 + * @module_offs: PRCM submodule offset from the start of the PRM/CM
8514 + * @prcm_reg_id: PRCM register ID (e.g., 3 for CM_AUTOIDLE3)
8515 + * @module_bit: register bit shift for AUTOIDLE, WKST, WKEN, GRPSEL regs
8516 + * @idlest_reg_id: IDLEST register ID (e.g., 3 for CM_IDLEST3)
8517 + * @idlest_idle_bit: register bit shift for CM_IDLEST slave idle bit
8518 + * @idlest_stdby_bit: register bit shift for CM_IDLEST master standby bit
8519 + *
8520 + * @prcm_reg_id and @module_bit are specific to the AUTOIDLE, WKST,
8521 + * WKEN, GRPSEL registers. In an ideal world, no extra information
8522 + * would be needed for IDLEST information, but alas, there are some
8523 + * exceptions, so @idlest_reg_id, @idlest_idle_bit, @idlest_stdby_bit
8524 + * are needed for the IDLEST registers (c.f. 2430 I2CHS, 3430 USBHOST)
8525 + */
8526 +struct omap_hwmod_omap2_prcm {
8527 + s16 module_offs;
8528 + u8 prcm_reg_id;
8529 + u8 module_bit;
8530 + u8 idlest_reg_id;
8531 + u8 idlest_idle_bit;
8532 + u8 idlest_stdby_bit;
8533 +};
8534 +
8535 +
8536 +/**
8537 + * struct omap_hwmod_omap4_prcm - OMAP4-specific PRCM data
8538 + * @module_offs: PRCM submodule offset from the start of the PRM/CM1/CM2
8539 + * @device_offs: device register offset from @module_offs
8540 + * @submodule_wkdep_bit: bit shift of the WKDEP range
8541 + */
8542 +struct omap_hwmod_omap4_prcm {
8543 + u32 module_offs;
8544 + u16 device_offs;
8545 + u8 submodule_wkdep_bit;
8546 +};
8547 +
8548 +
8549 +/*
8550 + * omap_hwmod.flags definitions
8551 + *
8552 + * HWMOD_SWSUP_SIDLE: omap_hwmod code should manually bring module in and out
8553 + * of idle, rather than relying on module smart-idle
8554 + * HWMOD_SWSUP_MSTDBY: omap_hwmod code should manually bring module in and out
8555 + * of standby, rather than relying on module smart-standby
8556 + * HWMOD_INIT_NO_RESET: don't reset this module at boot - important for
8557 + * SDRAM controller, etc.
8558 + * HWMOD_INIT_NO_IDLE: don't idle this module at boot - important for SDRAM
8559 + * controller, etc.
8560 + * HWMOD_NO_AUTOIDLE: disable module autoidle (OCP_SYSCONFIG.AUTOIDLE)
8561 + * when module is enabled, rather than the default, which is to
8562 + * enable autoidle
8563 + * HWMOD_SET_DEFAULT_CLOCKACT: program CLOCKACTIVITY bits at startup
8564 + */
8565 +#define HWMOD_SWSUP_SIDLE (1 << 0)
8566 +#define HWMOD_SWSUP_MSTANDBY (1 << 1)
8567 +#define HWMOD_INIT_NO_RESET (1 << 2)
8568 +#define HWMOD_INIT_NO_IDLE (1 << 3)
8569 +#define HWMOD_NO_OCP_AUTOIDLE (1 << 4)
8570 +#define HWMOD_SET_DEFAULT_CLOCKACT (1 << 5)
8571 +
8572 +/*
8573 + * omap_hwmod._int_flags definitions
8574 + * These are for internal use only and are managed by the omap_hwmod code.
8575 + *
8576 + * _HWMOD_NO_MPU_PORT: no path exists for the MPU to write to this module
8577 + * _HWMOD_WAKEUP_ENABLED: set when the omap_hwmod code has enabled ENAWAKEUP
8578 + * _HWMOD_SYSCONFIG_LOADED: set when the OCP_SYSCONFIG value has been cached
8579 + */
8580 +#define _HWMOD_NO_MPU_PORT (1 << 0)
8581 +#define _HWMOD_WAKEUP_ENABLED (1 << 1)
8582 +#define _HWMOD_SYSCONFIG_LOADED (1 << 2)
8583 +
8584 +/*
8585 + * omap_hwmod._state definitions
8586 + *
8587 + * INITIALIZED: reset (optionally), initialized, enabled, disabled
8588 + * (optionally)
8589 + *
8590 + *
8591 + */
8592 +#define _HWMOD_STATE_UNKNOWN 0
8593 +#define _HWMOD_STATE_REGISTERED 1
8594 +#define _HWMOD_STATE_CLKS_INITED 2
8595 +#define _HWMOD_STATE_INITIALIZED 3
8596 +#define _HWMOD_STATE_ENABLED 4
8597 +#define _HWMOD_STATE_IDLE 5
8598 +#define _HWMOD_STATE_DISABLED 6
8599 +
8600 +/**
8601 + * struct omap_hwmod - integration data for OMAP hardware "modules" (IP blocks)
8602 + * @name: name of the hwmod
8603 + * @od: struct omap_device currently associated with this hwmod (internal use)
8604 + * @mpu_irqs: ptr to an array of MPU IRQs (see also mpu_irqs_cnt)
8605 + * @sdma_chs: ptr to an array of SDMA channel IDs (see also sdma_chs_cnt)
8606 + * @prcm: PRCM data pertaining to this hwmod
8607 + * @clkdev_dev_id: main clock: clkdev dev_id string
8608 + * @clkdev_con_id: main clock: clkdev con_id string
8609 + * @_clk: pointer to the main struct clk (filled in at runtime)
8610 + * @opt_clks: other device clocks that drivers can request (0..*)
8611 + * @masters: ptr to array of OCP ifs that this hwmod can initiate on
8612 + * @slaves: ptr to array of OCP ifs that this hwmod can respond on
8613 + * @sysconfig: device SYSCONFIG/SYSSTATUS register data
8614 + * @dev_attr: arbitrary device attributes that can be passed to the driver
8615 + * @_sysc_cache: internal-use hwmod flags
8616 + * @_rt_va: cached register target start address (internal use)
8617 + * @_mpu_port_index: cached MPU register target slave ID (internal use)
8618 + * @msuspendmux_reg_id: CONTROL_MSUSPENDMUX register ID (1-6)
8619 + * @msuspendmux_shift: CONTROL_MSUSPENDMUX register bit shift
8620 + * @mpu_irqs_cnt: number of @mpu_irqs
8621 + * @sdma_chs_cnt: number of @sdma_chs
8622 + * @opt_clks_cnt: number of @opt_clks
8623 + * @master_cnt: number of @master entries
8624 + * @slaves_cnt: number of @slave entries
8625 + * @response_lat: device OCP response latency (in interface clock cycles)
8626 + * @_int_flags: internal-use hwmod flags
8627 + * @_state: internal-use hwmod state
8628 + * @flags: hwmod flags (documented below)
8629 + * @omap_chip: OMAP chips this hwmod is present on
8630 + * @node: list node for hwmod list (internal use)
8631 + *
8632 + * @clkdev_dev_id, @clkdev_con_id, and @clk all refer to this module's "main
8633 + * clock," which for our purposes is defined as "the functional clock needed
8634 + * for register accesses to complete." Modules may not have a main clock if
8635 + * the interface clock also serves as a main clock.
8636 + *
8637 + * Parameter names beginning with an underscore are managed internally by
8638 + * the omap_hwmod code and should not be set during initialization.
8639 + */
8640 +struct omap_hwmod {
8641 + const char *name;
8642 + struct omap_device *od;
8643 + struct omap_hwmod_irq_info *mpu_irqs;
8644 + struct omap_hwmod_dma_info *sdma_chs;
8645 + union {
8646 + struct omap_hwmod_omap2_prcm omap2;
8647 + struct omap_hwmod_omap4_prcm omap4;
8648 + } prcm;
8649 + const char *clkdev_dev_id;
8650 + const char *clkdev_con_id;
8651 + struct clk *_clk;
8652 + struct omap_hwmod_opt_clk *opt_clks;
8653 + struct omap_hwmod_ocp_if **masters; /* connect to *_IA */
8654 + struct omap_hwmod_ocp_if **slaves; /* connect to *_TA */
8655 + struct omap_hwmod_sysconfig *sysconfig;
8656 + void *dev_attr;
8657 + u32 _sysc_cache;
8658 + void __iomem *_rt_va;
8659 + struct list_head node;
8660 + u16 flags;
8661 + u8 _mpu_port_index;
8662 + u8 msuspendmux_reg_id;
8663 + u8 msuspendmux_shift;
8664 + u8 response_lat;
8665 + u8 mpu_irqs_cnt;
8666 + u8 sdma_chs_cnt;
8667 + u8 opt_clks_cnt;
8668 + u8 masters_cnt;
8669 + u8 slaves_cnt;
8670 + u8 hwmods_cnt;
8671 + u8 _int_flags;
8672 + u8 _state;
8673 + const struct omap_chip_id omap_chip;
8674 +};
8675 +
8676 +int omap_hwmod_init(struct omap_hwmod **ohs);
8677 +int omap_hwmod_register(struct omap_hwmod *oh);
8678 +int omap_hwmod_unregister(struct omap_hwmod *oh);
8679 +struct omap_hwmod *omap_hwmod_lookup(const char *name);
8680 +int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh));
8681 +int omap_hwmod_late_init(void);
8682 +
8683 +int omap_hwmod_enable(struct omap_hwmod *oh);
8684 +int omap_hwmod_idle(struct omap_hwmod *oh);
8685 +int omap_hwmod_shutdown(struct omap_hwmod *oh);
8686 +
8687 +int omap_hwmod_enable_clocks(struct omap_hwmod *oh);
8688 +int omap_hwmod_disable_clocks(struct omap_hwmod *oh);
8689 +
8690 +int omap_hwmod_reset(struct omap_hwmod *oh);
8691 +void omap_hwmod_ocp_barrier(struct omap_hwmod *oh);
8692 +
8693 +void omap_hwmod_writel(u32 v, struct omap_hwmod *oh, u16 reg_offs);
8694 +u32 omap_hwmod_readl(struct omap_hwmod *oh, u16 reg_offs);
8695 +
8696 +int omap_hwmod_count_resources(struct omap_hwmod *oh);
8697 +int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res);
8698 +
8699 +struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh);
8700 +
8701 +int omap_hwmod_add_initiator_dep(struct omap_hwmod *oh,
8702 + struct omap_hwmod *init_oh);
8703 +int omap_hwmod_del_initiator_dep(struct omap_hwmod *oh,
8704 + struct omap_hwmod *init_oh);
8705 +
8706 +int omap_hwmod_set_clockact_both(struct omap_hwmod *oh);
8707 +int omap_hwmod_set_clockact_main(struct omap_hwmod *oh);
8708 +int omap_hwmod_set_clockact_iclk(struct omap_hwmod *oh);
8709 +int omap_hwmod_set_clockact_none(struct omap_hwmod *oh);
8710 +
8711 +int omap_hwmod_enable_wakeup(struct omap_hwmod *oh);
8712 +int omap_hwmod_disable_wakeup(struct omap_hwmod *oh);
8713 +
8714 +#endif
8715 Index: linux-2.6.35/arch/arm/plat-omap/include/mach/omap-pm.h
8716 ===================================================================
8717 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
8718 +++ linux-2.6.35/arch/arm/plat-omap/include/mach/omap-pm.h 2010-08-08 12:57:12.000000000 +0200
8719 @@ -0,0 +1,301 @@
8720 +/*
8721 + * omap-pm.h - OMAP power management interface
8722 + *
8723 + * Copyright (C) 2008-2009 Texas Instruments, Inc.
8724 + * Copyright (C) 2008-2009 Nokia Corporation
8725 + * Paul Walmsley
8726 + *
8727 + * Interface developed by (in alphabetical order): Karthik Dasu, Jouni
8728 + * Högander, Tony Lindgren, Rajendra Nayak, Sakari Poussa,
8729 + * Veeramanikandan Raju, Anand Sawant, Igor Stoppa, Paul Walmsley,
8730 + * Richard Woodruff
8731 + */
8732 +
8733 +#ifndef ASM_ARM_ARCH_OMAP_OMAP_PM_H
8734 +#define ASM_ARM_ARCH_OMAP_OMAP_PM_H
8735 +
8736 +#include <linux/device.h>
8737 +#include <linux/cpufreq.h>
8738 +
8739 +#include "powerdomain.h"
8740 +
8741 +/**
8742 + * struct omap_opp - clock frequency-to-OPP ID table for DSP, MPU
8743 + * @rate: target clock rate
8744 + * @opp_id: OPP ID
8745 + * @min_vdd: minimum VDD1 voltage (in millivolts) for this OPP
8746 + *
8747 + * Operating performance point data. Can vary by OMAP chip and board.
8748 + */
8749 +struct omap_opp {
8750 + unsigned long rate;
8751 + u8 opp_id;
8752 + u16 min_vdd;
8753 +};
8754 +
8755 +extern struct omap_opp *mpu_opps;
8756 +extern struct omap_opp *dsp_opps;
8757 +extern struct omap_opp *l3_opps;
8758 +
8759 +/*
8760 + * agent_id values for use with omap_pm_set_min_bus_tput():
8761 + *
8762 + * OCP_INITIATOR_AGENT is only valid for devices that can act as
8763 + * initiators -- it represents the device's L3 interconnect
8764 + * connection. OCP_TARGET_AGENT represents the device's L4
8765 + * interconnect connection.
8766 + */
8767 +#define OCP_TARGET_AGENT 1
8768 +#define OCP_INITIATOR_AGENT 2
8769 +
8770 +/**
8771 + * omap_pm_if_early_init - OMAP PM init code called before clock fw init
8772 + * @mpu_opp_table: array ptr to struct omap_opp for MPU
8773 + * @dsp_opp_table: array ptr to struct omap_opp for DSP
8774 + * @l3_opp_table : array ptr to struct omap_opp for CORE
8775 + *
8776 + * Initialize anything that must be configured before the clock
8777 + * framework starts. The "_if_" is to avoid name collisions with the
8778 + * PM idle-loop code.
8779 + */
8780 +int __init omap_pm_if_early_init(struct omap_opp *mpu_opp_table,
8781 + struct omap_opp *dsp_opp_table,
8782 + struct omap_opp *l3_opp_table);
8783 +
8784 +/**
8785 + * omap_pm_if_init - OMAP PM init code called after clock fw init
8786 + *
8787 + * The main initialization code. OPP tables are passed in here. The
8788 + * "_if_" is to avoid name collisions with the PM idle-loop code.
8789 + */
8790 +int __init omap_pm_if_init(void);
8791 +
8792 +/**
8793 + * omap_pm_if_exit - OMAP PM exit code
8794 + *
8795 + * Exit code; currently unused. The "_if_" is to avoid name
8796 + * collisions with the PM idle-loop code.
8797 + */
8798 +void omap_pm_if_exit(void);
8799 +
8800 +/*
8801 + * Device-driver-originated constraints (via board-*.c files, platform_data)
8802 + */
8803 +
8804 +
8805 +/**
8806 + * omap_pm_set_max_mpu_wakeup_lat - set the maximum MPU wakeup latency
8807 + * @dev: struct device * requesting the constraint
8808 + * @t: maximum MPU wakeup latency in microseconds
8809 + *
8810 + * Request that the maximum interrupt latency for the MPU to be no
8811 + * greater than 't' microseconds. "Interrupt latency" in this case is
8812 + * defined as the elapsed time from the occurrence of a hardware or
8813 + * timer interrupt to the time when the device driver's interrupt
8814 + * service routine has been entered by the MPU.
8815 + *
8816 + * It is intended that underlying PM code will use this information to
8817 + * determine what power state to put the MPU powerdomain into, and
8818 + * possibly the CORE powerdomain as well, since interrupt handling
8819 + * code currently runs from SDRAM. Advanced PM or board*.c code may
8820 + * also configure interrupt controller priorities, OCP bus priorities,
8821 + * CPU speed(s), etc.
8822 + *
8823 + * This function will not affect device wakeup latency, e.g., time
8824 + * elapsed from when a device driver enables a hardware device with
8825 + * clk_enable(), to when the device is ready for register access or
8826 + * other use. To control this device wakeup latency, use
8827 + * set_max_dev_wakeup_lat()
8828 + *
8829 + * Multiple calls to set_max_mpu_wakeup_lat() will replace the
8830 + * previous t value. To remove the latency target for the MPU, call
8831 + * with t = -1.
8832 + *
8833 + * No return value.
8834 + */
8835 +void omap_pm_set_max_mpu_wakeup_lat(struct device *dev, long t);
8836 +
8837 +
8838 +/**
8839 + * omap_pm_set_min_bus_tput - set minimum bus throughput needed by device
8840 + * @dev: struct device * requesting the constraint
8841 + * @tbus_id: interconnect to operate on (OCP_{INITIATOR,TARGET}_AGENT)
8842 + * @r: minimum throughput (in KiB/s)
8843 + *
8844 + * Request that the minimum data throughput on the OCP interconnect
8845 + * attached to device 'dev' interconnect agent 'tbus_id' be no less
8846 + * than 'r' KiB/s.
8847 + *
8848 + * It is expected that the OMAP PM or bus code will use this
8849 + * information to set the interconnect clock to run at the lowest
8850 + * possible speed that satisfies all current system users. The PM or
8851 + * bus code will adjust the estimate based on its model of the bus, so
8852 + * device driver authors should attempt to specify an accurate
8853 + * quantity for their device use case, and let the PM or bus code
8854 + * overestimate the numbers as necessary to handle request/response
8855 + * latency, other competing users on the system, etc. On OMAP2/3, if
8856 + * a driver requests a minimum L4 interconnect speed constraint, the
8857 + * code will also need to add an minimum L3 interconnect speed
8858 + * constraint,
8859 + *
8860 + * Multiple calls to set_min_bus_tput() will replace the previous rate
8861 + * value for this device. To remove the interconnect throughput
8862 + * restriction for this device, call with r = 0.
8863 + *
8864 + * No return value.
8865 + */
8866 +void omap_pm_set_min_bus_tput(struct device *dev, u8 agent_id, unsigned long r);
8867 +
8868 +
8869 +/**
8870 + * omap_pm_set_max_dev_wakeup_lat - set the maximum device enable latency
8871 + * @dev: struct device *
8872 + * @t: maximum device wakeup latency in microseconds
8873 + *
8874 + * Request that the maximum amount of time necessary for a device to
8875 + * become accessible after its clocks are enabled should be no greater
8876 + * than 't' microseconds. Specifically, this represents the time from
8877 + * when a device driver enables device clocks with clk_enable(), to
8878 + * when the register reads and writes on the device will succeed.
8879 + * This function should be called before clk_disable() is called,
8880 + * since the power state transition decision may be made during
8881 + * clk_disable().
8882 + *
8883 + * It is intended that underlying PM code will use this information to
8884 + * determine what power state to put the powerdomain enclosing this
8885 + * device into.
8886 + *
8887 + * Multiple calls to set_max_dev_wakeup_lat() will replace the
8888 + * previous wakeup latency values for this device. To remove the wakeup
8889 + * latency restriction for this device, call with t = -1.
8890 + *
8891 + * No return value.
8892 + */
8893 +void omap_pm_set_max_dev_wakeup_lat(struct device *dev, long t);
8894 +
8895 +
8896 +/**
8897 + * omap_pm_set_max_sdma_lat - set the maximum system DMA transfer start latency
8898 + * @dev: struct device *
8899 + * @t: maximum DMA transfer start latency in microseconds
8900 + *
8901 + * Request that the maximum system DMA transfer start latency for this
8902 + * device 'dev' should be no greater than 't' microseconds. "DMA
8903 + * transfer start latency" here is defined as the elapsed time from
8904 + * when a device (e.g., McBSP) requests that a system DMA transfer
8905 + * start or continue, to the time at which data starts to flow into
8906 + * that device from the system DMA controller.
8907 + *
8908 + * It is intended that underlying PM code will use this information to
8909 + * determine what power state to put the CORE powerdomain into.
8910 + *
8911 + * Since system DMA transfers may not involve the MPU, this function
8912 + * will not affect MPU wakeup latency. Use set_max_cpu_lat() to do
8913 + * so. Similarly, this function will not affect device wakeup latency
8914 + * -- use set_max_dev_wakeup_lat() to affect that.
8915 + *
8916 + * Multiple calls to set_max_sdma_lat() will replace the previous t
8917 + * value for this device. To remove the maximum DMA latency for this
8918 + * device, call with t = -1.
8919 + *
8920 + * No return value.
8921 + */
8922 +void omap_pm_set_max_sdma_lat(struct device *dev, long t);
8923 +
8924 +
8925 +/*
8926 + * DSP Bridge-specific constraints
8927 + */
8928 +
8929 +/**
8930 + * omap_pm_dsp_get_opp_table - get OPP->DSP clock frequency table
8931 + *
8932 + * Intended for use by DSPBridge. Returns an array of OPP->DSP clock
8933 + * frequency entries. The final item in the array should have .rate =
8934 + * .opp_id = 0.
8935 + */
8936 +const struct omap_opp *omap_pm_dsp_get_opp_table(void);
8937 +
8938 +/**
8939 + * omap_pm_dsp_set_min_opp - receive desired OPP target ID from DSP Bridge
8940 + * @opp_id: target DSP OPP ID
8941 + *
8942 + * Set a minimum OPP ID for the DSP. This is intended to be called
8943 + * only from the DSP Bridge MPU-side driver. Unfortunately, the only
8944 + * information that code receives from the DSP/BIOS load estimator is the
8945 + * target OPP ID; hence, this interface. No return value.
8946 + */
8947 +void omap_pm_dsp_set_min_opp(u8 opp_id);
8948 +
8949 +/**
8950 + * omap_pm_dsp_get_opp - report the current DSP OPP ID
8951 + *
8952 + * Report the current OPP for the DSP. Since on OMAP3, the DSP and
8953 + * MPU share a single voltage domain, the OPP ID returned back may
8954 + * represent a higher DSP speed than the OPP requested via
8955 + * omap_pm_dsp_set_min_opp().
8956 + *
8957 + * Returns the current VDD1 OPP ID, or 0 upon error.
8958 + */
8959 +u8 omap_pm_dsp_get_opp(void);
8960 +
8961 +
8962 +/*
8963 + * CPUFreq-originated constraint
8964 + *
8965 + * In the future, this should be handled by custom OPP clocktype
8966 + * functions.
8967 + */
8968 +
8969 +/**
8970 + * omap_pm_cpu_get_freq_table - return a cpufreq_frequency_table array ptr
8971 + *
8972 + * Provide a frequency table usable by CPUFreq for the current chip/board.
8973 + * Returns a pointer to a struct cpufreq_frequency_table array or NULL
8974 + * upon error.
8975 + */
8976 +struct cpufreq_frequency_table **omap_pm_cpu_get_freq_table(void);
8977 +
8978 +/**
8979 + * omap_pm_cpu_set_freq - set the current minimum MPU frequency
8980 + * @f: MPU frequency in Hz
8981 + *
8982 + * Set the current minimum CPU frequency. The actual CPU frequency
8983 + * used could end up higher if the DSP requested a higher OPP.
8984 + * Intended to be called by plat-omap/cpu_omap.c:omap_target(). No
8985 + * return value.
8986 + */
8987 +void omap_pm_cpu_set_freq(unsigned long f);
8988 +
8989 +/**
8990 + * omap_pm_cpu_get_freq - report the current CPU frequency
8991 + *
8992 + * Returns the current MPU frequency, or 0 upon error.
8993 + */
8994 +unsigned long omap_pm_cpu_get_freq(void);
8995 +
8996 +
8997 +/*
8998 + * Device context loss tracking
8999 + */
9000 +
9001 +/**
9002 + * omap_pm_get_dev_context_loss_count - return count of times dev has lost ctx
9003 + * @dev: struct device *
9004 + *
9005 + * This function returns the number of times that the device @dev has
9006 + * lost its internal context. This generally occurs on a powerdomain
9007 + * transition to OFF. Drivers use this as an optimization to avoid restoring
9008 + * context if the device hasn't lost it. To use, drivers should initially
9009 + * call this in their context save functions and store the result. Early in
9010 + * the driver's context restore function, the driver should call this function
9011 + * again, and compare the result to the stored counter. If they differ, the
9012 + * driver must restore device context. If the number of context losses
9013 + * exceeds the maximum positive integer, the function will wrap to 0 and
9014 + * continue counting. Returns the number of context losses for this device,
9015 + * or -EINVAL upon error.
9016 + */
9017 +int omap_pm_get_dev_context_loss_count(struct device *dev);
9018 +
9019 +
9020 +#endif
9021 Index: linux-2.6.35/arch/arm/plat-omap/include/mach/onenand.h
9022 ===================================================================
9023 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
9024 +++ linux-2.6.35/arch/arm/plat-omap/include/mach/onenand.h 2010-08-08 12:57:12.000000000 +0200
9025 @@ -0,0 +1,43 @@
9026 +/*
9027 + * arch/arm/plat-omap/include/mach/onenand.h
9028 + *
9029 + * Copyright (C) 2006 Nokia Corporation
9030 + * Author: Juha Yrjola
9031 + *
9032 + * This program is free software; you can redistribute it and/or modify
9033 + * it under the terms of the GNU General Public License version 2 as
9034 + * published by the Free Software Foundation.
9035 + */
9036 +
9037 +#include <linux/mtd/mtd.h>
9038 +#include <linux/mtd/partitions.h>
9039 +
9040 +#define ONENAND_SYNC_READ (1 << 0)
9041 +#define ONENAND_SYNC_READWRITE (1 << 1)
9042 +
9043 +struct omap_onenand_platform_data {
9044 + int cs;
9045 + int gpio_irq;
9046 + struct mtd_partition *parts;
9047 + int nr_parts;
9048 + int (*onenand_setup)(void __iomem *, int freq);
9049 + int dma_channel;
9050 + u8 flags;
9051 +};
9052 +
9053 +#define ONENAND_MAX_PARTITIONS 8
9054 +
9055 +#if defined(CONFIG_MTD_ONENAND_OMAP2) || \
9056 + defined(CONFIG_MTD_ONENAND_OMAP2_MODULE)
9057 +
9058 +extern void gpmc_onenand_init(struct omap_onenand_platform_data *d);
9059 +
9060 +#else
9061 +
9062 +#define board_onenand_data NULL
9063 +
9064 +static inline void gpmc_onenand_init(struct omap_onenand_platform_data *d)
9065 +{
9066 +}
9067 +
9068 +#endif
9069 Index: linux-2.6.35/arch/arm/plat-omap/include/mach/param.h
9070 ===================================================================
9071 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
9072 +++ linux-2.6.35/arch/arm/plat-omap/include/mach/param.h 2010-08-08 12:57:13.000000000 +0200
9073 @@ -0,0 +1,8 @@
9074 +/*
9075 + * arch/arm/plat-omap/include/mach/param.h
9076 + *
9077 + */
9078 +
9079 +#ifdef CONFIG_OMAP_32K_TIMER_HZ
9080 +#define HZ CONFIG_OMAP_32K_TIMER_HZ
9081 +#endif
9082 Index: linux-2.6.35/arch/arm/plat-omap/include/mach/powerdomain.h
9083 ===================================================================
9084 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
9085 +++ linux-2.6.35/arch/arm/plat-omap/include/mach/powerdomain.h 2010-08-08 12:57:13.000000000 +0200
9086 @@ -0,0 +1,187 @@
9087 +/*
9088 + * OMAP2/3 powerdomain control
9089 + *
9090 + * Copyright (C) 2007-8 Texas Instruments, Inc.
9091 + * Copyright (C) 2007-8 Nokia Corporation
9092 + *
9093 + * Written by Paul Walmsley
9094 + *
9095 + * This program is free software; you can redistribute it and/or modify
9096 + * it under the terms of the GNU General Public License version 2 as
9097 + * published by the Free Software Foundation.
9098 + */
9099 +
9100 +#ifndef ASM_ARM_ARCH_OMAP_POWERDOMAIN
9101 +#define ASM_ARM_ARCH_OMAP_POWERDOMAIN
9102 +
9103 +#include <linux/types.h>
9104 +#include <linux/list.h>
9105 +
9106 +#include <asm/atomic.h>
9107 +
9108 +#include <plat/cpu.h>
9109 +
9110 +
9111 +/* Powerdomain basic power states */
9112 +#define PWRDM_POWER_OFF 0x0
9113 +#define PWRDM_POWER_RET 0x1
9114 +#define PWRDM_POWER_INACTIVE 0x2
9115 +#define PWRDM_POWER_ON 0x3
9116 +
9117 +#define PWRDM_MAX_PWRSTS 4
9118 +
9119 +/* Powerdomain allowable state bitfields */
9120 +#define PWRSTS_OFF_ON ((1 << PWRDM_POWER_OFF) | \
9121 + (1 << PWRDM_POWER_ON))
9122 +
9123 +#define PWRSTS_OFF_RET ((1 << PWRDM_POWER_OFF) | \
9124 + (1 << PWRDM_POWER_RET))
9125 +
9126 +#define PWRSTS_OFF_RET_ON (PWRSTS_OFF_RET | (1 << PWRDM_POWER_ON))
9127 +
9128 +
9129 +/* Powerdomain flags */
9130 +#define PWRDM_HAS_HDWR_SAR (1 << 0) /* hardware save-and-restore support */
9131 +#define PWRDM_HAS_MPU_QUIRK (1 << 1) /* MPU pwr domain has MEM bank 0 bits
9132 + * in MEM bank 1 position. This is
9133 + * true for OMAP3430
9134 + */
9135 +
9136 +/*
9137 + * Number of memory banks that are power-controllable. On OMAP3430, the
9138 + * maximum is 4.
9139 + */
9140 +#define PWRDM_MAX_MEM_BANKS 4
9141 +
9142 +/*
9143 + * Maximum number of clockdomains that can be associated with a powerdomain.
9144 + * CORE powerdomain on OMAP3 is the worst case
9145 + */
9146 +#define PWRDM_MAX_CLKDMS 4
9147 +
9148 +/* XXX A completely arbitrary number. What is reasonable here? */
9149 +#define PWRDM_TRANSITION_BAILOUT 100000
9150 +
9151 +struct clockdomain;
9152 +struct powerdomain;
9153 +
9154 +/* Encodes dependencies between powerdomains - statically defined */
9155 +struct pwrdm_dep {
9156 +
9157 + /* Powerdomain name */
9158 + const char *pwrdm_name;
9159 +
9160 + /* Powerdomain pointer - resolved by the powerdomain code */
9161 + struct powerdomain *pwrdm;
9162 +
9163 + /* Flags to mark OMAP chip restrictions, etc. */
9164 + const struct omap_chip_id omap_chip;
9165 +
9166 +};
9167 +
9168 +struct powerdomain {
9169 +
9170 + /* Powerdomain name */
9171 + const char *name;
9172 +
9173 + /* the address offset from CM_BASE/PRM_BASE */
9174 + const s16 prcm_offs;
9175 +
9176 + /* Used to represent the OMAP chip types containing this pwrdm */
9177 + const struct omap_chip_id omap_chip;
9178 +
9179 + /* Powerdomains that can be told to wake this powerdomain up */
9180 + struct pwrdm_dep *wkdep_srcs;
9181 +
9182 + /* Powerdomains that can be told to keep this pwrdm from inactivity */
9183 + struct pwrdm_dep *sleepdep_srcs;
9184 +
9185 + /* Bit shift of this powerdomain's PM_WKDEP/CM_SLEEPDEP bit */
9186 + const u8 dep_bit;
9187 +
9188 + /* Possible powerdomain power states */
9189 + const u8 pwrsts;
9190 +
9191 + /* Possible logic power states when pwrdm in RETENTION */
9192 + const u8 pwrsts_logic_ret;
9193 +
9194 + /* Powerdomain flags */
9195 + const u8 flags;
9196 +
9197 + /* Number of software-controllable memory banks in this powerdomain */
9198 + const u8 banks;
9199 +
9200 + /* Possible memory bank pwrstates when pwrdm in RETENTION */
9201 + const u8 pwrsts_mem_ret[PWRDM_MAX_MEM_BANKS];
9202 +
9203 + /* Possible memory bank pwrstates when pwrdm is ON */
9204 + const u8 pwrsts_mem_on[PWRDM_MAX_MEM_BANKS];
9205 +
9206 + /* Clockdomains in this powerdomain */
9207 + struct clockdomain *pwrdm_clkdms[PWRDM_MAX_CLKDMS];
9208 +
9209 + struct list_head node;
9210 +
9211 + int state;
9212 + unsigned state_counter[PWRDM_MAX_PWRSTS];
9213 +
9214 +#ifdef CONFIG_PM_DEBUG
9215 + s64 timer;
9216 + s64 state_timer[PWRDM_MAX_PWRSTS];
9217 +#endif
9218 +};
9219 +
9220 +
9221 +void pwrdm_init(struct powerdomain **pwrdm_list);
9222 +
9223 +int pwrdm_register(struct powerdomain *pwrdm);
9224 +int pwrdm_unregister(struct powerdomain *pwrdm);
9225 +struct powerdomain *pwrdm_lookup(const char *name);
9226 +
9227 +int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm, void *user),
9228 + void *user);
9229 +int pwrdm_for_each_nolock(int (*fn)(struct powerdomain *pwrdm, void *user),
9230 + void *user);
9231 +
9232 +int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm);
9233 +int pwrdm_del_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm);
9234 +int pwrdm_for_each_clkdm(struct powerdomain *pwrdm,
9235 + int (*fn)(struct powerdomain *pwrdm,
9236 + struct clockdomain *clkdm));
9237 +
9238 +int pwrdm_add_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
9239 +int pwrdm_del_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
9240 +int pwrdm_read_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
9241 +int pwrdm_add_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
9242 +int pwrdm_del_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
9243 +int pwrdm_read_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
9244 +
9245 +int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm);
9246 +
9247 +int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst);
9248 +int pwrdm_read_next_pwrst(struct powerdomain *pwrdm);
9249 +int pwrdm_read_pwrst(struct powerdomain *pwrdm);
9250 +int pwrdm_read_prev_pwrst(struct powerdomain *pwrdm);
9251 +int pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm);
9252 +
9253 +int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst);
9254 +int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
9255 +int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
9256 +
9257 +int pwrdm_read_logic_pwrst(struct powerdomain *pwrdm);
9258 +int pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm);
9259 +int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
9260 +int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
9261 +
9262 +int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm);
9263 +int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm);
9264 +bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm);
9265 +
9266 +int pwrdm_wait_transition(struct powerdomain *pwrdm);
9267 +
9268 +int pwrdm_state_switch(struct powerdomain *pwrdm);
9269 +int pwrdm_clkdm_state_switch(struct clockdomain *clkdm);
9270 +int pwrdm_pre_transition(void);
9271 +int pwrdm_post_transition(void);
9272 +
9273 +#endif
9274 Index: linux-2.6.35/arch/arm/plat-omap/include/mach/prcm.h
9275 ===================================================================
9276 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
9277 +++ linux-2.6.35/arch/arm/plat-omap/include/mach/prcm.h 2010-08-08 12:57:14.000000000 +0200
9278 @@ -0,0 +1,39 @@
9279 +/*
9280 + * arch/arm/plat-omap/include/mach/prcm.h
9281 + *
9282 + * Access definations for use in OMAP24XX clock and power management
9283 + *
9284 + * Copyright (C) 2005 Texas Instruments, Inc.
9285 + *
9286 + * This program is free software; you can redistribute it and/or modify
9287 + * it under the terms of the GNU General Public License as published by
9288 + * the Free Software Foundation; either version 2 of the License, or
9289 + * (at your option) any later version.
9290 + *
9291 + * This program is distributed in the hope that it will be useful,
9292 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
9293 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9294 + * GNU General Public License for more details.
9295 + *
9296 + * You should have received a copy of the GNU General Public License
9297 + * along with this program; if not, write to the Free Software
9298 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
9299 + */
9300 +
9301 +#ifndef __ASM_ARM_ARCH_OMAP_PRCM_H
9302 +#define __ASM_ARM_ARCH_OMAP_PRCM_H
9303 +
9304 +u32 omap_prcm_get_reset_sources(void);
9305 +void omap_prcm_arch_reset(char mode);
9306 +int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, const char *name);
9307 +
9308 +#define START_PADCONF_SAVE 0x2
9309 +#define PADCONF_SAVE_DONE 0x1
9310 +
9311 +void omap3_prcm_save_context(void);
9312 +void omap3_prcm_restore_context(void);
9313 +
9314 +#endif
9315 +
9316 +
9317 +
9318 Index: linux-2.6.35/arch/arm/plat-omap/include/mach/sdrc.h
9319 ===================================================================
9320 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
9321 +++ linux-2.6.35/arch/arm/plat-omap/include/mach/sdrc.h 2010-08-08 12:57:15.000000000 +0200
9322 @@ -0,0 +1,158 @@
9323 +#ifndef ____ASM_ARCH_SDRC_H
9324 +#define ____ASM_ARCH_SDRC_H
9325 +
9326 +/*
9327 + * OMAP2/3 SDRC/SMS register definitions
9328 + *
9329 + * Copyright (C) 2007-2008 Texas Instruments, Inc.
9330 + * Copyright (C) 2007-2008 Nokia Corporation
9331 + *
9332 + * Tony Lindgren
9333 + * Paul Walmsley
9334 + * Richard Woodruff
9335 + *
9336 + * This program is free software; you can redistribute it and/or modify
9337 + * it under the terms of the GNU General Public License version 2 as
9338 + * published by the Free Software Foundation.
9339 + */
9340 +
9341 +#include <mach/io.h>
9342 +
9343 +/* SDRC register offsets - read/write with sdrc_{read,write}_reg() */
9344 +
9345 +#define SDRC_SYSCONFIG 0x010
9346 +#define SDRC_CS_CFG 0x040
9347 +#define SDRC_SHARING 0x044
9348 +#define SDRC_ERR_TYPE 0x04C
9349 +#define SDRC_DLLA_CTRL 0x060
9350 +#define SDRC_DLLA_STATUS 0x064
9351 +#define SDRC_DLLB_CTRL 0x068
9352 +#define SDRC_DLLB_STATUS 0x06C
9353 +#define SDRC_POWER 0x070
9354 +#define SDRC_MCFG_0 0x080
9355 +#define SDRC_MR_0 0x084
9356 +#define SDRC_EMR2_0 0x08c
9357 +#define SDRC_ACTIM_CTRL_A_0 0x09c
9358 +#define SDRC_ACTIM_CTRL_B_0 0x0a0
9359 +#define SDRC_RFR_CTRL_0 0x0a4
9360 +#define SDRC_MANUAL_0 0x0a8
9361 +#define SDRC_MCFG_1 0x0B0
9362 +#define SDRC_MR_1 0x0B4
9363 +#define SDRC_EMR2_1 0x0BC
9364 +#define SDRC_ACTIM_CTRL_A_1 0x0C4
9365 +#define SDRC_ACTIM_CTRL_B_1 0x0C8
9366 +#define SDRC_RFR_CTRL_1 0x0D4
9367 +#define SDRC_MANUAL_1 0x0D8
9368 +
9369 +#define SDRC_POWER_AUTOCOUNT_SHIFT 8
9370 +#define SDRC_POWER_AUTOCOUNT_MASK (0xffff << SDRC_POWER_AUTOCOUNT_SHIFT)
9371 +#define SDRC_POWER_CLKCTRL_SHIFT 4
9372 +#define SDRC_POWER_CLKCTRL_MASK (0x3 << SDRC_POWER_CLKCTRL_SHIFT)
9373 +#define SDRC_SELF_REFRESH_ON_AUTOCOUNT (0x2 << SDRC_POWER_CLKCTRL_SHIFT)
9374 +
9375 +/*
9376 + * These values represent the number of memory clock cycles between
9377 + * autorefresh initiation. They assume 1 refresh per 64 ms (JEDEC), 8192
9378 + * rows per device, and include a subtraction of a 50 cycle window in the
9379 + * event that the autorefresh command is delayed due to other SDRC activity.
9380 + * The '| 1' sets the ARE field to send one autorefresh when the autorefresh
9381 + * counter reaches 0.
9382 + *
9383 + * These represent optimal values for common parts, it won't work for all.
9384 + * As long as you scale down, most parameters are still work, they just
9385 + * become sub-optimal. The RFR value goes in the opposite direction. If you
9386 + * don't adjust it down as your clock period increases the refresh interval
9387 + * will not be met. Setting all parameters for complete worst case may work,
9388 + * but may cut memory performance by 2x. Due to errata the DLLs need to be
9389 + * unlocked and their value needs run time calibration. A dynamic call is
9390 + * need for that as no single right value exists acorss production samples.
9391 + *
9392 + * Only the FULL speed values are given. Current code is such that rate
9393 + * changes must be made at DPLLoutx2. The actual value adjustment for low
9394 + * frequency operation will be handled by omap_set_performance()
9395 + *
9396 + * By having the boot loader boot up in the fastest L4 speed available likely
9397 + * will result in something which you can switch between.
9398 + */
9399 +#define SDRC_RFR_CTRL_165MHz (0x00044c00 | 1)
9400 +#define SDRC_RFR_CTRL_133MHz (0x0003de00 | 1)
9401 +#define SDRC_RFR_CTRL_100MHz (0x0002da01 | 1)
9402 +#define SDRC_RFR_CTRL_110MHz (0x0002da01 | 1) /* Need to calc */
9403 +#define SDRC_RFR_CTRL_BYPASS (0x00005000 | 1) /* Need to calc */
9404 +
9405 +
9406 +/*
9407 + * SMS register access
9408 + */
9409 +
9410 +#define OMAP242X_SMS_REGADDR(reg) \
9411 + (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE + reg)
9412 +#define OMAP243X_SMS_REGADDR(reg) \
9413 + (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE + reg)
9414 +#define OMAP343X_SMS_REGADDR(reg) \
9415 + (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE + reg)
9416 +
9417 +/* SMS register offsets - read/write with sms_{read,write}_reg() */
9418 +
9419 +#define SMS_SYSCONFIG 0x010
9420 +#define SMS_ROT_CONTROL(context) (0x180 + 0x10 * context)
9421 +#define SMS_ROT_SIZE(context) (0x184 + 0x10 * context)
9422 +#define SMS_ROT_PHYSICAL_BA(context) (0x188 + 0x10 * context)
9423 +/* REVISIT: fill in other SMS registers here */
9424 +
9425 +
9426 +#ifndef __ASSEMBLER__
9427 +
9428 +/**
9429 + * struct omap_sdrc_params - SDRC parameters for a given SDRC clock rate
9430 + * @rate: SDRC clock rate (in Hz)
9431 + * @actim_ctrla: Value to program to SDRC_ACTIM_CTRLA for this rate
9432 + * @actim_ctrlb: Value to program to SDRC_ACTIM_CTRLB for this rate
9433 + * @rfr_ctrl: Value to program to SDRC_RFR_CTRL for this rate
9434 + * @mr: Value to program to SDRC_MR for this rate
9435 + *
9436 + * This structure holds a pre-computed set of register values for the
9437 + * SDRC for a given SDRC clock rate and SDRAM chip. These are
9438 + * intended to be pre-computed and specified in an array in the board-*.c
9439 + * files. The structure is keyed off the 'rate' field.
9440 + */
9441 +struct omap_sdrc_params {
9442 + unsigned long rate;
9443 + u32 actim_ctrla;
9444 + u32 actim_ctrlb;
9445 + u32 rfr_ctrl;
9446 + u32 mr;
9447 +};
9448 +
9449 +void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
9450 + struct omap_sdrc_params *sdrc_cs1);
9451 +int omap2_sdrc_get_params(unsigned long r,
9452 + struct omap_sdrc_params **sdrc_cs0,
9453 + struct omap_sdrc_params **sdrc_cs1);
9454 +void omap2_sms_save_context(void);
9455 +void omap2_sms_restore_context(void);
9456 +
9457 +void omap2_sms_write_rot_control(u32 val, unsigned ctx);
9458 +void omap2_sms_write_rot_size(u32 val, unsigned ctx);
9459 +void omap2_sms_write_rot_physical_ba(u32 val, unsigned ctx);
9460 +
9461 +#ifdef CONFIG_ARCH_OMAP2
9462 +
9463 +struct memory_timings {
9464 + u32 m_type; /* ddr = 1, sdr = 0 */
9465 + u32 dll_mode; /* use lock mode = 1, unlock mode = 0 */
9466 + u32 slow_dll_ctrl; /* unlock mode, dll value for slow speed */
9467 + u32 fast_dll_ctrl; /* unlock mode, dll value for fast speed */
9468 + u32 base_cs; /* base chip select to use for calculations */
9469 +};
9470 +
9471 +extern void omap2xxx_sdrc_init_params(u32 force_lock_to_unlock_mode);
9472 +
9473 +u32 omap2xxx_sdrc_dll_is_unlocked(void);
9474 +u32 omap2xxx_sdrc_reprogram(u32 level, u32 force);
9475 +
9476 +#endif /* CONFIG_ARCH_OMAP2 */
9477 +
9478 +#endif /* __ASSEMBLER__ */
9479 +
9480 +#endif
9481 Index: linux-2.6.35/arch/arm/plat-omap/include/mach/serial.h
9482 ===================================================================
9483 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
9484 +++ linux-2.6.35/arch/arm/plat-omap/include/mach/serial.h 2010-08-08 12:57:15.000000000 +0200
9485 @@ -0,0 +1,65 @@
9486 +/*
9487 + * arch/arm/plat-omap/include/mach/serial.h
9488 + *
9489 + * Copyright (C) 2009 Texas Instruments
9490 + * Addded OMAP4 support- Santosh Shilimkar <santosh.shilimkar@ti.com>
9491 + *
9492 + * This program is distributed in the hope that it will be useful,
9493 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
9494 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9495 + * GNU General Public License for more details.
9496 + */
9497 +
9498 +#ifndef __ASM_ARCH_SERIAL_H
9499 +#define __ASM_ARCH_SERIAL_H
9500 +
9501 +#include <linux/init.h>
9502 +
9503 +#if defined(CONFIG_ARCH_OMAP1)
9504 +/* OMAP1 serial ports */
9505 +#define OMAP_UART1_BASE 0xfffb0000
9506 +#define OMAP_UART2_BASE 0xfffb0800
9507 +#define OMAP_UART3_BASE 0xfffb9800
9508 +#elif defined(CONFIG_ARCH_OMAP2)
9509 +/* OMAP2 serial ports */
9510 +#define OMAP_UART1_BASE 0x4806a000
9511 +#define OMAP_UART2_BASE 0x4806c000
9512 +#define OMAP_UART3_BASE 0x4806e000
9513 +#elif defined(CONFIG_ARCH_OMAP3)
9514 +/* OMAP3 serial ports */
9515 +#define OMAP_UART1_BASE 0x4806a000
9516 +#define OMAP_UART2_BASE 0x4806c000
9517 +#define OMAP_UART3_BASE 0x49020000
9518 +#elif defined(CONFIG_ARCH_OMAP4)
9519 +/* OMAP4 serial ports */
9520 +#define OMAP_UART1_BASE 0x4806a000
9521 +#define OMAP_UART2_BASE 0x4806c000
9522 +#define OMAP_UART3_BASE 0x48020000
9523 +#define OMAP_UART4_BASE 0x4806e000
9524 +#endif
9525 +
9526 +#define OMAP1510_BASE_BAUD (12000000/16)
9527 +#define OMAP16XX_BASE_BAUD (48000000/16)
9528 +#define OMAP24XX_BASE_BAUD (48000000/16)
9529 +
9530 +#define is_omap_port(pt) ({int __ret = 0; \
9531 + if ((pt)->port.mapbase == OMAP_UART1_BASE || \
9532 + (pt)->port.mapbase == OMAP_UART2_BASE || \
9533 + (pt)->port.mapbase == OMAP_UART3_BASE) \
9534 + __ret = 1; \
9535 + __ret; \
9536 + })
9537 +
9538 +#ifndef __ASSEMBLER__
9539 +extern void __init omap_serial_early_init(void);
9540 +extern void omap_serial_init(void);
9541 +extern void omap_serial_init_port(int port);
9542 +extern int omap_uart_can_sleep(void);
9543 +extern void omap_uart_check_wakeup(void);
9544 +extern void omap_uart_prepare_suspend(void);
9545 +extern void omap_uart_prepare_idle(int num);
9546 +extern void omap_uart_resume_idle(int num);
9547 +extern void omap_uart_enable_irqs(int enable);
9548 +#endif
9549 +
9550 +#endif
9551 Index: linux-2.6.35/arch/arm/plat-omap/include/mach/smp.h
9552 ===================================================================
9553 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
9554 +++ linux-2.6.35/arch/arm/plat-omap/include/mach/smp.h 2010-08-08 12:57:16.000000000 +0200
9555 @@ -0,0 +1,53 @@
9556 +/*
9557 + * OMAP4 machine specific smp.h
9558 + *
9559 + * Copyright (C) 2009 Texas Instruments, Inc.
9560 + *
9561 + * Author:
9562 + * Santosh Shilimkar <santosh.shilimkar@ti.com>
9563 + *
9564 + * Interface functions needed for the SMP. This file is based on arm
9565 + * realview smp platform.
9566 + * Copyright (c) 2003 ARM Limited.
9567 + *
9568 + * This program is free software; you can redistribute it and/or modify
9569 + * it under the terms of the GNU General Public License version 2 as
9570 + * published by the Free Software Foundation.
9571 + */
9572 +#ifndef OMAP_ARCH_SMP_H
9573 +#define OMAP_ARCH_SMP_H
9574 +
9575 +#include <asm/hardware/gic.h>
9576 +
9577 +/*
9578 + * set_event() is used to wake up secondary core from wfe using sev. ROM
9579 + * code puts the second core into wfe(standby).
9580 + *
9581 + */
9582 +#define set_event() __asm__ __volatile__ ("sev" : : : "memory")
9583 +
9584 +/* Needed for secondary core boot */
9585 +extern void omap_secondary_startup(void);
9586 +extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask);
9587 +extern void omap_auxcoreboot_addr(u32 cpu_addr);
9588 +
9589 +/*
9590 + * We use Soft IRQ1 as the IPI
9591 + */
9592 +static inline void smp_cross_call(const struct cpumask *mask)
9593 +{
9594 + gic_raise_softirq(mask, 1);
9595 +}
9596 +
9597 +/*
9598 + * Read MPIDR: Multiprocessor affinity register
9599 + */
9600 +#define hard_smp_processor_id() \
9601 + ({ \
9602 + unsigned int cpunum; \
9603 + __asm__("mrc p15, 0, %0, c0, c0, 5" \
9604 + : "=r" (cpunum)); \
9605 + cpunum &= 0x0F; \
9606 + })
9607 +
9608 +#endif
9609 Index: linux-2.6.35/arch/arm/plat-omap/include/mach/sram.h
9610 ===================================================================
9611 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
9612 +++ linux-2.6.35/arch/arm/plat-omap/include/mach/sram.h 2010-08-08 12:57:16.000000000 +0200
9613 @@ -0,0 +1,78 @@
9614 +/*
9615 + * arch/arm/plat-omap/include/mach/sram.h
9616 + *
9617 + * Interface for functions that need to be run in internal SRAM
9618 + *
9619 + * This program is free software; you can redistribute it and/or modify
9620 + * it under the terms of the GNU General Public License version 2 as
9621 + * published by the Free Software Foundation.
9622 + */
9623 +
9624 +#ifndef __ARCH_ARM_OMAP_SRAM_H
9625 +#define __ARCH_ARM_OMAP_SRAM_H
9626 +
9627 +extern int __init omap_sram_init(void);
9628 +extern void * omap_sram_push(void * start, unsigned long size);
9629 +extern void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl);
9630 +
9631 +extern void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
9632 + u32 base_cs, u32 force_unlock);
9633 +extern void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
9634 + u32 mem_type);
9635 +extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
9636 +
9637 +extern u32 omap3_configure_core_dpll(
9638 + u32 m2, u32 unlock_dll, u32 f, u32 inc,
9639 + u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
9640 + u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
9641 + u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
9642 + u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
9643 +extern void omap3_sram_restore_context(void);
9644 +
9645 +/* Do not use these */
9646 +extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
9647 +extern unsigned long omap1_sram_reprogram_clock_sz;
9648 +
9649 +extern void omap24xx_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
9650 +extern unsigned long omap24xx_sram_reprogram_clock_sz;
9651 +
9652 +extern void omap242x_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
9653 + u32 base_cs, u32 force_unlock);
9654 +extern unsigned long omap242x_sram_ddr_init_sz;
9655 +
9656 +extern u32 omap242x_sram_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val,
9657 + int bypass);
9658 +extern unsigned long omap242x_sram_set_prcm_sz;
9659 +
9660 +extern void omap242x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
9661 + u32 mem_type);
9662 +extern unsigned long omap242x_sram_reprogram_sdrc_sz;
9663 +
9664 +
9665 +extern void omap243x_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
9666 + u32 base_cs, u32 force_unlock);
9667 +extern unsigned long omap243x_sram_ddr_init_sz;
9668 +
9669 +extern u32 omap243x_sram_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val,
9670 + int bypass);
9671 +extern unsigned long omap243x_sram_set_prcm_sz;
9672 +
9673 +extern void omap243x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
9674 + u32 mem_type);
9675 +extern unsigned long omap243x_sram_reprogram_sdrc_sz;
9676 +
9677 +extern u32 omap3_sram_configure_core_dpll(
9678 + u32 m2, u32 unlock_dll, u32 f, u32 inc,
9679 + u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
9680 + u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
9681 + u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
9682 + u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
9683 +extern unsigned long omap3_sram_configure_core_dpll_sz;
9684 +
9685 +#ifdef CONFIG_PM
9686 +extern void omap_push_sram_idle(void);
9687 +#else
9688 +static inline void omap_push_sram_idle(void) {}
9689 +#endif /* CONFIG_PM */
9690 +
9691 +#endif
9692 Index: linux-2.6.35/arch/arm/plat-omap/include/mach/system.h
9693 ===================================================================
9694 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
9695 +++ linux-2.6.35/arch/arm/plat-omap/include/mach/system.h 2010-08-08 12:57:17.000000000 +0200
9696 @@ -0,0 +1,51 @@
9697 +/*
9698 + * Copied from arch/arm/mach-sa1100/include/mach/system.h
9699 + * Copyright (c) 1999 Nicolas Pitre <nico@fluxnic.net>
9700 + */
9701 +#ifndef __ASM_ARCH_SYSTEM_H
9702 +#define __ASM_ARCH_SYSTEM_H
9703 +#include <linux/clk.h>
9704 +
9705 +#include <asm/mach-types.h>
9706 +#include <mach/hardware.h>
9707 +
9708 +#include <plat/prcm.h>
9709 +
9710 +#ifndef CONFIG_MACH_VOICEBLUE
9711 +#define voiceblue_reset() do {} while (0)
9712 +#else
9713 +extern void voiceblue_reset(void);
9714 +#endif
9715 +
9716 +static inline void arch_idle(void)
9717 +{
9718 + cpu_do_idle();
9719 +}
9720 +
9721 +static inline void omap1_arch_reset(char mode)
9722 +{
9723 + /*
9724 + * Workaround for 5912/1611b bug mentioned in sprz209d.pdf p. 28
9725 + * "Global Software Reset Affects Traffic Controller Frequency".
9726 + */
9727 + if (cpu_is_omap5912()) {
9728 + omap_writew(omap_readw(DPLL_CTL) & ~(1 << 4),
9729 + DPLL_CTL);
9730 + omap_writew(0x8, ARM_RSTCT1);
9731 + }
9732 +
9733 + if (machine_is_voiceblue())
9734 + voiceblue_reset();
9735 + else
9736 + omap_writew(1, ARM_RSTCT1);
9737 +}
9738 +
9739 +static inline void arch_reset(char mode, const char *cmd)
9740 +{
9741 + if (!cpu_class_is_omap2())
9742 + omap1_arch_reset(mode);
9743 + else
9744 + omap_prcm_arch_reset(mode);
9745 +}
9746 +
9747 +#endif
9748 Index: linux-2.6.35/arch/arm/plat-omap/include/mach/tc.h
9749 ===================================================================
9750 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
9751 +++ linux-2.6.35/arch/arm/plat-omap/include/mach/tc.h 2010-08-08 12:57:18.000000000 +0200
9752 @@ -0,0 +1,106 @@
9753 +/*
9754 + * arch/arm/plat-omap/include/mach/tc.h
9755 + *
9756 + * OMAP Traffic Controller
9757 + *
9758 + * Copyright (C) 2004 Nokia Corporation
9759 + * Author: Imre Deak <imre.deak@nokia.com>
9760 + *
9761 + * This program is free software; you can redistribute it and/or modify it
9762 + * under the terms of the GNU General Public License as published by the
9763 + * Free Software Foundation; either version 2 of the License, or (at your
9764 + * option) any later version.
9765 + *
9766 + * This program is distributed in the hope that it will be useful, but
9767 + * WITHOUT ANY WARRANTY; without even the implied warranty of
9768 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
9769 + * General Public License for more details.
9770 + *
9771 + * You should have received a copy of the GNU General Public License along
9772 + * with this program; if not, write to the Free Software Foundation, Inc.,
9773 + * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
9774 + */
9775 +
9776 +#ifndef __ASM_ARCH_TC_H
9777 +#define __ASM_ARCH_TC_H
9778 +
9779 +#define TCMIF_BASE 0xfffecc00
9780 +#define OMAP_TC_OCPT1_PRIOR (TCMIF_BASE + 0x00)
9781 +#define OMAP_TC_EMIFS_PRIOR (TCMIF_BASE + 0x04)
9782 +#define OMAP_TC_EMIFF_PRIOR (TCMIF_BASE + 0x08)
9783 +#define EMIFS_CONFIG (TCMIF_BASE + 0x0c)
9784 +#define EMIFS_CS0_CONFIG (TCMIF_BASE + 0x10)
9785 +#define EMIFS_CS1_CONFIG (TCMIF_BASE + 0x14)
9786 +#define EMIFS_CS2_CONFIG (TCMIF_BASE + 0x18)
9787 +#define EMIFS_CS3_CONFIG (TCMIF_BASE + 0x1c)
9788 +#define EMIFF_SDRAM_CONFIG (TCMIF_BASE + 0x20)
9789 +#define EMIFF_MRS (TCMIF_BASE + 0x24)
9790 +#define TC_TIMEOUT1 (TCMIF_BASE + 0x28)
9791 +#define TC_TIMEOUT2 (TCMIF_BASE + 0x2c)
9792 +#define TC_TIMEOUT3 (TCMIF_BASE + 0x30)
9793 +#define TC_ENDIANISM (TCMIF_BASE + 0x34)
9794 +#define EMIFF_SDRAM_CONFIG_2 (TCMIF_BASE + 0x3c)
9795 +#define EMIF_CFG_DYNAMIC_WS (TCMIF_BASE + 0x40)
9796 +#define EMIFS_ACS0 (TCMIF_BASE + 0x50)
9797 +#define EMIFS_ACS1 (TCMIF_BASE + 0x54)
9798 +#define EMIFS_ACS2 (TCMIF_BASE + 0x58)
9799 +#define EMIFS_ACS3 (TCMIF_BASE + 0x5c)
9800 +#define OMAP_TC_OCPT2_PRIOR (TCMIF_BASE + 0xd0)
9801 +
9802 +/* external EMIFS chipselect regions */
9803 +#define OMAP_CS0_PHYS 0x00000000
9804 +#define OMAP_CS0_SIZE SZ_64M
9805 +
9806 +#define OMAP_CS1_PHYS 0x04000000
9807 +#define OMAP_CS1_SIZE SZ_64M
9808 +
9809 +#define OMAP_CS1A_PHYS OMAP_CS1_PHYS
9810 +#define OMAP_CS1A_SIZE SZ_32M
9811 +
9812 +#define OMAP_CS1B_PHYS (OMAP_CS1A_PHYS + OMAP_CS1A_SIZE)
9813 +#define OMAP_CS1B_SIZE SZ_32M
9814 +
9815 +#define OMAP_CS2_PHYS 0x08000000
9816 +#define OMAP_CS2_SIZE SZ_64M
9817 +
9818 +#define OMAP_CS2A_PHYS OMAP_CS2_PHYS
9819 +#define OMAP_CS2A_SIZE SZ_32M
9820 +
9821 +#define OMAP_CS2B_PHYS (OMAP_CS2A_PHYS + OMAP_CS2A_SIZE)
9822 +#define OMAP_CS2B_SIZE SZ_32M
9823 +
9824 +#define OMAP_CS3_PHYS 0x0c000000
9825 +#define OMAP_CS3_SIZE SZ_64M
9826 +
9827 +#ifndef __ASSEMBLER__
9828 +
9829 +/* EMIF Slow Interface Configuration Register */
9830 +#define OMAP_EMIFS_CONFIG_FR (1 << 4)
9831 +#define OMAP_EMIFS_CONFIG_PDE (1 << 3)
9832 +#define OMAP_EMIFS_CONFIG_PWD_EN (1 << 2)
9833 +#define OMAP_EMIFS_CONFIG_BM (1 << 1)
9834 +#define OMAP_EMIFS_CONFIG_WP (1 << 0)
9835 +
9836 +#define EMIFS_CCS(n) (EMIFS_CS0_CONFIG + (4 * (n)))
9837 +#define EMIFS_ACS(n) (EMIFS_ACS0 + (4 * (n)))
9838 +
9839 +/* Almost all documentation for chip and board memory maps assumes
9840 + * BM is clear. Most devel boards have a switch to control booting
9841 + * from NOR flash (using external chipselect 3) rather than mask ROM,
9842 + * which uses BM to interchange the physical CS0 and CS3 addresses.
9843 + */
9844 +static inline u32 omap_cs0_phys(void)
9845 +{
9846 + return (omap_readl(EMIFS_CONFIG) & OMAP_EMIFS_CONFIG_BM)
9847 + ? OMAP_CS3_PHYS : 0;
9848 +}
9849 +
9850 +static inline u32 omap_cs3_phys(void)
9851 +{
9852 + return (omap_readl(EMIFS_CONFIG) & OMAP_EMIFS_CONFIG_BM)
9853 + ? 0 : OMAP_CS3_PHYS;
9854 +}
9855 +
9856 +#endif /* __ASSEMBLER__ */
9857 +
9858 +#endif /* __ASM_ARCH_TC_H */
9859 Index: linux-2.6.35/arch/arm/plat-omap/include/mach/timer-gp.h
9860 ===================================================================
9861 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
9862 +++ linux-2.6.35/arch/arm/plat-omap/include/mach/timer-gp.h 2010-08-08 12:57:18.000000000 +0200
9863 @@ -0,0 +1,17 @@
9864 +/*
9865 + * OMAP2/3 GPTIMER support.headers
9866 + *
9867 + * Copyright (C) 2009 Nokia Corporation
9868 + *
9869 + * This file is subject to the terms and conditions of the GNU General Public
9870 + * License. See the file "COPYING" in the main directory of this archive
9871 + * for more details.
9872 + */
9873 +
9874 +#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_TIMER_GP_H
9875 +#define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_TIMER_GP_H
9876 +
9877 +int __init omap2_gp_clockevent_set_gptimer(u8 id);
9878 +
9879 +#endif
9880 +
9881 Index: linux-2.6.35/arch/arm/plat-omap/include/mach/timex.h
9882 ===================================================================
9883 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
9884 +++ linux-2.6.35/arch/arm/plat-omap/include/mach/timex.h 2010-08-08 12:57:19.000000000 +0200
9885 @@ -0,0 +1,41 @@
9886 +/*
9887 + * arch/arm/plat-omap/include/mach/timex.h
9888 + *
9889 + * Copyright (C) 2000 RidgeRun, Inc.
9890 + * Author: Greg Lonnon <glonnon@ridgerun.com>
9891 + *
9892 + * This program is free software; you can redistribute it and/or modify it
9893 + * under the terms of the GNU General Public License as published by the
9894 + * Free Software Foundation; either version 2 of the License, or (at your
9895 + * option) any later version.
9896 + *
9897 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
9898 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
9899 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
9900 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
9901 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
9902 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
9903 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
9904 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
9905 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
9906 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
9907 + *
9908 + * You should have received a copy of the GNU General Public License along
9909 + * with this program; if not, write to the Free Software Foundation, Inc.,
9910 + * 675 Mass Ave, Cambridge, MA 02139, USA.
9911 + */
9912 +
9913 +#if !defined(__ASM_ARCH_OMAP_TIMEX_H)
9914 +#define __ASM_ARCH_OMAP_TIMEX_H
9915 +
9916 +/*
9917 + * OMAP 32KHz timer updates time one jiffie at a time from a secondary timer,
9918 + * and that's why the CLOCK_TICK_RATE is not 32768.
9919 + */
9920 +#ifdef CONFIG_OMAP_32K_TIMER
9921 +#define CLOCK_TICK_RATE (CONFIG_OMAP_32K_TIMER_HZ)
9922 +#else
9923 +#define CLOCK_TICK_RATE (HZ * 100000UL)
9924 +#endif
9925 +
9926 +#endif /* __ASM_ARCH_OMAP_TIMEX_H */
9927 Index: linux-2.6.35/arch/arm/plat-omap/include/mach/uncompress.h
9928 ===================================================================
9929 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
9930 +++ linux-2.6.35/arch/arm/plat-omap/include/mach/uncompress.h 2010-08-08 12:57:19.000000000 +0200
9931 @@ -0,0 +1,88 @@
9932 +/*
9933 + * arch/arm/plat-omap/include/mach/uncompress.h
9934 + *
9935 + * Serial port stubs for kernel decompress status messages
9936 + *
9937 + * Initially based on:
9938 + * linux-2.4.15-rmk1-dsplinux1.6/arch/arm/plat-omap/include/mach1510/uncompress.h
9939 + * Copyright (C) 2000 RidgeRun, Inc.
9940 + * Author: Greg Lonnon <glonnon@ridgerun.com>
9941 + *
9942 + * Rewritten by:
9943 + * Author: <source@mvista.com>
9944 + * 2004 (c) MontaVista Software, Inc.
9945 + *
9946 + * This file is licensed under the terms of the GNU General Public License
9947 + * version 2. This program is licensed "as is" without any warranty of any
9948 + * kind, whether express or implied.
9949 + */
9950 +
9951 +#include <linux/types.h>
9952 +#include <linux/serial_reg.h>
9953 +#include <plat/serial.h>
9954 +
9955 +unsigned int system_rev;
9956 +
9957 +#define UART_OMAP_MDR1 0x08 /* mode definition register */
9958 +#define OMAP_ID_730 0x355F
9959 +#define OMAP_ID_850 0x362C
9960 +#define ID_MASK 0x7fff
9961 +#define check_port(base, shift) ((base[UART_OMAP_MDR1 << shift] & 7) == 0)
9962 +#define omap_get_id() ((*(volatile unsigned int *)(0xfffed404)) >> 12) & ID_MASK
9963 +
9964 +static void putc(int c)
9965 +{
9966 + volatile u8 * uart = 0;
9967 + int shift = 2;
9968 +
9969 +#ifdef CONFIG_MACH_OMAP_PALMTE
9970 + return;
9971 +#endif
9972 +
9973 +#ifdef CONFIG_ARCH_OMAP
9974 +#ifdef CONFIG_OMAP_LL_DEBUG_UART3
9975 + uart = (volatile u8 *)(OMAP_UART3_BASE);
9976 +#elif defined(CONFIG_OMAP_LL_DEBUG_UART2)
9977 + uart = (volatile u8 *)(OMAP_UART2_BASE);
9978 +#elif defined(CONFIG_OMAP_LL_DEBUG_UART1)
9979 + uart = (volatile u8 *)(OMAP_UART1_BASE);
9980 +#elif defined(CONFIG_OMAP_LL_DEBUG_NONE)
9981 + return;
9982 +#else
9983 + return;
9984 +#endif
9985 +
9986 +#ifdef CONFIG_ARCH_OMAP1
9987 + /* Determine which serial port to use */
9988 + do {
9989 + /* MMU is not on, so cpu_is_omapXXXX() won't work here */
9990 + unsigned int omap_id = omap_get_id();
9991 +
9992 + if (omap_id == OMAP_ID_730 || omap_id == OMAP_ID_850)
9993 + shift = 0;
9994 +
9995 + if (check_port(uart, shift))
9996 + break;
9997 + /* Silent boot if no serial ports are enabled. */
9998 + return;
9999 + } while (0);
10000 +#endif /* CONFIG_ARCH_OMAP1 */
10001 +#endif
10002 +
10003 + /*
10004 + * Now, xmit each character
10005 + */
10006 + while (!(uart[UART_LSR << shift] & UART_LSR_THRE))
10007 + barrier();
10008 + uart[UART_TX << shift] = c;
10009 +}
10010 +
10011 +static inline void flush(void)
10012 +{
10013 +}
10014 +
10015 +/*
10016 + * nothing to do
10017 + */
10018 +#define arch_decomp_setup()
10019 +#define arch_decomp_wdog()
10020 Index: linux-2.6.35/arch/arm/plat-omap/include/mach/usb.h
10021 ===================================================================
10022 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
10023 +++ linux-2.6.35/arch/arm/plat-omap/include/mach/usb.h 2010-08-08 12:57:20.000000000 +0200
10024 @@ -0,0 +1,162 @@
10025 +// include/asm-arm/mach-omap/usb.h
10026 +
10027 +#ifndef __ASM_ARCH_OMAP_USB_H
10028 +#define __ASM_ARCH_OMAP_USB_H
10029 +
10030 +#include <plat/board.h>
10031 +
10032 +#define OMAP3_HS_USB_PORTS 3
10033 +enum ehci_hcd_omap_mode {
10034 + EHCI_HCD_OMAP_MODE_UNKNOWN,
10035 + EHCI_HCD_OMAP_MODE_PHY,
10036 + EHCI_HCD_OMAP_MODE_TLL,
10037 +};
10038 +
10039 +struct ehci_hcd_omap_platform_data {
10040 + enum ehci_hcd_omap_mode port_mode[OMAP3_HS_USB_PORTS];
10041 + unsigned phy_reset:1;
10042 +
10043 + /* have to be valid if phy_reset is true and portx is in phy mode */
10044 + int reset_gpio_port[OMAP3_HS_USB_PORTS];
10045 +};
10046 +
10047 +/*-------------------------------------------------------------------------*/
10048 +
10049 +#define OMAP1_OTG_BASE 0xfffb0400
10050 +#define OMAP1_UDC_BASE 0xfffb4000
10051 +#define OMAP1_OHCI_BASE 0xfffba000
10052 +
10053 +#define OMAP2_OHCI_BASE 0x4805e000
10054 +#define OMAP2_UDC_BASE 0x4805e200
10055 +#define OMAP2_OTG_BASE 0x4805e300
10056 +
10057 +#ifdef CONFIG_ARCH_OMAP1
10058 +
10059 +#define OTG_BASE OMAP1_OTG_BASE
10060 +#define UDC_BASE OMAP1_UDC_BASE
10061 +#define OMAP_OHCI_BASE OMAP1_OHCI_BASE
10062 +
10063 +#else
10064 +
10065 +#define OTG_BASE OMAP2_OTG_BASE
10066 +#define UDC_BASE OMAP2_UDC_BASE
10067 +#define OMAP_OHCI_BASE OMAP2_OHCI_BASE
10068 +
10069 +extern void usb_musb_init(void);
10070 +
10071 +extern void usb_ehci_init(struct ehci_hcd_omap_platform_data *pdata);
10072 +
10073 +#endif
10074 +
10075 +void omap_usb_init(struct omap_usb_config *pdata);
10076 +
10077 +/*-------------------------------------------------------------------------*/
10078 +
10079 +/*
10080 + * OTG and transceiver registers, for OMAPs starting with ARM926
10081 + */
10082 +#define OTG_REV (OTG_BASE + 0x00)
10083 +#define OTG_SYSCON_1 (OTG_BASE + 0x04)
10084 +# define USB2_TRX_MODE(w) (((w)>>24)&0x07)
10085 +# define USB1_TRX_MODE(w) (((w)>>20)&0x07)
10086 +# define USB0_TRX_MODE(w) (((w)>>16)&0x07)
10087 +# define OTG_IDLE_EN (1 << 15)
10088 +# define HST_IDLE_EN (1 << 14)
10089 +# define DEV_IDLE_EN (1 << 13)
10090 +# define OTG_RESET_DONE (1 << 2)
10091 +# define OTG_SOFT_RESET (1 << 1)
10092 +#define OTG_SYSCON_2 (OTG_BASE + 0x08)
10093 +# define OTG_EN (1 << 31)
10094 +# define USBX_SYNCHRO (1 << 30)
10095 +# define OTG_MST16 (1 << 29)
10096 +# define SRP_GPDATA (1 << 28)
10097 +# define SRP_GPDVBUS (1 << 27)
10098 +# define SRP_GPUVBUS(w) (((w)>>24)&0x07)
10099 +# define A_WAIT_VRISE(w) (((w)>>20)&0x07)
10100 +# define B_ASE_BRST(w) (((w)>>16)&0x07)
10101 +# define SRP_DPW (1 << 14)
10102 +# define SRP_DATA (1 << 13)
10103 +# define SRP_VBUS (1 << 12)
10104 +# define OTG_PADEN (1 << 10)
10105 +# define HMC_PADEN (1 << 9)
10106 +# define UHOST_EN (1 << 8)
10107 +# define HMC_TLLSPEED (1 << 7)
10108 +# define HMC_TLLATTACH (1 << 6)
10109 +# define OTG_HMC(w) (((w)>>0)&0x3f)
10110 +#define OTG_CTRL (OTG_BASE + 0x0c)
10111 +# define OTG_USB2_EN (1 << 29)
10112 +# define OTG_USB2_DP (1 << 28)
10113 +# define OTG_USB2_DM (1 << 27)
10114 +# define OTG_USB1_EN (1 << 26)
10115 +# define OTG_USB1_DP (1 << 25)
10116 +# define OTG_USB1_DM (1 << 24)
10117 +# define OTG_USB0_EN (1 << 23)
10118 +# define OTG_USB0_DP (1 << 22)
10119 +# define OTG_USB0_DM (1 << 21)
10120 +# define OTG_ASESSVLD (1 << 20)
10121 +# define OTG_BSESSEND (1 << 19)
10122 +# define OTG_BSESSVLD (1 << 18)
10123 +# define OTG_VBUSVLD (1 << 17)
10124 +# define OTG_ID (1 << 16)
10125 +# define OTG_DRIVER_SEL (1 << 15)
10126 +# define OTG_A_SETB_HNPEN (1 << 12)
10127 +# define OTG_A_BUSREQ (1 << 11)
10128 +# define OTG_B_HNPEN (1 << 9)
10129 +# define OTG_B_BUSREQ (1 << 8)
10130 +# define OTG_BUSDROP (1 << 7)
10131 +# define OTG_PULLDOWN (1 << 5)
10132 +# define OTG_PULLUP (1 << 4)
10133 +# define OTG_DRV_VBUS (1 << 3)
10134 +# define OTG_PD_VBUS (1 << 2)
10135 +# define OTG_PU_VBUS (1 << 1)
10136 +# define OTG_PU_ID (1 << 0)
10137 +#define OTG_IRQ_EN (OTG_BASE + 0x10) /* 16-bit */
10138 +# define DRIVER_SWITCH (1 << 15)
10139 +# define A_VBUS_ERR (1 << 13)
10140 +# define A_REQ_TMROUT (1 << 12)
10141 +# define A_SRP_DETECT (1 << 11)
10142 +# define B_HNP_FAIL (1 << 10)
10143 +# define B_SRP_TMROUT (1 << 9)
10144 +# define B_SRP_DONE (1 << 8)
10145 +# define B_SRP_STARTED (1 << 7)
10146 +# define OPRT_CHG (1 << 0)
10147 +#define OTG_IRQ_SRC (OTG_BASE + 0x14) /* 16-bit */
10148 + // same bits as in IRQ_EN
10149 +#define OTG_OUTCTRL (OTG_BASE + 0x18) /* 16-bit */
10150 +# define OTGVPD (1 << 14)
10151 +# define OTGVPU (1 << 13)
10152 +# define OTGPUID (1 << 12)
10153 +# define USB2VDR (1 << 10)
10154 +# define USB2PDEN (1 << 9)
10155 +# define USB2PUEN (1 << 8)
10156 +# define USB1VDR (1 << 6)
10157 +# define USB1PDEN (1 << 5)
10158 +# define USB1PUEN (1 << 4)
10159 +# define USB0VDR (1 << 2)
10160 +# define USB0PDEN (1 << 1)
10161 +# define USB0PUEN (1 << 0)
10162 +#define OTG_TEST (OTG_BASE + 0x20) /* 16-bit */
10163 +#define OTG_VENDOR_CODE (OTG_BASE + 0xfc) /* 16-bit */
10164 +
10165 +/*-------------------------------------------------------------------------*/
10166 +
10167 +/* OMAP1 */
10168 +#define USB_TRANSCEIVER_CTRL (0xfffe1000 + 0x0064)
10169 +# define CONF_USB2_UNI_R (1 << 8)
10170 +# define CONF_USB1_UNI_R (1 << 7)
10171 +# define CONF_USB_PORT0_R(x) (((x)>>4)&0x7)
10172 +# define CONF_USB0_ISOLATE_R (1 << 3)
10173 +# define CONF_USB_PWRDN_DM_R (1 << 2)
10174 +# define CONF_USB_PWRDN_DP_R (1 << 1)
10175 +
10176 +/* OMAP2 */
10177 +# define USB_UNIDIR 0x0
10178 +# define USB_UNIDIR_TLL 0x1
10179 +# define USB_BIDIR 0x2
10180 +# define USB_BIDIR_TLL 0x3
10181 +# define USBTXWRMODEI(port, x) ((x) << (22 - (port * 2)))
10182 +# define USBT2TLL5PI (1 << 17)
10183 +# define USB0PUENACTLOI (1 << 16)
10184 +# define USBSTANDBYCTRL (1 << 15)
10185 +
10186 +#endif /* __ASM_ARCH_OMAP_USB_H */
10187 Index: linux-2.6.35/arch/arm/plat-omap/include/mach/vram.h
10188 ===================================================================
10189 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
10190 +++ linux-2.6.35/arch/arm/plat-omap/include/mach/vram.h 2010-08-08 12:57:21.000000000 +0200
10191 @@ -0,0 +1,62 @@
10192 +/*
10193 + * VRAM manager for OMAP
10194 + *
10195 + * Copyright (C) 2009 Nokia Corporation
10196 + * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
10197 + *
10198 + * This program is free software; you can redistribute it and/or modify
10199 + * it under the terms of the GNU General Public License version 2 as
10200 + * published by the Free Software Foundation.
10201 + *
10202 + * This program is distributed in the hope that it will be useful, but
10203 + * WITHOUT ANY WARRANTY; without even the implied warranty of
10204 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
10205 + * General Public License for more details.
10206 + *
10207 + * You should have received a copy of the GNU General Public License along
10208 + * with this program; if not, write to the Free Software Foundation, Inc.,
10209 + * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
10210 + */
10211 +
10212 +#ifndef __OMAP_VRAM_H__
10213 +#define __OMAP_VRAM_H__
10214 +
10215 +#include <linux/types.h>
10216 +
10217 +#define OMAP_VRAM_MEMTYPE_SDRAM 0
10218 +#define OMAP_VRAM_MEMTYPE_SRAM 1
10219 +#define OMAP_VRAM_MEMTYPE_MAX 1
10220 +
10221 +extern int omap_vram_add_region(unsigned long paddr, size_t size);
10222 +extern int omap_vram_free(unsigned long paddr, size_t size);
10223 +extern int omap_vram_alloc(int mtype, size_t size, unsigned long *paddr);
10224 +extern int omap_vram_reserve(unsigned long paddr, size_t size);
10225 +extern void omap_vram_get_info(unsigned long *vram, unsigned long *free_vram,
10226 + unsigned long *largest_free_block);
10227 +
10228 +#ifdef CONFIG_OMAP2_VRAM
10229 +extern void omap_vram_set_sdram_vram(u32 size, u32 start);
10230 +extern void omap_vram_set_sram_vram(u32 size, u32 start);
10231 +
10232 +extern void omap_vram_reserve_sdram(void);
10233 +extern unsigned long omap_vram_reserve_sram(unsigned long sram_pstart,
10234 + unsigned long sram_vstart,
10235 + unsigned long sram_size,
10236 + unsigned long pstart_avail,
10237 + unsigned long size_avail);
10238 +#else
10239 +static inline void omap_vram_set_sdram_vram(u32 size, u32 start) { }
10240 +static inline void omap_vram_set_sram_vram(u32 size, u32 start) { }
10241 +
10242 +static inline void omap_vram_reserve_sdram(void) { }
10243 +static inline unsigned long omap_vram_reserve_sram(unsigned long sram_pstart,
10244 + unsigned long sram_vstart,
10245 + unsigned long sram_size,
10246 + unsigned long pstart_avail,
10247 + unsigned long size_avail)
10248 +{
10249 + return 0;
10250 +}
10251 +#endif
10252 +
10253 +#endif
10254 Index: linux-2.6.35/arch/arm/plat-omap/include/mach/vrfb.h
10255 ===================================================================
10256 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
10257 +++ linux-2.6.35/arch/arm/plat-omap/include/mach/vrfb.h 2010-08-08 12:57:21.000000000 +0200
10258 @@ -0,0 +1,50 @@
10259 +/*
10260 + * VRFB Rotation Engine
10261 + *
10262 + * Copyright (C) 2009 Nokia Corporation
10263 + * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
10264 + *
10265 + * This program is free software; you can redistribute it and/or modify
10266 + * it under the terms of the GNU General Public License version 2 as
10267 + * published by the Free Software Foundation.
10268 + *
10269 + * This program is distributed in the hope that it will be useful, but
10270 + * WITHOUT ANY WARRANTY; without even the implied warranty of
10271 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
10272 + * General Public License for more details.
10273 + *
10274 + * You should have received a copy of the GNU General Public License along
10275 + * with this program; if not, write to the Free Software Foundation, Inc.,
10276 + * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
10277 + */
10278 +
10279 +#ifndef __OMAP_VRFB_H__
10280 +#define __OMAP_VRFB_H__
10281 +
10282 +#define OMAP_VRFB_LINE_LEN 2048
10283 +
10284 +struct vrfb {
10285 + u8 context;
10286 + void __iomem *vaddr[4];
10287 + unsigned long paddr[4];
10288 + u16 xres;
10289 + u16 yres;
10290 + u16 xoffset;
10291 + u16 yoffset;
10292 + u8 bytespp;
10293 + bool yuv_mode;
10294 +};
10295 +
10296 +extern int omap_vrfb_request_ctx(struct vrfb *vrfb);
10297 +extern void omap_vrfb_release_ctx(struct vrfb *vrfb);
10298 +extern void omap_vrfb_adjust_size(u16 *width, u16 *height,
10299 + u8 bytespp);
10300 +extern u32 omap_vrfb_min_phys_size(u16 width, u16 height, u8 bytespp);
10301 +extern u16 omap_vrfb_max_height(u32 phys_size, u16 width, u8 bytespp);
10302 +extern void omap_vrfb_setup(struct vrfb *vrfb, unsigned long paddr,
10303 + u16 width, u16 height,
10304 + unsigned bytespp, bool yuv_mode);
10305 +extern int omap_vrfb_map_angle(struct vrfb *vrfb, u16 height, u8 rot);
10306 +extern void omap_vrfb_restore_context(void);
10307 +
10308 +#endif /* __VRFB_H */
10309 Index: linux-2.6.35/arch/arm/plat-omap/include/plat/cbus.h
10310 ===================================================================
10311 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
10312 +++ linux-2.6.35/arch/arm/plat-omap/include/plat/cbus.h 2010-08-08 12:57:22.000000000 +0200
10313 @@ -0,0 +1,31 @@
10314 +/*
10315 + * cbus.h - CBUS platform_data definition
10316 + *
10317 + * Copyright (C) 2004 - 2009 Nokia Corporation
10318 + *
10319 + * Written by Felipe Balbi <felipe.balbi@nokia.com>
10320 + *
10321 + * This file is subject to the terms and conditions of the GNU General
10322 + * Public License. See the file "COPYING" in the main directory of this
10323 + * archive for more details.
10324 + *
10325 + * This program is distributed in the hope that it will be useful,
10326 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
10327 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10328 + * GNU General Public License for more details.
10329 + *
10330 + * You should have received a copy of the GNU General Public License
10331 + * along with this program; if not, write to the Free Software
10332 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
10333 + */
10334 +
10335 +#ifndef __PLAT_CBUS_H
10336 +#define __PLAT_CBUS_H
10337 +
10338 +struct cbus_host_platform_data {
10339 + int dat_gpio;
10340 + int clk_gpio;
10341 + int sel_gpio;
10342 +};
10343 +
10344 +#endif /* __PLAT_CBUS_H */
10345 Index: linux-2.6.35/arch/arm/plat-omap/Kconfig
10346 ===================================================================
10347 --- linux-2.6.35.orig/arch/arm/plat-omap/Kconfig 2010-08-08 12:56:11.000000000 +0200
10348 +++ linux-2.6.35/arch/arm/plat-omap/Kconfig 2010-08-08 12:57:22.000000000 +0200
10349 @@ -65,6 +65,30 @@ config OMAP_RESET_CLOCKS
10350 probably do not want this option enabled until your
10351 device drivers work properly.
10352
10353 +config OMAP_BOOT_TAG
10354 + bool "OMAP bootloader information passing"
10355 + depends on ARCH_OMAP
10356 + default n
10357 + help
10358 + Say Y, if you have a bootloader which passes information
10359 + about your board and its peripheral configuration.
10360 +
10361 +config OMAP_BOOT_REASON
10362 + bool "Support for boot reason"
10363 + depends on OMAP_BOOT_TAG
10364 + default n
10365 + help
10366 + Say Y, if you want to have a procfs entry for reading the boot
10367 + reason in user-space.
10368 +
10369 +config OMAP_COMPONENT_VERSION
10370 + bool "Support for component version display"
10371 + depends on OMAP_BOOT_TAG && PROC_FS
10372 + default n
10373 + help
10374 + Say Y, if you want to have a procfs entry for reading component
10375 + versions (supplied by the bootloader) in user-space.
10376 +
10377 config OMAP_MUX
10378 bool "OMAP multiplexing support"
10379 depends on ARCH_OMAP
10380 Index: linux-2.6.35/arch/arm/plat-omap/Makefile
10381 ===================================================================
10382 --- linux-2.6.35.orig/arch/arm/plat-omap/Makefile 2010-08-08 12:56:11.000000000 +0200
10383 +++ linux-2.6.35/arch/arm/plat-omap/Makefile 2010-08-08 12:57:23.000000000 +0200
10384 @@ -22,6 +22,8 @@ obj-$(CONFIG_OMAP_IOMMU_DEBUG) += iommu-
10385
10386 obj-$(CONFIG_CPU_FREQ) += cpu-omap.o
10387 obj-$(CONFIG_OMAP_DM_TIMER) += dmtimer.o
10388 +obj-$(CONFIG_OMAP_BOOT_REASON) += bootreason.o
10389 +obj-$(CONFIG_OMAP_COMPONENT_VERSION) += component-version.o
10390 obj-$(CONFIG_OMAP_DEBUG_DEVICES) += debug-devices.o
10391 obj-$(CONFIG_OMAP_DEBUG_LEDS) += debug-leds.o
10392 i2c-omap-$(CONFIG_I2C_OMAP) := i2c.o
10393 Index: linux-2.6.35/arch/arm/include/asm/setup.h
10394 ===================================================================
10395 --- linux-2.6.35.orig/arch/arm/include/asm/setup.h 2010-08-08 12:56:16.000000000 +0200
10396 +++ linux-2.6.35/arch/arm/include/asm/setup.h 2010-08-08 12:56:28.000000000 +0200
10397 @@ -136,6 +136,13 @@ struct tag_acorn {
10398 __u8 adfsdrives;
10399 };
10400
10401 +/* TI OMAP specific information */
10402 +#define ATAG_BOARD 0x414f4d50
10403 +
10404 +struct tag_omap {
10405 + u8 data[0];
10406 +};
10407 +
10408 /* footbridge memory clock, see arch/arm/mach-footbridge/arch.c */
10409 #define ATAG_MEMCLK 0x41000402
10410
10411 @@ -162,6 +169,11 @@ struct tag {
10412 struct tag_acorn acorn;
10413
10414 /*
10415 + * OMAP specific
10416 + */
10417 + struct tag_omap omap;
10418 +
10419 + /*
10420 * DC21285 specific
10421 */
10422 struct tag_memclk memclk;
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