2 * oxnas pinctrl driver based on at91 pinctrl driver
4 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
10 #include <linux/init.h>
11 #include <linux/module.h>
13 #include <linux/of_device.h>
14 #include <linux/of_address.h>
15 #include <linux/of_irq.h>
16 #include <linux/slab.h>
17 #include <linux/interrupt.h>
18 #include <linux/irq.h>
19 #include <linux/irqdomain.h>
20 #include <linux/irqchip/chained_irq.h>
22 #include <linux/gpio.h>
23 #include <linux/pinctrl/machine.h>
24 #include <linux/pinctrl/pinconf.h>
25 #include <linux/pinctrl/pinctrl.h>
26 #include <linux/pinctrl/pinmux.h>
27 /* Since we request GPIOs from ourself */
28 #include <linux/pinctrl/consumer.h>
29 #include <linux/version.h>
33 #include <mach/utils.h>
35 #define MAX_NB_GPIO_PER_BANK 32
36 #define MAX_GPIO_BANKS 2
38 struct oxnas_gpio_chip
{
39 struct gpio_chip chip
;
40 struct pinctrl_gpio_range range
;
41 void __iomem
*regbase
; /* GPIOA/B virtual address */
42 void __iomem
*ctrlbase
; /* SYS/SEC_CTRL virtual address */
43 struct irq_domain
*domain
; /* associated irq domain */
46 #define to_oxnas_gpio_chip(c) container_of(c, struct oxnas_gpio_chip, chip)
48 static struct oxnas_gpio_chip
*gpio_chips
[MAX_GPIO_BANKS
];
50 static int gpio_banks
;
52 #define PULL_UP (1 << 0)
53 #define PULL_DOWN (1 << 1)
54 #define DEBOUNCE (1 << 2)
57 * struct oxnas_pmx_func - describes pinmux functions
58 * @name: the name of this specific function
59 * @groups: corresponding pin groups
60 * @ngroups: the number of groups
62 struct oxnas_pmx_func
{
85 OUTPUT_EN_CLEAR
= 0x20,
86 DEBOUNCE_ENABLE
= 0x24,
87 RE_IRQ_ENABLE
= 0x28, /* rising edge */
88 FE_IRQ_ENABLE
= 0x2C, /* falling edge */
89 RE_IRQ_PENDING
= 0x30, /* rising edge */
90 FE_IRQ_PENDING
= 0x34, /* falling edge */
93 PULL_SENSE
= 0x54, /* 1 up, 0 down */
96 DEBOUNCE_MASK
= 0x3FFF0000,
97 /* put hw debounce and soft config at same bit position*/
102 PINMUX_SECONDARY_SEL
= 0x14,
103 PINMUX_TERTIARY_SEL
= 0x8c,
104 PINMUX_QUATERNARY_SEL
= 0x94,
105 PINMUX_DEBUG_SEL
= 0x9c,
106 PINMUX_ALTERNATIVE_SEL
= 0xa4,
107 PINMUX_PULLUP_SEL
= 0xac,
111 * struct oxnas_pmx_pin - describes an pin mux
112 * @bank: the bank of the pin
113 * @pin: the pin number in the @bank
114 * @mux: the mux mode : gpio or periph_x of the pin i.e. alternate function.
115 * @conf: the configuration of the pin: PULL_UP, MULTIDRIVE etc...
117 struct oxnas_pmx_pin
{
125 * struct oxnas_pin_group - describes an pin group
126 * @name: the name of this specific pin group
127 * @pins_conf: the mux mode for each pin in this group. The size of this
128 * array is the same as pins.
129 * @pins: an array of discrete physical pins used in this group, taken
130 * from the driver-local pin enumeration space
131 * @npins: the number of pins in this group array, i.e. the number of
132 * elements in .pins so we can iterate over that array
134 struct oxnas_pin_group
{
136 struct oxnas_pmx_pin
*pins_conf
;
141 struct oxnas_pinctrl
{
143 struct pinctrl_dev
*pctl
;
150 struct oxnas_pmx_func
*functions
;
153 struct oxnas_pin_group
*groups
;
157 static const inline struct oxnas_pin_group
*oxnas_pinctrl_find_group_by_name(
158 const struct oxnas_pinctrl
*info
,
161 const struct oxnas_pin_group
*grp
= NULL
;
164 for (i
= 0; i
< info
->ngroups
; i
++) {
165 if (strcmp(info
->groups
[i
].name
, name
))
168 grp
= &info
->groups
[i
];
169 dev_dbg(info
->dev
, "%s: %d 0:%d\n", name
, grp
->npins
,
177 static int oxnas_get_groups_count(struct pinctrl_dev
*pctldev
)
179 struct oxnas_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
181 return info
->ngroups
;
184 static const char *oxnas_get_group_name(struct pinctrl_dev
*pctldev
,
187 struct oxnas_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
189 return info
->groups
[selector
].name
;
192 static int oxnas_get_group_pins(struct pinctrl_dev
*pctldev
, unsigned selector
,
193 const unsigned **pins
,
196 struct oxnas_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
198 if (selector
>= info
->ngroups
)
201 *pins
= info
->groups
[selector
].pins
;
202 *npins
= info
->groups
[selector
].npins
;
207 static void oxnas_pin_dbg_show(struct pinctrl_dev
*pctldev
, struct seq_file
*s
,
210 seq_printf(s
, "%s", dev_name(pctldev
->dev
));
213 static int oxnas_dt_node_to_map(struct pinctrl_dev
*pctldev
,
214 struct device_node
*np
,
215 struct pinctrl_map
**map
, unsigned *num_maps
)
217 struct oxnas_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
218 const struct oxnas_pin_group
*grp
;
219 struct pinctrl_map
*new_map
;
220 struct device_node
*parent
;
225 * first find the group of this node and check if we need create
226 * config maps for pins
228 grp
= oxnas_pinctrl_find_group_by_name(info
, np
->name
);
230 dev_err(info
->dev
, "unable to find group for node %s\n",
235 map_num
+= grp
->npins
;
236 new_map
= devm_kzalloc(pctldev
->dev
, sizeof(*new_map
) * map_num
,
245 parent
= of_get_parent(np
);
247 devm_kfree(pctldev
->dev
, new_map
);
250 new_map
[0].type
= PIN_MAP_TYPE_MUX_GROUP
;
251 new_map
[0].data
.mux
.function
= parent
->name
;
252 new_map
[0].data
.mux
.group
= np
->name
;
255 /* create config map */
257 for (i
= 0; i
< grp
->npins
; i
++) {
258 new_map
[i
].type
= PIN_MAP_TYPE_CONFIGS_PIN
;
259 new_map
[i
].data
.configs
.group_or_pin
=
260 pin_get_name(pctldev
, grp
->pins
[i
]);
261 new_map
[i
].data
.configs
.configs
= &grp
->pins_conf
[i
].conf
;
262 new_map
[i
].data
.configs
.num_configs
= 1;
265 dev_dbg(pctldev
->dev
, "maps: function %s group %s num %d\n",
266 (*map
)->data
.mux
.function
, (*map
)->data
.mux
.group
, map_num
);
271 static void oxnas_dt_free_map(struct pinctrl_dev
*pctldev
,
272 struct pinctrl_map
*map
, unsigned num_maps
)
276 static const struct pinctrl_ops oxnas_pctrl_ops
= {
277 .get_groups_count
= oxnas_get_groups_count
,
278 .get_group_name
= oxnas_get_group_name
,
279 .get_group_pins
= oxnas_get_group_pins
,
280 .pin_dbg_show
= oxnas_pin_dbg_show
,
281 .dt_node_to_map
= oxnas_dt_node_to_map
,
282 .dt_free_map
= oxnas_dt_free_map
,
285 static void __iomem
*pin_to_gpioctrl(struct oxnas_pinctrl
*info
,
288 return gpio_chips
[bank
]->regbase
;
291 static void __iomem
*pin_to_muxctrl(struct oxnas_pinctrl
*info
,
294 return gpio_chips
[bank
]->ctrlbase
;
298 static inline int pin_to_bank(unsigned pin
)
300 return pin
/ MAX_NB_GPIO_PER_BANK
;
303 static unsigned pin_to_mask(unsigned int pin
)
308 static void oxnas_mux_disable_interrupt(void __iomem
*pio
, unsigned mask
)
310 oxnas_register_clear_mask(pio
+ RE_IRQ_ENABLE
, mask
);
311 oxnas_register_clear_mask(pio
+ FE_IRQ_ENABLE
, mask
);
314 static unsigned oxnas_mux_get_pullup(void __iomem
*pio
, unsigned pin
)
316 return (readl_relaxed(pio
+ PULL_ENABLE
) & BIT(pin
)) &&
317 (readl_relaxed(pio
+ PULL_SENSE
) & BIT(pin
));
320 static void oxnas_mux_set_pullup(void __iomem
*pio
, unsigned mask
, bool on
)
323 oxnas_register_set_mask(pio
+ PULL_SENSE
, mask
);
324 oxnas_register_set_mask(pio
+ PULL_ENABLE
, mask
);
326 oxnas_register_clear_mask(pio
+ PULL_ENABLE
, mask
);
330 static bool oxnas_mux_get_pulldown(void __iomem
*pio
, unsigned pin
)
332 return (readl_relaxed(pio
+ PULL_ENABLE
) & BIT(pin
)) &&
333 (!(readl_relaxed(pio
+ PULL_SENSE
) & BIT(pin
)));
336 static void oxnas_mux_set_pulldown(void __iomem
*pio
, unsigned mask
, bool on
)
339 oxnas_register_clear_mask(pio
+ PULL_SENSE
, mask
);
340 oxnas_register_set_mask(pio
+ PULL_ENABLE
, mask
);
342 oxnas_register_clear_mask(pio
+ PULL_ENABLE
, mask
);
346 /* unfortunately debounce control are shared */
347 static bool oxnas_mux_get_debounce(void __iomem
*pio
, unsigned pin
, u32
*div
)
349 *div
= __raw_readl(pio
+ CLOCK_DIV
) & DEBOUNCE_MASK
;
350 return __raw_readl(pio
+ DEBOUNCE_ENABLE
) & BIT(pin
);
353 static void oxnas_mux_set_debounce(void __iomem
*pio
, unsigned mask
,
357 oxnas_register_value_mask(pio
+ CLOCK_DIV
, DEBOUNCE_MASK
, div
);
358 oxnas_register_set_mask(pio
+ DEBOUNCE_ENABLE
, mask
);
360 oxnas_register_clear_mask(pio
+ DEBOUNCE_ENABLE
, mask
);
365 static void oxnas_mux_set_func2(void __iomem
*cio
, unsigned mask
)
367 /* in fact, SECONDARY takes precedence, so clear others is not necessary */
368 oxnas_register_set_mask(cio
+ PINMUX_SECONDARY_SEL
, mask
);
369 oxnas_register_clear_mask(cio
+ PINMUX_TERTIARY_SEL
, mask
);
370 oxnas_register_clear_mask(cio
+ PINMUX_QUATERNARY_SEL
, mask
);
371 oxnas_register_clear_mask(cio
+ PINMUX_DEBUG_SEL
, mask
);
372 oxnas_register_clear_mask(cio
+ PINMUX_ALTERNATIVE_SEL
, mask
);
375 static void oxnas_mux_set_func3(void __iomem
*cio
, unsigned mask
)
377 oxnas_register_clear_mask(cio
+ PINMUX_SECONDARY_SEL
, mask
);
378 oxnas_register_set_mask(cio
+ PINMUX_TERTIARY_SEL
, mask
);
379 oxnas_register_clear_mask(cio
+ PINMUX_QUATERNARY_SEL
, mask
);
380 oxnas_register_clear_mask(cio
+ PINMUX_DEBUG_SEL
, mask
);
381 oxnas_register_clear_mask(cio
+ PINMUX_ALTERNATIVE_SEL
, mask
);
384 static void oxnas_mux_set_func4(void __iomem
*cio
, unsigned mask
)
386 oxnas_register_clear_mask(cio
+ PINMUX_SECONDARY_SEL
, mask
);
387 oxnas_register_clear_mask(cio
+ PINMUX_TERTIARY_SEL
, mask
);
388 oxnas_register_set_mask(cio
+ PINMUX_QUATERNARY_SEL
, mask
);
389 oxnas_register_clear_mask(cio
+ PINMUX_DEBUG_SEL
, mask
);
390 oxnas_register_clear_mask(cio
+ PINMUX_ALTERNATIVE_SEL
, mask
);
393 static void oxnas_mux_set_func_dbg(void __iomem
*cio
, unsigned mask
)
395 oxnas_register_clear_mask(cio
+ PINMUX_SECONDARY_SEL
, mask
);
396 oxnas_register_clear_mask(cio
+ PINMUX_TERTIARY_SEL
, mask
);
397 oxnas_register_clear_mask(cio
+ PINMUX_QUATERNARY_SEL
, mask
);
398 oxnas_register_set_mask(cio
+ PINMUX_DEBUG_SEL
, mask
);
399 oxnas_register_clear_mask(cio
+ PINMUX_ALTERNATIVE_SEL
, mask
);
402 static void oxnas_mux_set_func_alt(void __iomem
*cio
, unsigned mask
)
404 oxnas_register_clear_mask(cio
+ PINMUX_SECONDARY_SEL
, mask
);
405 oxnas_register_clear_mask(cio
+ PINMUX_TERTIARY_SEL
, mask
);
406 oxnas_register_clear_mask(cio
+ PINMUX_QUATERNARY_SEL
, mask
);
407 oxnas_register_clear_mask(cio
+ PINMUX_DEBUG_SEL
, mask
);
408 oxnas_register_set_mask(cio
+ PINMUX_ALTERNATIVE_SEL
, mask
);
411 static void oxnas_mux_set_gpio(void __iomem
*cio
, unsigned mask
)
413 oxnas_register_clear_mask(cio
+ PINMUX_SECONDARY_SEL
, mask
);
414 oxnas_register_clear_mask(cio
+ PINMUX_TERTIARY_SEL
, mask
);
415 oxnas_register_clear_mask(cio
+ PINMUX_QUATERNARY_SEL
, mask
);
416 oxnas_register_clear_mask(cio
+ PINMUX_DEBUG_SEL
, mask
);
417 oxnas_register_clear_mask(cio
+ PINMUX_ALTERNATIVE_SEL
, mask
);
420 static enum oxnas_mux
oxnas_mux_get_func(void __iomem
*cio
, unsigned mask
)
422 if (readl_relaxed(cio
+ PINMUX_SECONDARY_SEL
) & mask
)
423 return OXNAS_PINMUX_FUNC2
;
424 if (readl_relaxed(cio
+ PINMUX_TERTIARY_SEL
) & mask
)
425 return OXNAS_PINMUX_FUNC3
;
426 if (readl_relaxed(cio
+ PINMUX_QUATERNARY_SEL
) & mask
)
427 return OXNAS_PINMUX_FUNC4
;
428 if (readl_relaxed(cio
+ PINMUX_DEBUG_SEL
) & mask
)
429 return OXNAS_PINMUX_DEBUG
;
430 if (readl_relaxed(cio
+ PINMUX_ALTERNATIVE_SEL
) & mask
)
431 return OXNAS_PINMUX_ALT
;
432 return OXNAS_PINMUX_GPIO
;
436 static void oxnas_pin_dbg(const struct device
*dev
,
437 const struct oxnas_pmx_pin
*pin
)
441 "MF_%c%d configured as periph%c with conf = 0x%lu\n",
442 pin
->bank
+ 'A', pin
->pin
, pin
->mux
- 1 + 'A',
445 dev_dbg(dev
, "MF_%c%d configured as gpio with conf = 0x%lu\n",
446 pin
->bank
+ 'A', pin
->pin
, pin
->conf
);
450 static int pin_check_config(struct oxnas_pinctrl
*info
, const char *name
,
451 int index
, const struct oxnas_pmx_pin
*pin
)
455 /* check if it's a valid config */
456 if (pin
->bank
>= info
->nbanks
) {
457 dev_err(info
->dev
, "%s: pin conf %d bank_id %d >= nbanks %d\n",
458 name
, index
, pin
->bank
, info
->nbanks
);
462 if (pin
->pin
>= MAX_NB_GPIO_PER_BANK
) {
463 dev_err(info
->dev
, "%s: pin conf %d pin_bank_id %d >= %d\n",
464 name
, index
, pin
->pin
, MAX_NB_GPIO_PER_BANK
);
467 /* gpio always allowed */
473 if (mux
>= info
->nmux
) {
474 dev_err(info
->dev
, "%s: pin conf %d mux_id %d >= nmux %d\n",
475 name
, index
, mux
, info
->nmux
);
479 if (!(info
->mux_mask
[pin
->bank
* info
->nmux
+ mux
] & 1 << pin
->pin
)) {
480 dev_err(info
->dev
, "%s: pin conf %d mux_id %d not supported for MF_%c%d\n",
481 name
, index
, mux
, pin
->bank
+ 'A', pin
->pin
);
488 static void oxnas_mux_gpio_enable(void __iomem
*cio
, void __iomem
*pio
,
489 unsigned mask
, bool input
)
491 oxnas_mux_set_gpio(cio
, mask
);
493 writel_relaxed(mask
, pio
+ OUTPUT_EN_CLEAR
);
495 writel_relaxed(mask
, pio
+ OUTPUT_EN_SET
);
498 static void oxnas_mux_gpio_disable(void __iomem
*cio
, void __iomem
*pio
,
501 /* when switch to other function, gpio is disabled automatically */
505 static int oxnas_pmx_set_mux(struct pinctrl_dev
*pctldev
, unsigned selector
,
508 struct oxnas_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
509 const struct oxnas_pmx_pin
*pins_conf
= info
->groups
[group
].pins_conf
;
510 const struct oxnas_pmx_pin
*pin
;
511 uint32_t npins
= info
->groups
[group
].npins
;
517 dev_dbg(info
->dev
, "enable function %s group %s\n",
518 info
->functions
[selector
].name
, info
->groups
[group
].name
);
520 /* first check that all the pins of the group are valid with a valid
522 for (i
= 0; i
< npins
; i
++) {
524 ret
= pin_check_config(info
, info
->groups
[group
].name
, i
, pin
);
529 for (i
= 0; i
< npins
; i
++) {
531 oxnas_pin_dbg(info
->dev
, pin
);
533 pio
= pin_to_gpioctrl(info
, pin
->bank
);
534 cio
= pin_to_muxctrl(info
, pin
->bank
);
536 mask
= pin_to_mask(pin
->pin
);
537 oxnas_mux_disable_interrupt(pio
, mask
);
540 case OXNAS_PINMUX_GPIO
:
541 oxnas_mux_gpio_enable(cio
, pio
, mask
, 1);
543 case OXNAS_PINMUX_FUNC2
:
544 oxnas_mux_set_func2(cio
, mask
);
546 case OXNAS_PINMUX_FUNC3
:
547 oxnas_mux_set_func3(cio
, mask
);
549 case OXNAS_PINMUX_FUNC4
:
550 oxnas_mux_set_func4(cio
, mask
);
552 case OXNAS_PINMUX_DEBUG
:
553 oxnas_mux_set_func_dbg(cio
, mask
);
555 case OXNAS_PINMUX_ALT
:
556 oxnas_mux_set_func_alt(cio
, mask
);
560 oxnas_mux_gpio_disable(cio
, pio
, mask
);
566 static int oxnas_pmx_get_funcs_count(struct pinctrl_dev
*pctldev
)
568 struct oxnas_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
570 return info
->nfunctions
;
573 static const char *oxnas_pmx_get_func_name(struct pinctrl_dev
*pctldev
,
576 struct oxnas_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
578 return info
->functions
[selector
].name
;
581 static int oxnas_pmx_get_groups(struct pinctrl_dev
*pctldev
, unsigned selector
,
582 const char * const **groups
,
583 unsigned * const num_groups
)
585 struct oxnas_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
587 *groups
= info
->functions
[selector
].groups
;
588 *num_groups
= info
->functions
[selector
].ngroups
;
593 static int oxnas_gpio_request_enable(struct pinctrl_dev
*pctldev
,
594 struct pinctrl_gpio_range
*range
,
597 struct oxnas_pinctrl
*npct
= pinctrl_dev_get_drvdata(pctldev
);
598 struct oxnas_gpio_chip
*oxnas_chip
;
599 struct gpio_chip
*chip
;
603 dev_err(npct
->dev
, "invalid range\n");
607 dev_err(npct
->dev
, "missing GPIO chip in range\n");
611 oxnas_chip
= container_of(chip
, struct oxnas_gpio_chip
, chip
);
613 dev_dbg(npct
->dev
, "enable pin %u as GPIO\n", offset
);
615 mask
= 1 << (offset
- chip
->base
);
617 dev_dbg(npct
->dev
, "enable pin %u as MF_%c%d 0x%x\n",
618 offset
, 'A' + range
->id
, offset
- chip
->base
, mask
);
620 oxnas_mux_set_gpio(oxnas_chip
->ctrlbase
, mask
);
625 static void oxnas_gpio_disable_free(struct pinctrl_dev
*pctldev
,
626 struct pinctrl_gpio_range
*range
,
629 struct oxnas_pinctrl
*npct
= pinctrl_dev_get_drvdata(pctldev
);
631 dev_dbg(npct
->dev
, "disable pin %u as GPIO\n", offset
);
632 /* Set the pin to some default state, GPIO is usually default */
635 static const struct pinmux_ops oxnas_pmx_ops
= {
636 .get_functions_count
= oxnas_pmx_get_funcs_count
,
637 .get_function_name
= oxnas_pmx_get_func_name
,
638 .get_function_groups
= oxnas_pmx_get_groups
,
639 .set_mux
= oxnas_pmx_set_mux
,
640 .gpio_request_enable
= oxnas_gpio_request_enable
,
641 .gpio_disable_free
= oxnas_gpio_disable_free
,
644 static int oxnas_pinconf_get(struct pinctrl_dev
*pctldev
,
645 unsigned pin_id
, unsigned long *config
)
647 struct oxnas_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
652 dev_dbg(info
->dev
, "%s:%d, pin_id=%d, config=0x%lx", __func__
,
653 __LINE__
, pin_id
, *config
);
654 pio
= pin_to_gpioctrl(info
, pin_to_bank(pin_id
));
655 pin
= pin_id
% MAX_NB_GPIO_PER_BANK
;
657 if (oxnas_mux_get_pullup(pio
, pin
))
660 if (oxnas_mux_get_pulldown(pio
, pin
))
661 *config
|= PULL_DOWN
;
663 if (oxnas_mux_get_debounce(pio
, pin
, &div
))
664 *config
|= DEBOUNCE
| div
;
668 static int oxnas_pinconf_set(struct pinctrl_dev
*pctldev
,
669 unsigned pin_id
, unsigned long *configs
,
670 unsigned num_configs
)
672 struct oxnas_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
676 unsigned long config
;
678 pio
= pin_to_gpioctrl(info
, pin_to_bank(pin_id
));
679 mask
= pin_to_mask(pin_id
% MAX_NB_GPIO_PER_BANK
);
681 for (i
= 0; i
< num_configs
; i
++) {
685 "%s:%d, pin_id=%d, config=0x%lx",
686 __func__
, __LINE__
, pin_id
, config
);
688 if ((config
& PULL_UP
) && (config
& PULL_DOWN
))
691 oxnas_mux_set_pullup(pio
, mask
, config
& PULL_UP
);
692 oxnas_mux_set_pulldown(pio
, mask
, config
& PULL_DOWN
);
693 oxnas_mux_set_debounce(pio
, mask
, config
& DEBOUNCE
,
694 config
& DEBOUNCE_MASK
);
696 } /* for each config */
701 static void oxnas_pinconf_dbg_show(struct pinctrl_dev
*pctldev
,
702 struct seq_file
*s
, unsigned pin_id
)
707 static void oxnas_pinconf_group_dbg_show(struct pinctrl_dev
*pctldev
,
708 struct seq_file
*s
, unsigned group
)
712 static const struct pinconf_ops oxnas_pinconf_ops
= {
713 .pin_config_get
= oxnas_pinconf_get
,
714 .pin_config_set
= oxnas_pinconf_set
,
715 .pin_config_dbg_show
= oxnas_pinconf_dbg_show
,
716 .pin_config_group_dbg_show
= oxnas_pinconf_group_dbg_show
,
719 static struct pinctrl_desc oxnas_pinctrl_desc
= {
720 .pctlops
= &oxnas_pctrl_ops
,
721 .pmxops
= &oxnas_pmx_ops
,
722 .confops
= &oxnas_pinconf_ops
,
723 .owner
= THIS_MODULE
,
726 static const char *gpio_compat
= "plxtech,nas782x-gpio";
728 static void oxnas_pinctrl_child_count(struct oxnas_pinctrl
*info
,
729 struct device_node
*np
)
731 struct device_node
*child
;
733 for_each_child_of_node(np
, child
) {
734 if (of_device_is_compatible(child
, gpio_compat
)) {
738 info
->ngroups
+= of_get_child_count(child
);
743 static int oxnas_pinctrl_mux_mask(struct oxnas_pinctrl
*info
,
744 struct device_node
*np
)
750 list
= of_get_property(np
, "plxtech,mux-mask", &size
);
752 dev_err(info
->dev
, "can not read the mux-mask of %d\n", size
);
756 size
/= sizeof(*list
);
757 if (!size
|| size
% info
->nbanks
) {
758 dev_err(info
->dev
, "wrong mux mask array should be by %d\n",
762 info
->nmux
= size
/ info
->nbanks
;
764 info
->mux_mask
= devm_kzalloc(info
->dev
, sizeof(u32
) * size
, GFP_KERNEL
);
765 if (!info
->mux_mask
) {
766 dev_err(info
->dev
, "could not alloc mux_mask\n");
770 ret
= of_property_read_u32_array(np
, "plxtech,mux-mask",
771 info
->mux_mask
, size
);
773 dev_err(info
->dev
, "can not read the mux-mask of %d\n", size
);
777 static int oxnas_pinctrl_parse_groups(struct device_node
*np
,
778 struct oxnas_pin_group
*grp
,
779 struct oxnas_pinctrl
*info
, u32 index
)
781 struct oxnas_pmx_pin
*pin
;
786 dev_dbg(info
->dev
, "group(%d): %s\n", index
, np
->name
);
788 /* Initialise group */
789 grp
->name
= np
->name
;
792 * the binding format is plxtech,pins = <bank pin mux CONFIG ...>,
793 * do sanity check and calculate pins number
795 list
= of_get_property(np
, "plxtech,pins", &size
);
796 /* we do not check return since it's safe node passed down */
797 size
/= sizeof(*list
);
798 if (!size
|| size
% 4) {
799 dev_err(info
->dev
, "wrong pins number or pins and configs"
800 " should be divisible by 4\n");
804 grp
->npins
= size
/ 4;
805 pin
= grp
->pins_conf
= devm_kzalloc(info
->dev
,
806 grp
->npins
* sizeof(struct oxnas_pmx_pin
),
808 grp
->pins
= devm_kzalloc(info
->dev
, grp
->npins
* sizeof(unsigned int),
810 if (!grp
->pins_conf
|| !grp
->pins
)
813 for (i
= 0, j
= 0; i
< size
; i
+= 4, j
++) {
814 pin
->bank
= be32_to_cpu(*list
++);
815 pin
->pin
= be32_to_cpu(*list
++);
816 grp
->pins
[j
] = pin
->bank
* MAX_NB_GPIO_PER_BANK
+ pin
->pin
;
817 pin
->mux
= be32_to_cpu(*list
++);
818 pin
->conf
= be32_to_cpu(*list
++);
820 oxnas_pin_dbg(info
->dev
, pin
);
827 static int oxnas_pinctrl_parse_functions(struct device_node
*np
,
828 struct oxnas_pinctrl
*info
, u32 index
)
830 struct device_node
*child
;
831 struct oxnas_pmx_func
*func
;
832 struct oxnas_pin_group
*grp
;
834 static u32 grp_index
;
837 dev_dbg(info
->dev
, "parse function(%d): %s\n", index
, np
->name
);
839 func
= &info
->functions
[index
];
841 /* Initialise function */
842 func
->name
= np
->name
;
843 func
->ngroups
= of_get_child_count(np
);
844 if (func
->ngroups
<= 0) {
845 dev_err(info
->dev
, "no groups defined\n");
848 func
->groups
= devm_kzalloc(info
->dev
,
849 func
->ngroups
* sizeof(char *), GFP_KERNEL
);
853 for_each_child_of_node(np
, child
) {
854 func
->groups
[i
] = child
->name
;
855 grp
= &info
->groups
[grp_index
++];
856 ret
= oxnas_pinctrl_parse_groups(child
, grp
, info
, i
++);
864 static struct of_device_id oxnas_pinctrl_of_match
[] = {
865 { .compatible
= "plxtech,nas782x-pinctrl"},
869 static int oxnas_pinctrl_probe_dt(struct platform_device
*pdev
,
870 struct oxnas_pinctrl
*info
)
875 struct device_node
*np
= pdev
->dev
.of_node
;
876 struct device_node
*child
;
881 info
->dev
= &pdev
->dev
;
883 oxnas_pinctrl_child_count(info
, np
);
885 if (info
->nbanks
< 1) {
886 dev_err(&pdev
->dev
, "you need to specify atleast one gpio-controller\n");
890 ret
= oxnas_pinctrl_mux_mask(info
, np
);
894 dev_dbg(&pdev
->dev
, "nmux = %d\n", info
->nmux
);
896 dev_dbg(&pdev
->dev
, "mux-mask\n");
897 tmp
= info
->mux_mask
;
898 for (i
= 0; i
< info
->nbanks
; i
++)
899 for (j
= 0; j
< info
->nmux
; j
++, tmp
++)
900 dev_dbg(&pdev
->dev
, "%d:%d\t0x%x\n", i
, j
, tmp
[0]);
902 dev_dbg(&pdev
->dev
, "nfunctions = %d\n", info
->nfunctions
);
903 dev_dbg(&pdev
->dev
, "ngroups = %d\n", info
->ngroups
);
904 info
->functions
= devm_kzalloc(&pdev
->dev
, info
->nfunctions
*
905 sizeof(struct oxnas_pmx_func
),
907 if (!info
->functions
)
910 info
->groups
= devm_kzalloc(&pdev
->dev
, info
->ngroups
*
911 sizeof(struct oxnas_pin_group
),
916 dev_dbg(&pdev
->dev
, "nbanks = %d\n", info
->nbanks
);
917 dev_dbg(&pdev
->dev
, "nfunctions = %d\n", info
->nfunctions
);
918 dev_dbg(&pdev
->dev
, "ngroups = %d\n", info
->ngroups
);
922 for_each_child_of_node(np
, child
) {
923 if (of_device_is_compatible(child
, gpio_compat
))
925 ret
= oxnas_pinctrl_parse_functions(child
, info
, i
++);
927 dev_err(&pdev
->dev
, "failed to parse function\n");
935 static int oxnas_pinctrl_probe(struct platform_device
*pdev
)
937 struct oxnas_pinctrl
*info
;
938 struct pinctrl_pin_desc
*pdesc
;
941 info
= devm_kzalloc(&pdev
->dev
, sizeof(*info
), GFP_KERNEL
);
945 ret
= oxnas_pinctrl_probe_dt(pdev
, info
);
950 * We need all the GPIO drivers to probe FIRST, or we will not be able
951 * to obtain references to the struct gpio_chip * for them, and we
952 * need this to proceed.
954 for (i
= 0; i
< info
->nbanks
; i
++) {
955 if (!gpio_chips
[i
]) {
957 "GPIO chip %d not registered yet\n", i
);
958 devm_kfree(&pdev
->dev
, info
);
959 return -EPROBE_DEFER
;
963 oxnas_pinctrl_desc
.name
= dev_name(&pdev
->dev
);
964 oxnas_pinctrl_desc
.npins
= info
->nbanks
* MAX_NB_GPIO_PER_BANK
;
965 oxnas_pinctrl_desc
.pins
= pdesc
=
966 devm_kzalloc(&pdev
->dev
, sizeof(*pdesc
) *
967 oxnas_pinctrl_desc
.npins
, GFP_KERNEL
);
969 if (!oxnas_pinctrl_desc
.pins
)
972 for (i
= 0 , k
= 0; i
< info
->nbanks
; i
++) {
973 for (j
= 0; j
< MAX_NB_GPIO_PER_BANK
; j
++, k
++) {
975 pdesc
->name
= kasprintf(GFP_KERNEL
, "MF_%c%d", i
+ 'A',
981 platform_set_drvdata(pdev
, info
);
982 info
->pctl
= pinctrl_register(&oxnas_pinctrl_desc
, &pdev
->dev
, info
);
985 dev_err(&pdev
->dev
, "could not register OX820 pinctrl driver\n");
990 /* We will handle a range of GPIO pins */
991 for (i
= 0; i
< info
->nbanks
; i
++)
992 pinctrl_add_gpio_range(info
->pctl
, &gpio_chips
[i
]->range
);
994 dev_info(&pdev
->dev
, "initialized OX820 pinctrl driver\n");
1002 static int oxnas_pinctrl_remove(struct platform_device
*pdev
)
1004 struct oxnas_pinctrl
*info
= platform_get_drvdata(pdev
);
1006 pinctrl_unregister(info
->pctl
);
1011 static int oxnas_gpio_request(struct gpio_chip
*chip
, unsigned offset
)
1014 * Map back to global GPIO space and request muxing, the direction
1015 * parameter does not matter for this controller.
1017 int gpio
= chip
->base
+ offset
;
1018 int bank
= chip
->base
/ chip
->ngpio
;
1020 dev_dbg(chip
->dev
, "%s:%d MF_%c%d(%d)\n", __func__
, __LINE__
,
1021 'A' + bank
, offset
, gpio
);
1023 return pinctrl_request_gpio(gpio
);
1026 static void oxnas_gpio_free(struct gpio_chip
*chip
, unsigned offset
)
1028 int gpio
= chip
->base
+ offset
;
1030 pinctrl_free_gpio(gpio
);
1033 static int oxnas_gpio_direction_input(struct gpio_chip
*chip
, unsigned offset
)
1035 struct oxnas_gpio_chip
*oxnas_gpio
= to_oxnas_gpio_chip(chip
);
1036 void __iomem
*pio
= oxnas_gpio
->regbase
;
1038 writel_relaxed(BIT(offset
), pio
+ OUTPUT_EN_CLEAR
);
1042 static int oxnas_gpio_get(struct gpio_chip
*chip
, unsigned offset
)
1044 struct oxnas_gpio_chip
*oxnas_gpio
= to_oxnas_gpio_chip(chip
);
1045 void __iomem
*pio
= oxnas_gpio
->regbase
;
1046 unsigned mask
= 1 << offset
;
1049 pdsr
= readl_relaxed(pio
+ INPUT_VALUE
);
1050 return (pdsr
& mask
) != 0;
1053 static void oxnas_gpio_set(struct gpio_chip
*chip
, unsigned offset
,
1056 struct oxnas_gpio_chip
*oxnas_gpio
= to_oxnas_gpio_chip(chip
);
1057 void __iomem
*pio
= oxnas_gpio
->regbase
;
1060 writel_relaxed(BIT(offset
), pio
+ OUTPUT_SET
);
1062 writel_relaxed(BIT(offset
), pio
+ OUTPUT_CLEAR
);
1066 static int oxnas_gpio_direction_output(struct gpio_chip
*chip
, unsigned offset
,
1069 struct oxnas_gpio_chip
*oxnas_gpio
= to_oxnas_gpio_chip(chip
);
1070 void __iomem
*pio
= oxnas_gpio
->regbase
;
1073 writel_relaxed(BIT(offset
), pio
+ OUTPUT_SET
);
1075 writel_relaxed(BIT(offset
), pio
+ OUTPUT_CLEAR
);
1077 writel_relaxed(BIT(offset
), pio
+ OUTPUT_EN_SET
);
1082 static int oxnas_gpio_to_irq(struct gpio_chip
*chip
, unsigned offset
)
1084 struct oxnas_gpio_chip
*oxnas_gpio
= to_oxnas_gpio_chip(chip
);
1087 if (offset
< chip
->ngpio
)
1088 virq
= irq_create_mapping(oxnas_gpio
->domain
, offset
);
1092 dev_dbg(chip
->dev
, "%s: request IRQ for GPIO %d, return %d\n",
1093 chip
->label
, offset
+ chip
->base
, virq
);
1097 #ifdef CONFIG_DEBUG_FS
1098 static void oxnas_gpio_dbg_show(struct seq_file
*s
, struct gpio_chip
*chip
)
1100 enum oxnas_mux mode
;
1102 struct oxnas_gpio_chip
*oxnas_gpio
= to_oxnas_gpio_chip(chip
);
1103 void __iomem
*pio
= oxnas_gpio
->regbase
;
1104 void __iomem
*cio
= oxnas_gpio
->ctrlbase
;
1106 for (i
= 0; i
< chip
->ngpio
; i
++) {
1107 unsigned pin
= chip
->base
+ i
;
1108 unsigned mask
= pin_to_mask(pin
);
1109 const char *gpio_label
;
1112 gpio_label
= gpiochip_is_requested(chip
, i
);
1116 mode
= oxnas_mux_get_func(cio
, mask
);
1117 seq_printf(s
, "[%s] GPIO%s%d: ",
1118 gpio_label
, chip
->label
, i
);
1119 if (mode
== OXNAS_PINMUX_GPIO
) {
1120 pdsr
= readl_relaxed(pio
+ INPUT_VALUE
);
1122 seq_printf(s
, "[gpio] %s\n",
1126 seq_printf(s
, "[periph %c]\n",
1132 #define oxnas_gpio_dbg_show NULL
1135 /* Several AIC controller irqs are dispatched through this GPIO handler.
1136 * To use any AT91_PIN_* as an externally triggered IRQ, first call
1137 * oxnas_set_gpio_input() then maybe enable its glitch filter.
1138 * Then just request_irq() with the pin ID; it works like any ARM IRQ
1142 static void gpio_irq_mask(struct irq_data
*d
)
1144 struct oxnas_gpio_chip
*oxnas_gpio
= irq_data_get_irq_chip_data(d
);
1145 void __iomem
*pio
= oxnas_gpio
->regbase
;
1146 unsigned mask
= 1 << d
->hwirq
;
1147 unsigned type
= irqd_get_trigger_type(d
);
1149 /* FIXME: need proper lock */
1150 if (type
& IRQ_TYPE_EDGE_RISING
)
1151 oxnas_register_clear_mask(pio
+ RE_IRQ_ENABLE
, mask
);
1152 if (type
& IRQ_TYPE_EDGE_FALLING
)
1153 oxnas_register_clear_mask(pio
+ FE_IRQ_ENABLE
, mask
);
1156 static void gpio_irq_unmask(struct irq_data
*d
)
1158 struct oxnas_gpio_chip
*oxnas_gpio
= irq_data_get_irq_chip_data(d
);
1159 void __iomem
*pio
= oxnas_gpio
->regbase
;
1160 unsigned mask
= 1 << d
->hwirq
;
1161 unsigned type
= irqd_get_trigger_type(d
);
1163 /* FIXME: need proper lock */
1164 if (type
& IRQ_TYPE_EDGE_RISING
)
1165 oxnas_register_set_mask(pio
+ RE_IRQ_ENABLE
, mask
);
1166 if (type
& IRQ_TYPE_EDGE_FALLING
)
1167 oxnas_register_set_mask(pio
+ FE_IRQ_ENABLE
, mask
);
1171 static int gpio_irq_type(struct irq_data
*d
, unsigned type
)
1173 if ((type
& IRQ_TYPE_EDGE_BOTH
) == 0) {
1174 pr_warn("OX820: Unsupported type for irq %d\n",
1175 gpio_to_irq(d
->irq
));
1178 /* seems no way to set trigger type without enable irq, so leave it to unmask time */
1183 static struct irq_chip gpio_irqchip
= {
1185 .irq_disable
= gpio_irq_mask
,
1186 .irq_mask
= gpio_irq_mask
,
1187 .irq_unmask
= gpio_irq_unmask
,
1188 .irq_set_type
= gpio_irq_type
,
1191 #if LINUX_VERSION_CODE < KERNEL_VERSION(4,2,0)
1192 static void gpio_irq_handler(unsigned irq
, struct irq_desc
*desc
)
1194 static void gpio_irq_handler(struct irq_desc
*desc
)
1197 struct irq_chip
*chip
= irq_desc_get_chip(desc
);
1198 struct irq_data
*idata
= irq_desc_get_irq_data(desc
);
1199 struct oxnas_gpio_chip
*oxnas_gpio
= irq_data_get_irq_chip_data(idata
);
1200 void __iomem
*pio
= oxnas_gpio
->regbase
;
1204 chained_irq_enter(chip
, desc
);
1206 /* TODO: see if it works */
1207 isr
= readl_relaxed(pio
+ IRQ_PENDING
);
1210 /* acks pending interrupts */
1211 writel_relaxed(isr
, pio
+ IRQ_PENDING
);
1213 for_each_set_bit(n
, &isr
, BITS_PER_LONG
) {
1214 generic_handle_irq(irq_find_mapping(oxnas_gpio
->domain
,
1218 chained_irq_exit(chip
, desc
);
1219 /* now it may re-trigger */
1223 * This lock class tells lockdep that GPIO irqs are in a different
1224 * category than their parents, so it won't report false recursion.
1226 static struct lock_class_key gpio_lock_class
;
1228 static int oxnas_gpio_irq_map(struct irq_domain
*h
, unsigned int virq
,
1231 struct oxnas_gpio_chip
*oxnas_gpio
= h
->host_data
;
1233 irq_set_lockdep_class(virq
, &gpio_lock_class
);
1235 irq_set_chip_and_handler(virq
, &gpio_irqchip
, handle_edge_irq
);
1236 #if LINUX_VERSION_CODE < KERNEL_VERSION(4,2,0)
1237 set_irq_flags(virq
, IRQF_VALID
);
1239 irq_set_chip_data(virq
, oxnas_gpio
);
1244 static int oxnas_gpio_irq_domain_xlate(struct irq_domain
*d
,
1245 struct device_node
*ctrlr
,
1247 unsigned int intsize
,
1248 irq_hw_number_t
*out_hwirq
,
1249 unsigned int *out_type
)
1251 struct oxnas_gpio_chip
*oxnas_gpio
= d
->host_data
;
1253 int pin
= oxnas_gpio
->chip
.base
+ intspec
[0];
1255 if (WARN_ON(intsize
< 2))
1257 *out_hwirq
= intspec
[0];
1258 *out_type
= intspec
[1] & IRQ_TYPE_SENSE_MASK
;
1260 ret
= gpio_request(pin
, ctrlr
->full_name
);
1264 ret
= gpio_direction_input(pin
);
1271 static struct irq_domain_ops oxnas_gpio_ops
= {
1272 .map
= oxnas_gpio_irq_map
,
1273 .xlate
= oxnas_gpio_irq_domain_xlate
,
1276 static int oxnas_gpio_of_irq_setup(struct device_node
*node
,
1277 struct oxnas_gpio_chip
*oxnas_gpio
,
1280 /* Disable irqs of this controller */
1281 writel_relaxed(0, oxnas_gpio
->regbase
+ RE_IRQ_ENABLE
);
1282 writel_relaxed(0, oxnas_gpio
->regbase
+ FE_IRQ_ENABLE
);
1284 /* Setup irq domain */
1285 oxnas_gpio
->domain
= irq_domain_add_linear(node
, oxnas_gpio
->chip
.ngpio
,
1286 &oxnas_gpio_ops
, oxnas_gpio
);
1287 if (!oxnas_gpio
->domain
)
1288 panic("oxnas_gpio: couldn't allocate irq domain (DT).\n");
1290 irq_set_chip_data(irq
, oxnas_gpio
);
1291 irq_set_chained_handler(irq
, gpio_irq_handler
);
1296 /* This structure is replicated for each GPIO block allocated at probe time */
1297 static struct gpio_chip oxnas_gpio_template
= {
1298 .request
= oxnas_gpio_request
,
1299 .free
= oxnas_gpio_free
,
1300 .direction_input
= oxnas_gpio_direction_input
,
1301 .get
= oxnas_gpio_get
,
1302 .direction_output
= oxnas_gpio_direction_output
,
1303 .set
= oxnas_gpio_set
,
1304 .to_irq
= oxnas_gpio_to_irq
,
1305 .dbg_show
= oxnas_gpio_dbg_show
,
1307 .ngpio
= MAX_NB_GPIO_PER_BANK
,
1310 static struct of_device_id oxnas_gpio_of_match
[] = {
1311 { .compatible
= "plxtech,nas782x-gpio"},
1315 static int oxnas_gpio_probe(struct platform_device
*pdev
)
1317 struct device_node
*np
= pdev
->dev
.of_node
;
1318 struct resource
*res
;
1319 struct oxnas_gpio_chip
*oxnas_chip
= NULL
;
1320 struct gpio_chip
*chip
;
1321 struct pinctrl_gpio_range
*range
;
1324 int alias_idx
= of_alias_get_id(np
, "gpio");
1328 BUG_ON(alias_idx
>= ARRAY_SIZE(gpio_chips
));
1329 if (gpio_chips
[alias_idx
]) {
1334 irq
= platform_get_irq(pdev
, 0);
1340 oxnas_chip
= devm_kzalloc(&pdev
->dev
, sizeof(*oxnas_chip
), GFP_KERNEL
);
1346 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1347 oxnas_chip
->regbase
= devm_ioremap_resource(&pdev
->dev
, res
);
1348 if (IS_ERR(oxnas_chip
->regbase
)) {
1349 ret
= PTR_ERR(oxnas_chip
->regbase
);
1353 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 1);
1354 oxnas_chip
->ctrlbase
= devm_ioremap_resource(&pdev
->dev
, res
);
1355 if (IS_ERR(oxnas_chip
->ctrlbase
)) {
1356 ret
= PTR_ERR(oxnas_chip
->ctrlbase
);
1360 oxnas_chip
->chip
= oxnas_gpio_template
;
1362 chip
= &oxnas_chip
->chip
;
1364 chip
->label
= dev_name(&pdev
->dev
);
1365 chip
->dev
= &pdev
->dev
;
1366 chip
->owner
= THIS_MODULE
;
1367 chip
->base
= alias_idx
* MAX_NB_GPIO_PER_BANK
;
1369 if (!of_property_read_u32(np
, "#gpio-lines", &ngpio
)) {
1370 if (ngpio
> MAX_NB_GPIO_PER_BANK
)
1371 pr_err("oxnas_gpio.%d, gpio-nb >= %d failback to %d\n",
1372 alias_idx
, MAX_NB_GPIO_PER_BANK
,
1373 MAX_NB_GPIO_PER_BANK
);
1375 chip
->ngpio
= ngpio
;
1378 names
= devm_kzalloc(&pdev
->dev
, sizeof(char *) * chip
->ngpio
,
1386 for (i
= 0; i
< chip
->ngpio
; i
++)
1387 names
[i
] = kasprintf(GFP_KERNEL
, "MF_%c%d", alias_idx
+ 'A', i
);
1389 chip
->names
= (const char *const *)names
;
1391 range
= &oxnas_chip
->range
;
1392 range
->name
= chip
->label
;
1393 range
->id
= alias_idx
;
1394 range
->pin_base
= range
->base
= range
->id
* MAX_NB_GPIO_PER_BANK
;
1396 range
->npins
= chip
->ngpio
;
1399 ret
= gpiochip_add(chip
);
1403 gpio_chips
[alias_idx
] = oxnas_chip
;
1404 gpio_banks
= max(gpio_banks
, alias_idx
+ 1);
1406 oxnas_gpio_of_irq_setup(np
, oxnas_chip
, irq
);
1408 dev_info(&pdev
->dev
, "at address %p\n", oxnas_chip
->regbase
);
1412 dev_err(&pdev
->dev
, "Failure %i for GPIO %i\n", ret
, alias_idx
);
1417 static struct platform_driver oxnas_gpio_driver
= {
1419 .name
= "gpio-oxnas",
1420 .owner
= THIS_MODULE
,
1421 .of_match_table
= of_match_ptr(oxnas_gpio_of_match
),
1423 .probe
= oxnas_gpio_probe
,
1426 static struct platform_driver oxnas_pinctrl_driver
= {
1428 .name
= "pinctrl-oxnas",
1429 .owner
= THIS_MODULE
,
1430 .of_match_table
= of_match_ptr(oxnas_pinctrl_of_match
),
1432 .probe
= oxnas_pinctrl_probe
,
1433 .remove
= oxnas_pinctrl_remove
,
1436 static int __init
oxnas_pinctrl_init(void)
1440 ret
= platform_driver_register(&oxnas_gpio_driver
);
1443 return platform_driver_register(&oxnas_pinctrl_driver
);
1445 arch_initcall(oxnas_pinctrl_init
);
1447 static void __exit
oxnas_pinctrl_exit(void)
1449 platform_driver_unregister(&oxnas_pinctrl_driver
);
1452 module_exit(oxnas_pinctrl_exit
);
1453 MODULE_AUTHOR("Ma Hajun <mahaijuns@gmail.com>");
1454 MODULE_DESCRIPTION("Plxtech Nas782x pinctrl driver");
1455 MODULE_LICENSE("GPL v2");