target/linux/oxnas/patches-5.4/340-oxnas-pcie.patch

   1 --- a/drivers/pci/controller/Kconfig
   2 +++ b/drivers/pci/controller/Kconfig
   3 @@ -48,6 +48,11 @@ config PCIE_CADENCE_EP
   4           endpoint mode. This PCIe controller may be embedded into many
   5           different vendors SoCs.
   6
   7 +config PCIE_OXNAS
   8 +       bool "PLX Oxnas PCIe controller"
   9 +       depends on ARCH_OXNAS
  10 +       select PCIEPORTBUS
  11 +
  12  endmenu
  13
  14  config PCIE_XILINX_NWL
  15 --- a/drivers/pci/controller/Makefile
  16 +++ b/drivers/pci/controller/Makefile
  17 @@ -28,6 +28,7 @@ obj-$(CONFIG_PCIE_ROCKCHIP_EP) += pcie-r
  18  obj-$(CONFIG_PCIE_ROCKCHIP_HOST) += pcie-rockchip-host.o
  19  obj-$(CONFIG_PCIE_MEDIATEK) += pcie-mediatek.o
  20  obj-$(CONFIG_PCIE_MOBIVEIL) += pcie-mobiveil.o
  21 +obj-$(CONFIG_PCIE_OXNAS) += pcie-oxnas.o
  22  obj-$(CONFIG_PCIE_TANGO_SMP8759) += pcie-tango.o
  23  obj-$(CONFIG_VMD) += vmd.o
  24  # pcie-hisi.o quirks are needed even without CONFIG_PCIE_DW
  25 --- a/arch/arm/boot/dts/ox820.dtsi
  26 +++ b/arch/arm/boot/dts/ox820.dtsi
  27 @@ -289,7 +289,7 @@
  28                         #address-cells = <1>;
  29                         #size-cells = <1>;
  30                         compatible = "simple-bus";
  31 -                       ranges = <0 0x47000000 0x1000000>;
  32 +                       ranges = <0 0x47000000 0x2000>;
  33
  34                         scu: scu@0 {
  35                                 compatible = "arm,arm11mp-scu";
  36 @@ -318,5 +318,86 @@
  37                                       <0x100 0x500>;
  38                         };
  39                 };
  40 +
  41 +               pcie0: pcie-controller@47c00000 {
  42 +                       compatible = "plxtech,nas782x-pcie";
  43 +                       device_type = "pci";
  44 +                       #address-cells = <3>;
  45 +                       #size-cells = <2>;
  46 +
  47 +                       /*              flag & space    bus address     host address    size */
  48 +                       ranges = <      0x82000000      0 0x48000000    0x48000000      0 0x2000000
  49 +                                       0xC2000000      0 0x4A000000    0x4A000000      0 0x1E00000
  50 +                                       0x81000000      0 0x4BE00000    0x4BE00000      0 0x0100000
  51 +                                       0x80000000      0 0x4BF00000    0x4BF00000      0 0x0100000>;
  52 +
  53 +                       bus-range = <0x00 0x7f>;
  54 +
  55 +                       /*      cfg                     inbound translator      */
  56 +                       reg =   <0x47c00000 0x1000>,    <0x47d00000 0x100>;
  57 +
  58 +                       phys = <&pcie_phy>;
  59 +                       phy-names = "pcie-phy";
  60 +
  61 +                       #interrupt-cells = <1>;
  62 +                       /* wild card mask, match all bus address & interrupt specifier */
  63 +                       /* format: bus address mask, interrupt specifier mask */
  64 +                       /* each bit 1 means need match, 0 means ignored when match */
  65 +                       interrupt-map-mask = <0 0 0 0>;
  66 +                       /* format: a list of: bus address, interrupt specifier,
  67 +                        * parent interrupt controller & specifier */
  68 +                       interrupt-map = <0 0 0 0 &gic 0 19 0x304>;
  69 +                       gpios = <&gpio1 12 0>;
  70 +                       clocks = <&stdclk CLK_820_PCIEA>, <&pllb>;
  71 +                       clock-names = "pcie", "busclk";
  72 +                       resets = <&reset RESET_PCIEA>;
  73 +                       reset-names = "pcie";
  74 +
  75 +                       plxtech,pcie-hcsl-bit = <2>;
  76 +                       plxtech,pcie-ctrl-offset = <0x120>;
  77 +                       plxtech,pcie-outbound-offset = <0x138>;
  78 +                       status = "disabled";
  79 +               };
  80 +
  81 +               pcie1: pcie-controller@47e00000 {
  82 +                       compatible = "plxtech,nas782x-pcie";
  83 +                       device_type = "pci";
  84 +                       #address-cells = <3>;
  85 +                       #size-cells = <2>;
  86 +
  87 +                       /*              flag & space    bus address     host address    size */
  88 +                       ranges = <      0x82000000      0 0x4C000000    0x4C000000      0 0x2000000
  89 +                                       0xC2000000      0 0x4E000000    0x4E000000      0 0x1E00000
  90 +                                       0x81000000      0 0x4FE00000    0x4FE00000      0 0x0100000
  91 +                                       0x80000000      0 0x4FF00000    0x4FF00000      0 0x0100000>;
  92 +
  93 +                       bus-range = <0x80 0xff>;
  94 +
  95 +                       /*      cfg                     inbound translator      */
  96 +                       reg =   <0x47e00000 0x1000>,    <0x47f00000 0x100>;
  97 +
  98 +                       phys = <&pcie_phy>;
  99 +                       phy-names = "pcie-phy";
 100 +
 101 +                       #interrupt-cells = <1>;
 102 +                       /* wild card mask, match all bus address & interrupt specifier */
 103 +                       /* format: bus address mask, interrupt specifier mask */
 104 +                       /* each bit 1 means need match, 0 means ignored when match */
 105 +                       interrupt-map-mask = <0 0 0 0>;
 106 +                       /* format: a list of: bus address, interrupt specifier,
 107 +                        * parent interrupt controller & specifier */
 108 +                       interrupt-map = <0 0 0 0 &gic 0 20 0x304>;
 109 +
 110 +                       /* gpios = <&gpio1 12 0>; */
 111 +                       clocks = <&stdclk CLK_820_PCIEB>, <&pllb>;
 112 +                       clock-names = "pcie", "busclk";
 113 +                       resets = <&reset RESET_PCIEB>;
 114 +                       reset-names = "pcie";
 115 +
 116 +                       plxtech,pcie-hcsl-bit = <3>;
 117 +                       plxtech,pcie-ctrl-offset = <0x124>;
 118 +                       plxtech,pcie-outbound-offset = <0x174>;
 119 +                       status = "disabled";
 120 +               };
 121         };
 122  };