target/linux/ramips/dts/mt7620a_lb-link_bl-w1200.dts

   1 // SPDX-License-Identifier: GPL-2.0-only
   2
   3 #include "mt7620a.dtsi"
   4
   5 #include <dt-bindings/gpio/gpio.h>
   6 #include <dt-bindings/input/input.h>
   7
   8 / {
   9         compatible = "lb-link,bl-w1200", "ralink,mt7620a-soc";
  10         model = "LB-Link BL-W1200";
  11
  12         aliases {
  13                 led-boot = &led_wps;
  14                 led-failsafe = &led_wps;
  15                 led-upgrade = &led_wps;
  16         };
  17
  18         keys {
  19                 compatible = "gpio-keys";
  20
  21                 reset_wps {
  22                         label = "reset_wps";
  23                         gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
  24                         linux,code = <KEY_RESTART>;
  25                 };
  26         };
  27
  28         leds {
  29                 compatible = "gpio-leds";
  30
  31                 led_wps: wps {
  32                         label = "green:wps";
  33                         gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
  34                 };
  35         };
  36 };
  37
  38 &gpio1 {
  39         status = "okay";
  40 };
  41
  42 &spi0 {
  43         status = "okay";
  44
  45         flash@0 {
  46                 compatible = "jedec,spi-nor";
  47                 reg = <0>;
  48                 spi-max-frequency = <50000000>;
  49
  50                 partitions {
  51                         compatible = "fixed-partitions";
  52                         #address-cells = <1>;
  53                         #size-cells = <1>;
  54
  55                         partition@0 {
  56                                 label = "u-boot";
  57                                 reg = <0x0 0x30000>;
  58                                 read-only;
  59                         };
  60
  61                         partition@30000 {
  62                                 label = "config";
  63                                 reg = <0x30000 0x10000>;
  64                                 read-only;
  65                         };
  66
  67                         factory: partition@40000 {
  68                                 label = "factory";
  69                                 reg = <0x40000 0x10000>;
  70                                 read-only;
  71
  72                                 nvmem-layout {
  73                                         compatible = "fixed-layout";
  74                                         #address-cells = <1>;
  75                                         #size-cells = <1>;
  76
  77                                         eeprom_factory_0: eeprom@0 {
  78                                                 reg = <0x0 0x200>;
  79                                         };
  80
  81                                         eeprom_factory_8000: eeprom@8000 {
  82                                                 reg = <0x8000 0x200>;
  83                                         };
  84
  85                                         macaddr_factory_28: macaddr@28 {
  86                                                 reg = <0x28 0x6>;
  87                                         };
  88                                 };
  89                         };
  90
  91                         partition@50000 {
  92                                 compatible = "denx,uimage";
  93                                 label = "firmware";
  94                                 reg = <0x50000 0x7b0000>;
  95                         };
  96                 };
  97         };
  98 };
  99
 100 &state_default {
 101         gpio {
 102                 groups = "uartf", "spi refclk";
 103                 function = "gpio";
 104         };
 105 };
 106
 107 &ethernet {
 108         pinctrl-names = "default";
 109         pinctrl-0 = <&rgmii2_pins &mdio_pins>;
 110
 111         nvmem-cells = <&macaddr_factory_28>;
 112         nvmem-cell-names = "mac-address";
 113
 114         mediatek,portmap = "wllll";
 115
 116         port@5 {
 117                 status = "okay";
 118                 mediatek,fixed-link = <1000 1 1 1>;
 119                 phy-mode = "rgmii";
 120         };
 121
 122         mdio-bus {
 123                 status = "okay";
 124
 125                 ethernet-phy@0 {
 126                         reg = <0>;
 127                         phy-mode = "rgmii";
 128                 };
 129
 130                 ethernet-phy@1 {
 131                         reg = <1>;
 132                         phy-mode = "rgmii";
 133                 };
 134
 135                 ethernet-phy@2 {
 136                         reg = <2>;
 137                         phy-mode = "rgmii";
 138                 };
 139
 140                 ethernet-phy@3 {
 141                         reg = <3>;
 142                         phy-mode = "rgmii";
 143                 };
 144
 145                 ethernet-phy@4 {
 146                         reg = <4>;
 147                         phy-mode = "rgmii";
 148                 };
 149
 150                 ethernet-phy@1f {
 151                         reg = <0x1f>;
 152                         phy-mode = "rgmii";
 153                 };
 154         };
 155 };
 156
 157 &gsw {
 158         mediatek,ephy-base = /bits/ 8 <12>;
 159 };
 160
 161 &wmac {
 162         nvmem-cells = <&eeprom_factory_0>;
 163         nvmem-cell-names = "eeprom";
 164 };
 165
 166 &pcie {
 167         status = "okay";
 168 };
 169
 170 &pcie0 {
 171         wifi@0,0 {
 172                 compatible = "mediatek,mt76";
 173                 reg = <0x0000 0 0 0 0>;
 174                 ieee80211-freq-limit = <5000000 6000000>;
 175                 nvmem-cells = <&eeprom_factory_8000>;
 176                 nvmem-cell-names = "eeprom";
 177
 178                 led {
 179                         led-sources = <2>;
 180                         led-active-low;
 181                 };
 182         };
 183 };
 184
 185 &ehci {
 186         status = "okay";
 187 };
 188
 189 &ohci {
 190         status = "okay";
 191 };