3c6f7c582ef7ab85de1ba3976a499bddd9271029
[openwrt/openwrt.git] / target / linux / ramips / dts / mt7620a_planex_mzk-750dhp.dts
1 #include "mt7620a.dtsi"
2
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/input/input.h>
5
6 / {
7 compatible = "planex,mzk-750dhp", "ralink,mt7620a-soc";
8 model = "Planex MZK-750DHP";
9
10 aliases {
11 led-boot = &led_power;
12 led-failsafe = &led_power;
13 led-running = &led_power;
14 led-upgrade = &led_power;
15 };
16
17 leds {
18 compatible = "gpio-leds";
19
20 wps {
21 label = "green:wps";
22 gpios = <&gpio2 15 GPIO_ACTIVE_LOW>;
23 };
24
25 led_power: power {
26 label = "green:power";
27 gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
28 };
29
30 wlan5g {
31 label = "green:wlan5g";
32 gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
33 };
34 };
35
36 keys {
37 compatible = "gpio-keys";
38
39 s1 {
40 label = "reset";
41 gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
42 linux,code = <KEY_RESTART>;
43 };
44
45 s2 {
46 label = "wps";
47 gpios = <&gpio2 19 GPIO_ACTIVE_LOW>;
48 linux,code = <KEY_WPS_BUTTON>;
49 };
50 };
51 };
52
53 &gpio1 {
54 status = "okay";
55 };
56
57 &gpio2 {
58 status = "okay";
59 };
60
61 &spi0 {
62 status = "okay";
63
64 flash@0 {
65 compatible = "jedec,spi-nor";
66 reg = <0>;
67 spi-max-frequency = <10000000>;
68
69 partitions {
70 compatible = "fixed-partitions";
71 #address-cells = <1>;
72 #size-cells = <1>;
73
74 partition@0 {
75 label = "u-boot";
76 reg = <0x0 0x30000>;
77 read-only;
78 };
79
80 partition@30000 {
81 label = "u-boot-env";
82 reg = <0x30000 0x10000>;
83 read-only;
84 };
85
86 factory: partition@40000 {
87 label = "factory";
88 reg = <0x40000 0x10000>;
89 read-only;
90
91 nvmem-layout {
92 compatible = "fixed-layout";
93 #address-cells = <1>;
94 #size-cells = <1>;
95
96 eeprom_factory_0: eeprom@0 {
97 reg = <0x0 0x200>;
98 };
99
100 eeprom_factory_8000: eeprom@8000 {
101 reg = <0x8000 0x200>;
102 };
103
104 macaddr_factory_4: macaddr@4 {
105 reg = <0x4 0x6>;
106 };
107 };
108 };
109
110 partition@50000 {
111 compatible = "denx,uimage";
112 label = "firmware";
113 reg = <0x50000 0x7b0000>;
114 };
115 };
116 };
117 };
118
119 &state_default {
120 gpio {
121 groups = "i2c", "spi refclk", "rgmii1", "nd_sd";
122 function = "gpio";
123 };
124 };
125
126 &ethernet {
127 pinctrl-names = "default";
128 pinctrl-0 = <&ephy_pins>;
129
130 nvmem-cells = <&macaddr_factory_4>;
131 nvmem-cell-names = "mac-address";
132
133 mediatek,portmap = "llllw";
134 };
135
136 &wmac {
137 nvmem-cells = <&eeprom_factory_0>;
138 nvmem-cell-names = "eeprom";
139 };
140
141 &pcie {
142 status = "okay";
143 };
144
145 &pcie0 {
146 mt76@0,0 {
147 reg = <0x0000 0 0 0 0>;
148 nvmem-cells = <&eeprom_factory_8000>;
149 nvmem-cell-names = "eeprom";
150 };
151 };