88d241601019ab404f18c9236cb7138c36dd561b
[openwrt/openwrt.git] / target / linux / ramips / dts / mt7620a_tplink_archer-c2-v1.dts
1 #include "mt7620a.dtsi"
2
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/input/input.h>
5
6 / {
7 compatible = "tplink,archer-c2-v1", "ralink,mt7620a-soc";
8 model = "TP-Link Archer C2 v1";
9
10 aliases {
11 led-boot = &led_wps;
12 led-failsafe = &led_wps;
13 led-running = &led_wps;
14 led-upgrade = &led_wps;
15 };
16
17 chosen {
18 bootargs = "console=ttyS0,115200";
19 };
20
21 leds {
22 compatible = "gpio-leds";
23
24 lan {
25 label = "green:lan";
26 gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
27 };
28
29 usb {
30 label = "green:usb";
31 gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
32 trigger-sources = <&ohci_port1>, <&ehci_port1>;
33 linux,default-trigger = "usbport";
34 };
35
36 led_wps: wps {
37 label = "green:wps";
38 gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
39 };
40
41 wan {
42 label = "green:wan";
43 gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
44 };
45
46 wlan {
47 label = "green:wlan";
48 gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
49 linux,default-trigger = "phy1tpt";
50 };
51 };
52
53 keys {
54 compatible = "gpio-keys";
55
56 reset_wps {
57 label = "reset_wps";
58 gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
59 linux,code = <KEY_RESTART>;
60 };
61
62 rfkill {
63 label = "rfkill";
64 gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
65 linux,code = <KEY_RFKILL>;
66 };
67 };
68
69 rtl8367rb {
70 compatible = "realtek,rtl8367b", "rtl8367b";
71 cpu_port = <6>;
72 realtek,extif1 = <1 0 1 1 1 1 1 1 2>;
73 mii-bus = <&mdio0>;
74 };
75 };
76
77 &spi0 {
78 status = "okay";
79
80 flash@0 {
81 compatible = "jedec,spi-nor";
82 reg = <0>;
83 spi-max-frequency = <30000000>;
84
85 partitions {
86 compatible = "fixed-partitions";
87 #address-cells = <1>;
88 #size-cells = <1>;
89
90 partition@0 {
91 label = "u-boot";
92 reg = <0x0 0x20000>;
93 read-only;
94 };
95
96 partition@20000 {
97 compatible = "tplink,firmware";
98 label = "firmware";
99 reg = <0x20000 0x7a0000>;
100 };
101
102 partition@7c0000 {
103 label = "config";
104 reg = <0x7c0000 0x10000>;
105 read-only;
106 };
107
108 rom: partition@7d0000 {
109 label = "rom";
110 reg = <0x7d0000 0x10000>;
111 read-only;
112
113 nvmem-layout {
114 compatible = "fixed-layout";
115 #address-cells = <1>;
116 #size-cells = <1>;
117
118 macaddr_rom_f100: macaddr@f100 {
119 compatible = "mac-base";
120 reg = <0xf100 0x6>;
121 #nvmem-cell-cells = <1>;
122 };
123 };
124 };
125
126 partition@7e0000 {
127 label = "romfile";
128 reg = <0x7e0000 0x10000>;
129 read-only;
130 };
131
132 radio: partition@7f0000 {
133 label = "radio";
134 reg = <0x7f0000 0x10000>;
135 read-only;
136
137 nvmem-layout {
138 compatible = "fixed-layout";
139 #address-cells = <1>;
140 #size-cells = <1>;
141
142 eeprom_radio_0: eeprom@0 {
143 reg = <0x0 0x200>;
144 };
145
146 eeprom_radio_8000: eeprom@8000 {
147 reg = <0x8000 0x200>;
148 };
149 };
150 };
151 };
152 };
153 };
154
155 &ethernet {
156 pinctrl-names = "default";
157 pinctrl-0 = <&rgmii1_pins &rgmii2_pins &mdio_pins>;
158
159 nvmem-cells = <&macaddr_rom_f100 0>;
160 nvmem-cell-names = "mac-address";
161
162 port@5 {
163 status = "okay";
164 mediatek,fixed-link = <1000 1 1 1>;
165 phy-mode = "rgmii";
166 };
167
168 mdio0: mdio-bus {
169 status = "okay";
170 };
171 };
172
173 &gpio1 {
174 status = "okay";
175 };
176
177 &gpio2 {
178 status = "okay";
179 };
180
181 &gpio3 {
182 status = "okay";
183 };
184
185 &state_default {
186 gpio {
187 groups = "i2c", "uartf", "wled", "ephy", "spi refclk";
188 function = "gpio";
189 };
190 };
191
192 &wmac {
193 nvmem-cells = <&eeprom_radio_0>, <&macaddr_rom_f100 0>;
194 nvmem-cell-names = "eeprom", "mac-address";
195 };
196
197 &ehci {
198 status = "okay";
199 };
200
201 &ohci {
202 status = "okay";
203 };
204
205 &pcie {
206 status = "okay";
207 };
208
209 &pcie0 {
210 mt76@0,0 {
211 reg = <0x0000 0 0 0 0>;
212 nvmem-cells = <&eeprom_radio_8000>, <&macaddr_rom_f100 (-1)>;
213 nvmem-cell-names = "eeprom", "mac-address";
214 };
215 };