target/linux/ramips/dts/mt7621_ubnt_edgerouter-x.dtsi

   1 #include "mt7621.dtsi"
   2
   3 #include <dt-bindings/gpio/gpio.h>
   4 #include <dt-bindings/input/input.h>
   5
   6 / {
   7         aliases {
   8                 label-mac-device = &gmac0;
   9         };
  10
  11         keys {
  12                 compatible = "gpio-keys";
  13
  14                 reset {
  15                         label = "reset";
  16                         gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
  17                         linux,code = <KEY_RESTART>;
  18                 };
  19         };
  20 };
  21
  22 &ethernet {
  23         pinctrl-0 = <&mdio_pins>, <&rgmii1_pins>;
  24 };
  25
  26 &gmac0 {
  27         nvmem-cells = <&macaddr_factory_22>;
  28         nvmem-cell-names = "mac-address";
  29         label = "dsa";
  30 };
  31
  32 &switch0 {
  33         ports {
  34                 port@0 {
  35                         status = "okay";
  36                         label = "eth0";
  37                 };
  38
  39                 port@1 {
  40                         status = "okay";
  41                         label = "eth1";
  42                         nvmem-cells = <&macaddr_factory_22>;
  43                         nvmem-cell-names = "mac-address";
  44                         mac-address-increment = <1>;
  45                 };
  46
  47                 port@2 {
  48                         status = "okay";
  49                         label = "eth2";
  50                         nvmem-cells = <&macaddr_factory_22>;
  51                         nvmem-cell-names = "mac-address";
  52                         mac-address-increment = <2>;
  53                 };
  54
  55                 port@3 {
  56                         status = "okay";
  57                         label = "eth3";
  58                         nvmem-cells = <&macaddr_factory_22>;
  59                         nvmem-cell-names = "mac-address";
  60                         mac-address-increment = <3>;
  61                 };
  62
  63                 port@4 {
  64                         status = "okay";
  65                         label = "eth4";
  66                         nvmem-cells = <&macaddr_factory_22>;
  67                         nvmem-cell-names = "mac-address";
  68                         mac-address-increment = <4>;
  69                 };
  70         };
  71 };
  72
  73 &nand {
  74         status = "okay";
  75
  76         partitions {
  77                 compatible = "fixed-partitions";
  78                 #address-cells = <1>;
  79                 #size-cells = <1>;
  80
  81                 partition@0 {
  82                         label = "u-boot";
  83                         reg = <0x0 0x80000>;
  84                         read-only;
  85                 };
  86
  87                 partition@80000 {
  88                         label = "u-boot-env";
  89                         reg = <0x80000 0x60000>;
  90                         read-only;
  91                 };
  92
  93                 factory: partition@e0000 {
  94                         label = "factory";
  95                         reg = <0xe0000 0x60000>;
  96                 };
  97
  98                 partition@140000 {
  99                         label = "kernel1";
 100                         reg = <0x140000 0x300000>;
 101                 };
 102
 103                 partition@440000 {
 104                         label = "kernel2";
 105                         reg = <0x440000 0x300000>;
 106                 };
 107
 108                 partition@740000 {
 109                         label = "ubi";
 110                         reg = <0x740000 0xf7c0000>;
 111                 };
 112         };
 113 };
 114
 115 &state_default {
 116         gpio {
 117                 groups = "uart2", "uart3", "pcie", "rgmii2", "jtag";
 118                 function = "gpio";
 119         };
 120 };
 121
 122 &spi0 {
 123         /*
 124          * This board has 2Mb spi flash soldered in and visible
 125          * from manufacturer's firmware.
 126          * But this SoC shares spi and nand pins,
 127          * and current driver doesn't handle this sharing well
 128          */
 129         status = "disabled";
 130
 131         flash@1 {
 132                 compatible = "jedec,spi-nor";
 133                 reg = <1>;
 134                 spi-max-frequency = <10000000>;
 135
 136                 partitions {
 137                         compatible = "fixed-partitions";
 138                         #address-cells = <1>;
 139                         #size-cells = <1>;
 140
 141                         partition@0 {
 142                                 label = "spi";
 143                                 reg = <0x0 0x200000>;
 144                                 read-only;
 145                         };
 146                 };
 147         };
 148 };
 149
 150 &xhci {
 151         status = "disabled";
 152 };
 153
 154 &factory {
 155         compatible = "nvmem-cells";
 156         #address-cells = <1>;
 157         #size-cells = <1>;
 158
 159         macaddr_factory_22: macaddr@22 {
 160                 reg = <0x22 0x6>;
 161         };
 162 };