target/linux/ramips/files/arch/mips/ralink/rt3883/rt3883.c

   1 /*
   2  * Ralink RT3662/RT3883 SoC specific setup
   3  *
   4  * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
   5  *
   6  * Parts of this file are based on Ralink's 2.6.21 BSP
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms of the GNU General Public License version 2 as published
  10  * by the Free Software Foundation.
  11  */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/init.h>
  15 #include <linux/module.h>
  16
  17 #include <asm/mach-ralink/common.h>
  18 #include <asm/mach-ralink/ramips_gpio.h>
  19 #include <asm/mach-ralink/rt3883.h>
  20 #include <asm/mach-ralink/rt3883_regs.h>
  21
  22 void __iomem * rt3883_sysc_base;
  23 void __iomem * rt3883_memc_base;
  24
  25 void __init rt3883_detect_sys_type(void)
  26 {
  27         u32 n0;
  28         u32 n1;
  29         u32 id;
  30
  31         n0 = rt3883_sysc_rr(RT3883_SYSC_REG_CHIPID0_3);
  32         n1 = rt3883_sysc_rr(RT3883_SYSC_REG_CHIPID4_7);
  33         id = rt3883_sysc_rr(RT3883_SYSC_REG_REVID);
  34
  35         snprintf(ramips_sys_type, RAMIPS_SYS_TYPE_LEN,
  36                 "Ralink %c%c%c%c%c%c%c%c ver:%u eco:%u",
  37                 (char) (n0 & 0xff), (char) ((n0 >> 8) & 0xff),
  38                 (char) ((n0 >> 16) & 0xff), (char) ((n0 >> 24) & 0xff),
  39                 (char) (n1 & 0xff), (char) ((n1 >> 8) & 0xff),
  40                 (char) ((n1 >> 16) & 0xff), (char) ((n1 >> 24) & 0xff),
  41                 (id >> RT3883_REVID_VER_ID_SHIFT) & RT3883_REVID_VER_ID_MASK,
  42                 (id & RT3883_REVID_ECO_ID_MASK));
  43 }
  44
  45 static struct ramips_gpio_chip rt3883_gpio_chips[] = {
  46         {
  47                 .chip = {
  48                         .label                  = "RT3883-GPIO0",
  49                         .base                   = 0,
  50                         .ngpio                  = 24,
  51                 },
  52                 .regs = {
  53                         [RAMIPS_GPIO_REG_INT]   = 0x00,
  54                         [RAMIPS_GPIO_REG_EDGE]  = 0x04,
  55                         [RAMIPS_GPIO_REG_RENA]  = 0x08,
  56                         [RAMIPS_GPIO_REG_FENA]  = 0x0c,
  57                         [RAMIPS_GPIO_REG_DATA]  = 0x20,
  58                         [RAMIPS_GPIO_REG_DIR]   = 0x24,
  59                         [RAMIPS_GPIO_REG_POL]   = 0x28,
  60                         [RAMIPS_GPIO_REG_SET]   = 0x2c,
  61                         [RAMIPS_GPIO_REG_RESET] = 0x30,
  62                         [RAMIPS_GPIO_REG_TOGGLE] = 0x34,
  63                 },
  64                 .map_base       = RT3883_PIO_BASE,
  65                 .map_size       = RT3883_PIO_SIZE,
  66         },
  67         {
  68                 .chip = {
  69                         .label                  = "RT3883-GPIO1",
  70                         .base                   = 24,
  71                         .ngpio                  = 16,
  72                 },
  73                 .regs = {
  74                         [RAMIPS_GPIO_REG_INT]   = 0x38,
  75                         [RAMIPS_GPIO_REG_EDGE]  = 0x3c,
  76                         [RAMIPS_GPIO_REG_RENA]  = 0x40,
  77                         [RAMIPS_GPIO_REG_FENA]  = 0x44,
  78                         [RAMIPS_GPIO_REG_DATA]  = 0x48,
  79                         [RAMIPS_GPIO_REG_DIR]   = 0x4c,
  80                         [RAMIPS_GPIO_REG_POL]   = 0x50,
  81                         [RAMIPS_GPIO_REG_SET]   = 0x54,
  82                         [RAMIPS_GPIO_REG_RESET] = 0x58,
  83                         [RAMIPS_GPIO_REG_TOGGLE] = 0x5c,
  84                 },
  85                 .map_base       = RT3883_PIO_BASE,
  86                 .map_size       = RT3883_PIO_SIZE,
  87         },
  88         {
  89                 .chip = {
  90                         .label                  = "RT3883-GPIO2",
  91                         .base                   = 40,
  92                         .ngpio                  = 32,
  93                 },
  94                 .regs = {
  95                         [RAMIPS_GPIO_REG_INT]   = 0x60,
  96                         [RAMIPS_GPIO_REG_EDGE]  = 0x64,
  97                         [RAMIPS_GPIO_REG_RENA]  = 0x68,
  98                         [RAMIPS_GPIO_REG_FENA]  = 0x6c,
  99                         [RAMIPS_GPIO_REG_DATA]  = 0x70,
 100                         [RAMIPS_GPIO_REG_DIR]   = 0x74,
 101                         [RAMIPS_GPIO_REG_POL]   = 0x78,
 102                         [RAMIPS_GPIO_REG_SET]   = 0x7c,
 103                         [RAMIPS_GPIO_REG_RESET] = 0x80,
 104                         [RAMIPS_GPIO_REG_TOGGLE] = 0x84,
 105                 },
 106                 .map_base       = RT3883_PIO_BASE,
 107                 .map_size       = RT3883_PIO_SIZE,
 108         },
 109         {
 110                 .chip = {
 111                         .label                  = "RT3883-GPIO3",
 112                         .base                   = 72,
 113                         .ngpio                  = 24,
 114                 },
 115                 .regs = {
 116                         [RAMIPS_GPIO_REG_INT]   = 0x88,
 117                         [RAMIPS_GPIO_REG_EDGE]  = 0x8c,
 118                         [RAMIPS_GPIO_REG_RENA]  = 0x90,
 119                         [RAMIPS_GPIO_REG_FENA]  = 0x94,
 120                         [RAMIPS_GPIO_REG_DATA]  = 0x98,
 121                         [RAMIPS_GPIO_REG_DIR]   = 0x9c,
 122                         [RAMIPS_GPIO_REG_POL]   = 0xa0,
 123                         [RAMIPS_GPIO_REG_SET]   = 0xa4,
 124                         [RAMIPS_GPIO_REG_RESET] = 0xa8,
 125                         [RAMIPS_GPIO_REG_TOGGLE] = 0xac,
 126                 },
 127                 .map_base       = RT3883_PIO_BASE,
 128                 .map_size       = RT3883_PIO_SIZE,
 129         },
 130 };
 131
 132 static struct ramips_gpio_data rt3883_gpio_data = {
 133         .chips = rt3883_gpio_chips,
 134         .num_chips = ARRAY_SIZE(rt3883_gpio_chips),
 135 };
 136
 137 static void rt3883_gpio_reserve(int first, int last)
 138 {
 139         for (; first <= last; first++)
 140                 gpio_request(first, "reserved");
 141 }
 142
 143 void __init rt3883_gpio_init(u32 mode)
 144 {
 145         u32 t;
 146
 147         rt3883_sysc_wr(mode, RT3883_SYSC_REG_GPIO_MODE);
 148
 149         ramips_gpio_init(&rt3883_gpio_data);
 150         if ((mode & RT3883_GPIO_MODE_I2C) == 0)
 151                 rt3883_gpio_reserve(RT3883_GPIO_I2C_SD, RT3883_GPIO_I2C_SCLK);
 152
 153         if ((mode & RT3883_GPIO_MODE_SPI) == 0)
 154                 rt3883_gpio_reserve(RT3883_GPIO_SPI_CS0, RT3883_GPIO_SPI_CLK);
 155
 156         t = mode >> RT3883_GPIO_MODE_UART0_SHIFT;
 157         t &= RT3883_GPIO_MODE_UART0_MASK;
 158         switch (t) {
 159         case RT3883_GPIO_MODE_UARTF:
 160         case RT3883_GPIO_MODE_PCM_UARTF:
 161         case RT3883_GPIO_MODE_PCM_I2S:
 162         case RT3883_GPIO_MODE_I2S_UARTF:
 163                 rt3883_gpio_reserve(RT3883_GPIO_7, RT3883_GPIO_14);
 164                 break;
 165         case RT3883_GPIO_MODE_PCM_GPIO:
 166                 rt3883_gpio_reserve(RT3883_GPIO_11, RT3883_GPIO_14);
 167                 break;
 168         case RT3883_GPIO_MODE_GPIO_UARTF:
 169         case RT3883_GPIO_MODE_GPIO_I2S:
 170                 rt3883_gpio_reserve(RT3883_GPIO_7, RT3883_GPIO_10);
 171                 break;
 172         }
 173
 174         if ((mode & RT3883_GPIO_MODE_UART1) == 0)
 175                 rt3883_gpio_reserve(RT3883_GPIO_UART1_TXD,
 176                                     RT3883_GPIO_UART1_RXD);
 177
 178         if ((mode & RT3883_GPIO_MODE_JTAG) == 0)
 179                 rt3883_gpio_reserve(RT3883_GPIO_JTAG_TDO,
 180                                     RT3883_GPIO_JTAG_TCLK);
 181
 182         if ((mode & RT3883_GPIO_MODE_MDIO) == 0)
 183                 rt3883_gpio_reserve(RT3883_GPIO_MDIO_MDC,
 184                                     RT3883_GPIO_MDIO_MDIO);
 185
 186         if ((mode & RT3883_GPIO_MODE_GE1) == 0)
 187                 rt3883_gpio_reserve(RT3883_GPIO_GE1_TXD0,
 188                                     RT3883_GPIO_GE1_RXCLK);
 189
 190         if ((mode & RT3883_GPIO_MODE_GE2) == 0)
 191                 rt3883_gpio_reserve(RT3883_GPIO_GE2_TXD0,
 192                                     RT3883_GPIO_GE2_RXCLK);
 193
 194         t = mode >> RT3883_GPIO_MODE_PCI_SHIFT;
 195         t &= RT3883_GPIO_MODE_PCI_MASK;
 196         if (t != RT3883_GPIO_MODE_PCI_GPIO)
 197                 rt3883_gpio_reserve(RT3883_GPIO_PCI_AD0,
 198                                     RT3883_GPIO_PCI_AD31);
 199
 200         t = mode >> RT3883_GPIO_MODE_LNA_A_SHIFT;
 201         t &= RT3883_GPIO_MODE_LNA_A_MASK;
 202         if (t != RT3883_GPIO_MODE_LNA_A_GPIO)
 203                 rt3883_gpio_reserve(RT3883_GPIO_LNA_PE_A0,
 204                                     RT3883_GPIO_LNA_PE_A2);
 205
 206         t = mode >> RT3883_GPIO_MODE_LNA_G_SHIFT;
 207         t &= RT3883_GPIO_MODE_LNA_G_MASK;
 208         if (t != RT3883_GPIO_MODE_LNA_G_GPIO)
 209                 rt3883_gpio_reserve(RT3883_GPIO_LNA_PE_G0,
 210                                     RT3883_GPIO_LNA_PE_G2);
 211 }