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kernel: remove obsolete kernel version switches
[openwrt/openwrt.git] / target / linux / ramips / files / drivers / net / ethernet / ralink / mtk_eth_soc.c
1 /* This program is free software; you can redistribute it and/or modify
2 * it under the terms of the GNU General Public License as published by
3 * the Free Software Foundation; version 2 of the License
4 *
5 * This program is distributed in the hope that it will be useful,
6 * but WITHOUT ANY WARRANTY; without even the implied warranty of
7 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8 * GNU General Public License for more details.
9 *
10 * Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
11 * Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
12 * Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
13 */
14
15 #include <linux/module.h>
16 #include <linux/kernel.h>
17 #include <linux/types.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/init.h>
20 #include <linux/skbuff.h>
21 #include <linux/etherdevice.h>
22 #include <linux/ethtool.h>
23 #include <linux/platform_device.h>
24 #include <linux/of_device.h>
25 #include <linux/clk.h>
26 #include <linux/of_net.h>
27 #include <linux/of_mdio.h>
28 #include <linux/if_vlan.h>
29 #include <linux/reset.h>
30 #include <linux/tcp.h>
31 #include <linux/io.h>
32 #include <linux/bug.h>
33 #include <linux/netfilter.h>
34 #include <net/netfilter/nf_flow_table.h>
35 #include <linux/of_gpio.h>
36 #include <linux/gpio.h>
37 #include <linux/gpio/consumer.h>
38
39 #include <asm/mach-ralink/ralink_regs.h>
40
41 #include "mtk_eth_soc.h"
42 #include "mdio.h"
43 #include "ethtool.h"
44
45 #define MAX_RX_LENGTH 1536
46 #define FE_RX_ETH_HLEN (VLAN_ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN)
47 #define FE_RX_HLEN (NET_SKB_PAD + FE_RX_ETH_HLEN + NET_IP_ALIGN)
48 #define DMA_DUMMY_DESC 0xffffffff
49 #define FE_DEFAULT_MSG_ENABLE \
50 (NETIF_MSG_DRV | \
51 NETIF_MSG_PROBE | \
52 NETIF_MSG_LINK | \
53 NETIF_MSG_TIMER | \
54 NETIF_MSG_IFDOWN | \
55 NETIF_MSG_IFUP | \
56 NETIF_MSG_RX_ERR | \
57 NETIF_MSG_TX_ERR)
58
59 #define TX_DMA_DESP2_DEF (TX_DMA_LS0 | TX_DMA_DONE)
60 #define TX_DMA_DESP4_DEF (TX_DMA_QN(3) | TX_DMA_PN(1))
61 #define NEXT_TX_DESP_IDX(X) (((X) + 1) & (ring->tx_ring_size - 1))
62 #define NEXT_RX_DESP_IDX(X) (((X) + 1) & (ring->rx_ring_size - 1))
63
64 #define SYSC_REG_RSTCTRL 0x34
65
66 static int fe_msg_level = -1;
67 module_param_named(msg_level, fe_msg_level, int, 0);
68 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
69
70 static const u16 fe_reg_table_default[FE_REG_COUNT] = {
71 [FE_REG_PDMA_GLO_CFG] = FE_PDMA_GLO_CFG,
72 [FE_REG_PDMA_RST_CFG] = FE_PDMA_RST_CFG,
73 [FE_REG_DLY_INT_CFG] = FE_DLY_INT_CFG,
74 [FE_REG_TX_BASE_PTR0] = FE_TX_BASE_PTR0,
75 [FE_REG_TX_MAX_CNT0] = FE_TX_MAX_CNT0,
76 [FE_REG_TX_CTX_IDX0] = FE_TX_CTX_IDX0,
77 [FE_REG_TX_DTX_IDX0] = FE_TX_DTX_IDX0,
78 [FE_REG_RX_BASE_PTR0] = FE_RX_BASE_PTR0,
79 [FE_REG_RX_MAX_CNT0] = FE_RX_MAX_CNT0,
80 [FE_REG_RX_CALC_IDX0] = FE_RX_CALC_IDX0,
81 [FE_REG_RX_DRX_IDX0] = FE_RX_DRX_IDX0,
82 [FE_REG_FE_INT_ENABLE] = FE_FE_INT_ENABLE,
83 [FE_REG_FE_INT_STATUS] = FE_FE_INT_STATUS,
84 [FE_REG_FE_DMA_VID_BASE] = FE_DMA_VID0,
85 [FE_REG_FE_COUNTER_BASE] = FE_GDMA1_TX_GBCNT,
86 [FE_REG_FE_RST_GL] = FE_FE_RST_GL,
87 };
88
89 static const u16 *fe_reg_table = fe_reg_table_default;
90
91 struct fe_work_t {
92 int bitnr;
93 void (*action)(struct fe_priv *);
94 };
95
96 static void __iomem *fe_base;
97
98 void fe_w32(u32 val, unsigned reg)
99 {
100 __raw_writel(val, fe_base + reg);
101 }
102
103 u32 fe_r32(unsigned reg)
104 {
105 return __raw_readl(fe_base + reg);
106 }
107
108 void fe_reg_w32(u32 val, enum fe_reg reg)
109 {
110 fe_w32(val, fe_reg_table[reg]);
111 }
112
113 u32 fe_reg_r32(enum fe_reg reg)
114 {
115 return fe_r32(fe_reg_table[reg]);
116 }
117
118 void fe_m32(struct fe_priv *eth, u32 clear, u32 set, unsigned reg)
119 {
120 u32 val;
121
122 spin_lock(&eth->page_lock);
123 val = __raw_readl(fe_base + reg);
124 val &= ~clear;
125 val |= set;
126 __raw_writel(val, fe_base + reg);
127 spin_unlock(&eth->page_lock);
128 }
129
130 void fe_reset(u32 reset_bits)
131 {
132 u32 t;
133
134 t = rt_sysc_r32(SYSC_REG_RSTCTRL);
135 t |= reset_bits;
136 rt_sysc_w32(t, SYSC_REG_RSTCTRL);
137 usleep_range(10, 20);
138
139 t &= ~reset_bits;
140 rt_sysc_w32(t, SYSC_REG_RSTCTRL);
141 usleep_range(10, 20);
142 }
143
144 void fe_reset_fe(struct fe_priv *priv)
145 {
146 if (!priv->rst_fe)
147 return;
148
149 reset_control_assert(priv->rst_fe);
150 usleep_range(60, 120);
151 reset_control_deassert(priv->rst_fe);
152 usleep_range(60, 120);
153 }
154
155 static inline void fe_int_disable(u32 mask)
156 {
157 fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE) & ~mask,
158 FE_REG_FE_INT_ENABLE);
159 /* flush write */
160 fe_reg_r32(FE_REG_FE_INT_ENABLE);
161 }
162
163 static inline void fe_int_enable(u32 mask)
164 {
165 fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE) | mask,
166 FE_REG_FE_INT_ENABLE);
167 /* flush write */
168 fe_reg_r32(FE_REG_FE_INT_ENABLE);
169 }
170
171 static inline void fe_hw_set_macaddr(struct fe_priv *priv, unsigned char *mac)
172 {
173 unsigned long flags;
174
175 spin_lock_irqsave(&priv->page_lock, flags);
176 fe_w32((mac[0] << 8) | mac[1], FE_GDMA1_MAC_ADRH);
177 fe_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
178 FE_GDMA1_MAC_ADRL);
179 spin_unlock_irqrestore(&priv->page_lock, flags);
180 }
181
182 static int fe_set_mac_address(struct net_device *dev, void *p)
183 {
184 int ret = eth_mac_addr(dev, p);
185
186 if (!ret) {
187 struct fe_priv *priv = netdev_priv(dev);
188
189 if (priv->soc->set_mac)
190 priv->soc->set_mac(priv, dev->dev_addr);
191 else
192 fe_hw_set_macaddr(priv, p);
193 }
194
195 return ret;
196 }
197
198 static inline int fe_max_frag_size(int mtu)
199 {
200 /* make sure buf_size will be at least MAX_RX_LENGTH */
201 if (mtu + FE_RX_ETH_HLEN < MAX_RX_LENGTH)
202 mtu = MAX_RX_LENGTH - FE_RX_ETH_HLEN;
203
204 return SKB_DATA_ALIGN(FE_RX_HLEN + mtu) +
205 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
206 }
207
208 static inline int fe_max_buf_size(int frag_size)
209 {
210 int buf_size = frag_size - NET_SKB_PAD - NET_IP_ALIGN -
211 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
212
213 BUG_ON(buf_size < MAX_RX_LENGTH);
214 return buf_size;
215 }
216
217 static inline void fe_get_rxd(struct fe_rx_dma *rxd, struct fe_rx_dma *dma_rxd)
218 {
219 rxd->rxd1 = dma_rxd->rxd1;
220 rxd->rxd2 = dma_rxd->rxd2;
221 rxd->rxd3 = dma_rxd->rxd3;
222 rxd->rxd4 = dma_rxd->rxd4;
223 }
224
225 static inline void fe_set_txd(struct fe_tx_dma *txd, struct fe_tx_dma *dma_txd)
226 {
227 dma_txd->txd1 = txd->txd1;
228 dma_txd->txd3 = txd->txd3;
229 dma_txd->txd4 = txd->txd4;
230 /* clean dma done flag last */
231 dma_txd->txd2 = txd->txd2;
232 }
233
234 static void fe_clean_rx(struct fe_priv *priv)
235 {
236 struct fe_rx_ring *ring = &priv->rx_ring;
237 struct page *page;
238 int i;
239
240 if (ring->rx_data) {
241 for (i = 0; i < ring->rx_ring_size; i++)
242 if (ring->rx_data[i]) {
243 if (ring->rx_dma && ring->rx_dma[i].rxd1)
244 dma_unmap_single(priv->dev,
245 ring->rx_dma[i].rxd1,
246 ring->rx_buf_size,
247 DMA_FROM_DEVICE);
248 skb_free_frag(ring->rx_data[i]);
249 }
250
251 kfree(ring->rx_data);
252 ring->rx_data = NULL;
253 }
254
255 if (ring->rx_dma) {
256 dma_free_coherent(priv->dev,
257 ring->rx_ring_size * sizeof(*ring->rx_dma),
258 ring->rx_dma,
259 ring->rx_phys);
260 ring->rx_dma = NULL;
261 }
262
263 if (!ring->frag_cache.va)
264 return;
265
266 page = virt_to_page(ring->frag_cache.va);
267 __page_frag_cache_drain(page, ring->frag_cache.pagecnt_bias);
268 memset(&ring->frag_cache, 0, sizeof(ring->frag_cache));
269 }
270
271 static int fe_alloc_rx(struct fe_priv *priv)
272 {
273 struct fe_rx_ring *ring = &priv->rx_ring;
274 int i, pad;
275
276 ring->rx_data = kcalloc(ring->rx_ring_size, sizeof(*ring->rx_data),
277 GFP_KERNEL);
278 if (!ring->rx_data)
279 goto no_rx_mem;
280
281 for (i = 0; i < ring->rx_ring_size; i++) {
282 ring->rx_data[i] = page_frag_alloc(&ring->frag_cache,
283 ring->frag_size,
284 GFP_KERNEL);
285 if (!ring->rx_data[i])
286 goto no_rx_mem;
287 }
288
289 ring->rx_dma = dma_alloc_coherent(priv->dev,
290 ring->rx_ring_size * sizeof(*ring->rx_dma),
291 &ring->rx_phys,
292 GFP_ATOMIC | __GFP_ZERO);
293 if (!ring->rx_dma)
294 goto no_rx_mem;
295
296 if (priv->flags & FE_FLAG_RX_2B_OFFSET)
297 pad = 0;
298 else
299 pad = NET_IP_ALIGN;
300 for (i = 0; i < ring->rx_ring_size; i++) {
301 dma_addr_t dma_addr = dma_map_single(priv->dev,
302 ring->rx_data[i] + NET_SKB_PAD + pad,
303 ring->rx_buf_size,
304 DMA_FROM_DEVICE);
305 if (unlikely(dma_mapping_error(priv->dev, dma_addr)))
306 goto no_rx_mem;
307 ring->rx_dma[i].rxd1 = (unsigned int)dma_addr;
308
309 if (priv->flags & FE_FLAG_RX_SG_DMA)
310 ring->rx_dma[i].rxd2 = RX_DMA_PLEN0(ring->rx_buf_size);
311 else
312 ring->rx_dma[i].rxd2 = RX_DMA_LSO;
313 }
314 ring->rx_calc_idx = ring->rx_ring_size - 1;
315 /* make sure that all changes to the dma ring are flushed before we
316 * continue
317 */
318 wmb();
319
320 fe_reg_w32(ring->rx_phys, FE_REG_RX_BASE_PTR0);
321 fe_reg_w32(ring->rx_ring_size, FE_REG_RX_MAX_CNT0);
322 fe_reg_w32(ring->rx_calc_idx, FE_REG_RX_CALC_IDX0);
323 fe_reg_w32(FE_PST_DRX_IDX0, FE_REG_PDMA_RST_CFG);
324
325 return 0;
326
327 no_rx_mem:
328 return -ENOMEM;
329 }
330
331 static void fe_txd_unmap(struct device *dev, struct fe_tx_buf *tx_buf)
332 {
333 if (dma_unmap_len(tx_buf, dma_len0))
334 dma_unmap_page(dev,
335 dma_unmap_addr(tx_buf, dma_addr0),
336 dma_unmap_len(tx_buf, dma_len0),
337 DMA_TO_DEVICE);
338
339 if (dma_unmap_len(tx_buf, dma_len1))
340 dma_unmap_page(dev,
341 dma_unmap_addr(tx_buf, dma_addr1),
342 dma_unmap_len(tx_buf, dma_len1),
343 DMA_TO_DEVICE);
344
345 dma_unmap_len_set(tx_buf, dma_addr0, 0);
346 dma_unmap_len_set(tx_buf, dma_addr1, 0);
347 if (tx_buf->skb && (tx_buf->skb != (struct sk_buff *)DMA_DUMMY_DESC))
348 dev_kfree_skb_any(tx_buf->skb);
349 tx_buf->skb = NULL;
350 }
351
352 static void fe_clean_tx(struct fe_priv *priv)
353 {
354 int i;
355 struct device *dev = priv->dev;
356 struct fe_tx_ring *ring = &priv->tx_ring;
357
358 if (ring->tx_buf) {
359 for (i = 0; i < ring->tx_ring_size; i++)
360 fe_txd_unmap(dev, &ring->tx_buf[i]);
361 kfree(ring->tx_buf);
362 ring->tx_buf = NULL;
363 }
364
365 if (ring->tx_dma) {
366 dma_free_coherent(dev,
367 ring->tx_ring_size * sizeof(*ring->tx_dma),
368 ring->tx_dma,
369 ring->tx_phys);
370 ring->tx_dma = NULL;
371 }
372
373 netdev_reset_queue(priv->netdev);
374 }
375
376 static int fe_alloc_tx(struct fe_priv *priv)
377 {
378 int i;
379 struct fe_tx_ring *ring = &priv->tx_ring;
380
381 ring->tx_free_idx = 0;
382 ring->tx_next_idx = 0;
383 ring->tx_thresh = max((unsigned long)ring->tx_ring_size >> 2,
384 MAX_SKB_FRAGS);
385
386 ring->tx_buf = kcalloc(ring->tx_ring_size, sizeof(*ring->tx_buf),
387 GFP_KERNEL);
388 if (!ring->tx_buf)
389 goto no_tx_mem;
390
391 ring->tx_dma = dma_alloc_coherent(priv->dev,
392 ring->tx_ring_size * sizeof(*ring->tx_dma),
393 &ring->tx_phys,
394 GFP_ATOMIC | __GFP_ZERO);
395 if (!ring->tx_dma)
396 goto no_tx_mem;
397
398 for (i = 0; i < ring->tx_ring_size; i++) {
399 if (priv->soc->tx_dma)
400 priv->soc->tx_dma(&ring->tx_dma[i]);
401 ring->tx_dma[i].txd2 = TX_DMA_DESP2_DEF;
402 }
403 /* make sure that all changes to the dma ring are flushed before we
404 * continue
405 */
406 wmb();
407
408 fe_reg_w32(ring->tx_phys, FE_REG_TX_BASE_PTR0);
409 fe_reg_w32(ring->tx_ring_size, FE_REG_TX_MAX_CNT0);
410 fe_reg_w32(0, FE_REG_TX_CTX_IDX0);
411 fe_reg_w32(FE_PST_DTX_IDX0, FE_REG_PDMA_RST_CFG);
412
413 return 0;
414
415 no_tx_mem:
416 return -ENOMEM;
417 }
418
419 static int fe_init_dma(struct fe_priv *priv)
420 {
421 int err;
422
423 err = fe_alloc_tx(priv);
424 if (err)
425 return err;
426
427 err = fe_alloc_rx(priv);
428 if (err)
429 return err;
430
431 return 0;
432 }
433
434 static void fe_free_dma(struct fe_priv *priv)
435 {
436 fe_clean_tx(priv);
437 fe_clean_rx(priv);
438 }
439
440 void fe_stats_update(struct fe_priv *priv)
441 {
442 struct fe_hw_stats *hwstats = priv->hw_stats;
443 unsigned int base = fe_reg_table[FE_REG_FE_COUNTER_BASE];
444 u64 stats;
445
446 u64_stats_update_begin(&hwstats->syncp);
447
448 if (IS_ENABLED(CONFIG_SOC_MT7621)) {
449 hwstats->rx_bytes += fe_r32(base);
450 stats = fe_r32(base + 0x04);
451 if (stats)
452 hwstats->rx_bytes += (stats << 32);
453 hwstats->rx_packets += fe_r32(base + 0x08);
454 hwstats->rx_overflow += fe_r32(base + 0x10);
455 hwstats->rx_fcs_errors += fe_r32(base + 0x14);
456 hwstats->rx_short_errors += fe_r32(base + 0x18);
457 hwstats->rx_long_errors += fe_r32(base + 0x1c);
458 hwstats->rx_checksum_errors += fe_r32(base + 0x20);
459 hwstats->rx_flow_control_packets += fe_r32(base + 0x24);
460 hwstats->tx_skip += fe_r32(base + 0x28);
461 hwstats->tx_collisions += fe_r32(base + 0x2c);
462 hwstats->tx_bytes += fe_r32(base + 0x30);
463 stats = fe_r32(base + 0x34);
464 if (stats)
465 hwstats->tx_bytes += (stats << 32);
466 hwstats->tx_packets += fe_r32(base + 0x38);
467 } else {
468 hwstats->tx_bytes += fe_r32(base);
469 hwstats->tx_packets += fe_r32(base + 0x04);
470 hwstats->tx_skip += fe_r32(base + 0x08);
471 hwstats->tx_collisions += fe_r32(base + 0x0c);
472 hwstats->rx_bytes += fe_r32(base + 0x20);
473 hwstats->rx_packets += fe_r32(base + 0x24);
474 hwstats->rx_overflow += fe_r32(base + 0x28);
475 hwstats->rx_fcs_errors += fe_r32(base + 0x2c);
476 hwstats->rx_short_errors += fe_r32(base + 0x30);
477 hwstats->rx_long_errors += fe_r32(base + 0x34);
478 hwstats->rx_checksum_errors += fe_r32(base + 0x38);
479 hwstats->rx_flow_control_packets += fe_r32(base + 0x3c);
480 }
481
482 u64_stats_update_end(&hwstats->syncp);
483 }
484
485 static void fe_get_stats64(struct net_device *dev,
486 struct rtnl_link_stats64 *storage)
487 {
488 struct fe_priv *priv = netdev_priv(dev);
489 struct fe_hw_stats *hwstats = priv->hw_stats;
490 unsigned int base = fe_reg_table[FE_REG_FE_COUNTER_BASE];
491 unsigned int start;
492
493 if (!base) {
494 netdev_stats_to_stats64(storage, &dev->stats);
495 return;
496 }
497
498 if (netif_running(dev) && netif_device_present(dev)) {
499 if (spin_trylock_bh(&hwstats->stats_lock)) {
500 fe_stats_update(priv);
501 spin_unlock_bh(&hwstats->stats_lock);
502 }
503 }
504
505 do {
506 start = u64_stats_fetch_begin_irq(&hwstats->syncp);
507 storage->rx_packets = hwstats->rx_packets;
508 storage->tx_packets = hwstats->tx_packets;
509 storage->rx_bytes = hwstats->rx_bytes;
510 storage->tx_bytes = hwstats->tx_bytes;
511 storage->collisions = hwstats->tx_collisions;
512 storage->rx_length_errors = hwstats->rx_short_errors +
513 hwstats->rx_long_errors;
514 storage->rx_over_errors = hwstats->rx_overflow;
515 storage->rx_crc_errors = hwstats->rx_fcs_errors;
516 storage->rx_errors = hwstats->rx_checksum_errors;
517 storage->tx_aborted_errors = hwstats->tx_skip;
518 } while (u64_stats_fetch_retry_irq(&hwstats->syncp, start));
519
520 storage->tx_errors = priv->netdev->stats.tx_errors;
521 storage->rx_dropped = priv->netdev->stats.rx_dropped;
522 storage->tx_dropped = priv->netdev->stats.tx_dropped;
523 }
524
525 static int fe_vlan_rx_add_vid(struct net_device *dev,
526 __be16 proto, u16 vid)
527 {
528 struct fe_priv *priv = netdev_priv(dev);
529 u32 idx = (vid & 0xf);
530 u32 vlan_cfg;
531
532 if (!((fe_reg_table[FE_REG_FE_DMA_VID_BASE]) &&
533 (dev->features & NETIF_F_HW_VLAN_CTAG_TX)))
534 return 0;
535
536 if (test_bit(idx, &priv->vlan_map)) {
537 netdev_warn(dev, "disable tx vlan offload\n");
538 dev->wanted_features &= ~NETIF_F_HW_VLAN_CTAG_TX;
539 netdev_update_features(dev);
540 } else {
541 vlan_cfg = fe_r32(fe_reg_table[FE_REG_FE_DMA_VID_BASE] +
542 ((idx >> 1) << 2));
543 if (idx & 0x1) {
544 vlan_cfg &= 0xffff;
545 vlan_cfg |= (vid << 16);
546 } else {
547 vlan_cfg &= 0xffff0000;
548 vlan_cfg |= vid;
549 }
550 fe_w32(vlan_cfg, fe_reg_table[FE_REG_FE_DMA_VID_BASE] +
551 ((idx >> 1) << 2));
552 set_bit(idx, &priv->vlan_map);
553 }
554
555 return 0;
556 }
557
558 static int fe_vlan_rx_kill_vid(struct net_device *dev,
559 __be16 proto, u16 vid)
560 {
561 struct fe_priv *priv = netdev_priv(dev);
562 u32 idx = (vid & 0xf);
563
564 if (!((fe_reg_table[FE_REG_FE_DMA_VID_BASE]) &&
565 (dev->features & NETIF_F_HW_VLAN_CTAG_TX)))
566 return 0;
567
568 clear_bit(idx, &priv->vlan_map);
569
570 return 0;
571 }
572
573 static inline u32 fe_empty_txd(struct fe_tx_ring *ring)
574 {
575 barrier();
576 return (u32)(ring->tx_ring_size -
577 ((ring->tx_next_idx - ring->tx_free_idx) &
578 (ring->tx_ring_size - 1)));
579 }
580
581 struct fe_map_state {
582 struct device *dev;
583 struct fe_tx_dma txd;
584 u32 def_txd4;
585 int ring_idx;
586 int i;
587 };
588
589 static void fe_tx_dma_write_desc(struct fe_tx_ring *ring, struct fe_map_state *st)
590 {
591 fe_set_txd(&st->txd, &ring->tx_dma[st->ring_idx]);
592 memset(&st->txd, 0, sizeof(st->txd));
593 st->txd.txd4 = st->def_txd4;
594 st->ring_idx = NEXT_TX_DESP_IDX(st->ring_idx);
595 }
596
597 static int __fe_tx_dma_map_page(struct fe_tx_ring *ring, struct fe_map_state *st,
598 struct page *page, size_t offset, size_t size)
599 {
600 struct device *dev = st->dev;
601 struct fe_tx_buf *tx_buf;
602 dma_addr_t mapped_addr;
603
604 mapped_addr = dma_map_page(dev, page, offset, size, DMA_TO_DEVICE);
605 if (unlikely(dma_mapping_error(dev, mapped_addr)))
606 return -EIO;
607
608 if (st->i && !(st->i & 1))
609 fe_tx_dma_write_desc(ring, st);
610
611 tx_buf = &ring->tx_buf[st->ring_idx];
612 if (st->i & 1) {
613 st->txd.txd3 = mapped_addr;
614 st->txd.txd2 |= TX_DMA_PLEN1(size);
615 dma_unmap_addr_set(tx_buf, dma_addr1, mapped_addr);
616 dma_unmap_len_set(tx_buf, dma_len1, size);
617 } else {
618 tx_buf->skb = (struct sk_buff *)DMA_DUMMY_DESC;
619 st->txd.txd1 = mapped_addr;
620 st->txd.txd2 = TX_DMA_PLEN0(size);
621 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
622 dma_unmap_len_set(tx_buf, dma_len0, size);
623 }
624 st->i++;
625
626 return 0;
627 }
628
629 static int fe_tx_dma_map_page(struct fe_tx_ring *ring, struct fe_map_state *st,
630 struct page *page, size_t offset, size_t size)
631 {
632 int cur_size;
633 int ret;
634
635 while (size > 0) {
636 cur_size = min_t(size_t, size, TX_DMA_BUF_LEN);
637
638 ret = __fe_tx_dma_map_page(ring, st, page, offset, cur_size);
639 if (ret)
640 return ret;
641
642 size -= cur_size;
643 offset += cur_size;
644 }
645
646 return 0;
647 }
648
649 static int fe_tx_dma_map_skb(struct fe_tx_ring *ring, struct fe_map_state *st,
650 struct sk_buff *skb)
651 {
652 struct page *page = virt_to_page(skb->data);
653 size_t offset = offset_in_page(skb->data);
654 size_t size = skb_headlen(skb);
655
656 return fe_tx_dma_map_page(ring, st, page, offset, size);
657 }
658
659 static inline struct sk_buff *
660 fe_next_frag(struct sk_buff *head, struct sk_buff *skb)
661 {
662 if (skb != head)
663 return skb->next;
664
665 if (skb_has_frag_list(skb))
666 return skb_shinfo(skb)->frag_list;
667
668 return NULL;
669 }
670
671
672 static int fe_tx_map_dma(struct sk_buff *skb, struct net_device *dev,
673 int tx_num, struct fe_tx_ring *ring)
674 {
675 struct fe_priv *priv = netdev_priv(dev);
676 struct fe_map_state st = {
677 .dev = priv->dev,
678 .ring_idx = ring->tx_next_idx,
679 };
680 struct sk_buff *head = skb;
681 struct fe_tx_buf *tx_buf;
682 unsigned int nr_frags;
683 int i, j;
684
685 /* init tx descriptor */
686 if (priv->soc->tx_dma)
687 priv->soc->tx_dma(&st.txd);
688 else
689 st.txd.txd4 = TX_DMA_DESP4_DEF;
690 st.def_txd4 = st.txd.txd4;
691
692 /* TX Checksum offload */
693 if (skb->ip_summed == CHECKSUM_PARTIAL)
694 st.txd.txd4 |= TX_DMA_CHKSUM;
695
696 /* VLAN header offload */
697 if (skb_vlan_tag_present(skb)) {
698 u16 tag = skb_vlan_tag_get(skb);
699
700 if (IS_ENABLED(CONFIG_SOC_MT7621))
701 st.txd.txd4 |= TX_DMA_INS_VLAN_MT7621 | tag;
702 else
703 st.txd.txd4 |= TX_DMA_INS_VLAN |
704 ((tag >> VLAN_PRIO_SHIFT) << 4) |
705 (tag & 0xF);
706 }
707
708 /* TSO: fill MSS info in tcp checksum field */
709 if (skb_is_gso(skb)) {
710 if (skb_cow_head(skb, 0)) {
711 netif_warn(priv, tx_err, dev,
712 "GSO expand head fail.\n");
713 goto err_out;
714 }
715 if (skb_shinfo(skb)->gso_type &
716 (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
717 st.txd.txd4 |= TX_DMA_TSO;
718 tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size);
719 }
720 }
721
722 next_frag:
723 if (skb_headlen(skb) && fe_tx_dma_map_skb(ring, &st, skb))
724 goto err_dma;
725
726 /* TX SG offload */
727 nr_frags = skb_shinfo(skb)->nr_frags;
728 for (i = 0; i < nr_frags; i++) {
729 skb_frag_t *frag;
730
731 frag = &skb_shinfo(skb)->frags[i];
732 if (fe_tx_dma_map_page(ring, &st, skb_frag_page(frag),
733 skb_frag_off(frag), skb_frag_size(frag)))
734 goto err_dma;
735 }
736
737 skb = fe_next_frag(head, skb);
738 if (skb)
739 goto next_frag;
740
741 /* set last segment */
742 if (st.i & 0x1)
743 st.txd.txd2 |= TX_DMA_LS0;
744 else
745 st.txd.txd2 |= TX_DMA_LS1;
746
747 /* store skb to cleanup */
748 tx_buf = &ring->tx_buf[st.ring_idx];
749 tx_buf->skb = head;
750
751 netdev_sent_queue(dev, head->len);
752 skb_tx_timestamp(head);
753
754 fe_tx_dma_write_desc(ring, &st);
755 ring->tx_next_idx = st.ring_idx;
756
757 /* make sure that all changes to the dma ring are flushed before we
758 * continue
759 */
760 wmb();
761 if (unlikely(fe_empty_txd(ring) <= ring->tx_thresh)) {
762 netif_stop_queue(dev);
763 smp_mb();
764 if (unlikely(fe_empty_txd(ring) > ring->tx_thresh))
765 netif_wake_queue(dev);
766 }
767
768 if (netif_xmit_stopped(netdev_get_tx_queue(dev, 0)) || !netdev_xmit_more())
769 fe_reg_w32(ring->tx_next_idx, FE_REG_TX_CTX_IDX0);
770
771 return 0;
772
773 err_dma:
774 j = ring->tx_next_idx;
775 for (i = 0; i < tx_num; i++) {
776 /* unmap dma */
777 fe_txd_unmap(priv->dev, &ring->tx_buf[j]);
778 ring->tx_dma[j].txd2 = TX_DMA_DESP2_DEF;
779
780 j = NEXT_TX_DESP_IDX(j);
781 }
782 /* make sure that all changes to the dma ring are flushed before we
783 * continue
784 */
785 wmb();
786
787 err_out:
788 return -1;
789 }
790
791 static inline int fe_skb_padto(struct sk_buff *skb, struct fe_priv *priv)
792 {
793 unsigned int len;
794 int ret;
795
796 ret = 0;
797 if (unlikely(skb->len < VLAN_ETH_ZLEN)) {
798 if ((priv->flags & FE_FLAG_PADDING_64B) &&
799 !(priv->flags & FE_FLAG_PADDING_BUG))
800 return ret;
801
802 if (skb_vlan_tag_present(skb))
803 len = ETH_ZLEN;
804 else if (skb->protocol == cpu_to_be16(ETH_P_8021Q))
805 len = VLAN_ETH_ZLEN;
806 else if (!(priv->flags & FE_FLAG_PADDING_64B))
807 len = ETH_ZLEN;
808 else
809 return ret;
810
811 if (skb->len < len) {
812 ret = skb_pad(skb, len - skb->len);
813 if (ret < 0)
814 return ret;
815 skb->len = len;
816 skb_set_tail_pointer(skb, len);
817 }
818 }
819
820 return ret;
821 }
822
823 static inline int fe_cal_txd_req(struct sk_buff *skb)
824 {
825 struct sk_buff *head = skb;
826 int i, nfrags = 0;
827 skb_frag_t *frag;
828
829 next_frag:
830 nfrags++;
831 if (skb_is_gso(skb)) {
832 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
833 frag = &skb_shinfo(skb)->frags[i];
834 nfrags += DIV_ROUND_UP(skb_frag_size(frag), TX_DMA_BUF_LEN);
835 }
836 } else {
837 nfrags += skb_shinfo(skb)->nr_frags;
838 }
839
840 skb = fe_next_frag(head, skb);
841 if (skb)
842 goto next_frag;
843
844 return DIV_ROUND_UP(nfrags, 2);
845 }
846
847 static int fe_start_xmit(struct sk_buff *skb, struct net_device *dev)
848 {
849 struct fe_priv *priv = netdev_priv(dev);
850 struct fe_tx_ring *ring = &priv->tx_ring;
851 struct net_device_stats *stats = &dev->stats;
852 int tx_num;
853 int len = skb->len;
854
855 if (fe_skb_padto(skb, priv)) {
856 netif_warn(priv, tx_err, dev, "tx padding failed!\n");
857 return NETDEV_TX_OK;
858 }
859
860 tx_num = fe_cal_txd_req(skb);
861 if (unlikely(fe_empty_txd(ring) <= tx_num)) {
862 netif_stop_queue(dev);
863 netif_err(priv, tx_queued, dev,
864 "Tx Ring full when queue awake!\n");
865 return NETDEV_TX_BUSY;
866 }
867
868 if (fe_tx_map_dma(skb, dev, tx_num, ring) < 0) {
869 stats->tx_dropped++;
870 } else {
871 stats->tx_packets++;
872 stats->tx_bytes += len;
873 }
874
875 return NETDEV_TX_OK;
876 }
877
878 static int fe_poll_rx(struct napi_struct *napi, int budget,
879 struct fe_priv *priv, u32 rx_intr)
880 {
881 struct net_device *netdev = priv->netdev;
882 struct net_device_stats *stats = &netdev->stats;
883 struct fe_soc_data *soc = priv->soc;
884 struct fe_rx_ring *ring = &priv->rx_ring;
885 int idx = ring->rx_calc_idx;
886 u32 checksum_bit;
887 struct sk_buff *skb;
888 u8 *data, *new_data;
889 struct fe_rx_dma *rxd, trxd;
890 int done = 0, pad;
891
892 if (netdev->features & NETIF_F_RXCSUM)
893 checksum_bit = soc->checksum_bit;
894 else
895 checksum_bit = 0;
896
897 if (priv->flags & FE_FLAG_RX_2B_OFFSET)
898 pad = 0;
899 else
900 pad = NET_IP_ALIGN;
901
902 while (done < budget) {
903 unsigned int pktlen;
904 dma_addr_t dma_addr;
905
906 idx = NEXT_RX_DESP_IDX(idx);
907 rxd = &ring->rx_dma[idx];
908 data = ring->rx_data[idx];
909
910 fe_get_rxd(&trxd, rxd);
911 if (!(trxd.rxd2 & RX_DMA_DONE))
912 break;
913
914 /* alloc new buffer */
915 new_data = page_frag_alloc(&ring->frag_cache, ring->frag_size,
916 GFP_ATOMIC);
917 if (unlikely(!new_data)) {
918 stats->rx_dropped++;
919 goto release_desc;
920 }
921 dma_addr = dma_map_single(priv->dev,
922 new_data + NET_SKB_PAD + pad,
923 ring->rx_buf_size,
924 DMA_FROM_DEVICE);
925 if (unlikely(dma_mapping_error(priv->dev, dma_addr))) {
926 skb_free_frag(new_data);
927 goto release_desc;
928 }
929
930 /* receive data */
931 skb = build_skb(data, ring->frag_size);
932 if (unlikely(!skb)) {
933 skb_free_frag(new_data);
934 goto release_desc;
935 }
936 skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN);
937
938 dma_unmap_single(priv->dev, trxd.rxd1,
939 ring->rx_buf_size, DMA_FROM_DEVICE);
940 pktlen = RX_DMA_GET_PLEN0(trxd.rxd2);
941 skb->dev = netdev;
942 skb_put(skb, pktlen);
943 if (trxd.rxd4 & checksum_bit)
944 skb->ip_summed = CHECKSUM_UNNECESSARY;
945 else
946 skb_checksum_none_assert(skb);
947 skb->protocol = eth_type_trans(skb, netdev);
948
949 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX &&
950 RX_DMA_VID(trxd.rxd3))
951 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
952 RX_DMA_VID(trxd.rxd3));
953
954 stats->rx_packets++;
955 stats->rx_bytes += pktlen;
956
957 napi_gro_receive(napi, skb);
958
959 ring->rx_data[idx] = new_data;
960 rxd->rxd1 = (unsigned int)dma_addr;
961
962 release_desc:
963 if (priv->flags & FE_FLAG_RX_SG_DMA)
964 rxd->rxd2 = RX_DMA_PLEN0(ring->rx_buf_size);
965 else
966 rxd->rxd2 = RX_DMA_LSO;
967
968 ring->rx_calc_idx = idx;
969 /* make sure that all changes to the dma ring are flushed before
970 * we continue
971 */
972 wmb();
973 fe_reg_w32(ring->rx_calc_idx, FE_REG_RX_CALC_IDX0);
974 done++;
975 }
976
977 if (done < budget)
978 fe_reg_w32(rx_intr, FE_REG_FE_INT_STATUS);
979
980 return done;
981 }
982
983 static int fe_poll_tx(struct fe_priv *priv, int budget, u32 tx_intr,
984 int *tx_again)
985 {
986 struct net_device *netdev = priv->netdev;
987 unsigned int bytes_compl = 0;
988 struct sk_buff *skb;
989 struct fe_tx_buf *tx_buf;
990 int done = 0;
991 u32 idx, hwidx;
992 struct fe_tx_ring *ring = &priv->tx_ring;
993
994 idx = ring->tx_free_idx;
995 hwidx = fe_reg_r32(FE_REG_TX_DTX_IDX0);
996
997 while ((idx != hwidx) && budget) {
998 tx_buf = &ring->tx_buf[idx];
999 skb = tx_buf->skb;
1000
1001 if (!skb)
1002 break;
1003
1004 if (skb != (struct sk_buff *)DMA_DUMMY_DESC) {
1005 bytes_compl += skb->len;
1006 done++;
1007 budget--;
1008 }
1009 fe_txd_unmap(priv->dev, tx_buf);
1010 idx = NEXT_TX_DESP_IDX(idx);
1011 }
1012 ring->tx_free_idx = idx;
1013
1014 if (idx == hwidx) {
1015 /* read hw index again make sure no new tx packet */
1016 hwidx = fe_reg_r32(FE_REG_TX_DTX_IDX0);
1017 if (idx == hwidx)
1018 fe_reg_w32(tx_intr, FE_REG_FE_INT_STATUS);
1019 else
1020 *tx_again = 1;
1021 } else {
1022 *tx_again = 1;
1023 }
1024
1025 if (done) {
1026 netdev_completed_queue(netdev, done, bytes_compl);
1027 smp_mb();
1028 if (unlikely(netif_queue_stopped(netdev) &&
1029 (fe_empty_txd(ring) > ring->tx_thresh)))
1030 netif_wake_queue(netdev);
1031 }
1032
1033 return done;
1034 }
1035
1036 static int fe_poll(struct napi_struct *napi, int budget)
1037 {
1038 struct fe_priv *priv = container_of(napi, struct fe_priv, rx_napi);
1039 struct fe_hw_stats *hwstat = priv->hw_stats;
1040 int tx_done, rx_done, tx_again;
1041 u32 status, fe_status, status_reg, mask;
1042 u32 tx_intr, rx_intr, status_intr;
1043
1044 status = fe_reg_r32(FE_REG_FE_INT_STATUS);
1045 fe_status = status;
1046 tx_intr = priv->soc->tx_int;
1047 rx_intr = priv->soc->rx_int;
1048 status_intr = priv->soc->status_int;
1049 tx_done = 0;
1050 rx_done = 0;
1051 tx_again = 0;
1052
1053 if (fe_reg_table[FE_REG_FE_INT_STATUS2]) {
1054 fe_status = fe_reg_r32(FE_REG_FE_INT_STATUS2);
1055 status_reg = FE_REG_FE_INT_STATUS2;
1056 } else {
1057 status_reg = FE_REG_FE_INT_STATUS;
1058 }
1059
1060 if (status & tx_intr)
1061 tx_done = fe_poll_tx(priv, budget, tx_intr, &tx_again);
1062
1063 if (status & rx_intr)
1064 rx_done = fe_poll_rx(napi, budget, priv, rx_intr);
1065
1066 if (unlikely(fe_status & status_intr)) {
1067 if (hwstat && spin_trylock(&hwstat->stats_lock)) {
1068 fe_stats_update(priv);
1069 spin_unlock(&hwstat->stats_lock);
1070 }
1071 fe_reg_w32(status_intr, status_reg);
1072 }
1073
1074 if (unlikely(netif_msg_intr(priv))) {
1075 mask = fe_reg_r32(FE_REG_FE_INT_ENABLE);
1076 netdev_info(priv->netdev,
1077 "done tx %d, rx %d, intr 0x%08x/0x%x\n",
1078 tx_done, rx_done, status, mask);
1079 }
1080
1081 if (!tx_again && (rx_done < budget)) {
1082 status = fe_reg_r32(FE_REG_FE_INT_STATUS);
1083 if (status & (tx_intr | rx_intr)) {
1084 /* let napi poll again */
1085 rx_done = budget;
1086 goto poll_again;
1087 }
1088
1089 napi_complete_done(napi, rx_done);
1090 fe_int_enable(tx_intr | rx_intr);
1091 } else {
1092 rx_done = budget;
1093 }
1094
1095 poll_again:
1096 return rx_done;
1097 }
1098
1099 static void fe_tx_timeout(struct net_device *dev, unsigned int txqueue)
1100 {
1101 struct fe_priv *priv = netdev_priv(dev);
1102 struct fe_tx_ring *ring = &priv->tx_ring;
1103
1104 priv->netdev->stats.tx_errors++;
1105 netif_err(priv, tx_err, dev,
1106 "transmit timed out\n");
1107 netif_info(priv, drv, dev, "dma_cfg:%08x\n",
1108 fe_reg_r32(FE_REG_PDMA_GLO_CFG));
1109 netif_info(priv, drv, dev, "tx_ring=%d, "
1110 "base=%08x, max=%u, ctx=%u, dtx=%u, fdx=%hu, next=%hu\n",
1111 0, fe_reg_r32(FE_REG_TX_BASE_PTR0),
1112 fe_reg_r32(FE_REG_TX_MAX_CNT0),
1113 fe_reg_r32(FE_REG_TX_CTX_IDX0),
1114 fe_reg_r32(FE_REG_TX_DTX_IDX0),
1115 ring->tx_free_idx,
1116 ring->tx_next_idx);
1117 netif_info(priv, drv, dev,
1118 "rx_ring=%d, base=%08x, max=%u, calc=%u, drx=%u\n",
1119 0, fe_reg_r32(FE_REG_RX_BASE_PTR0),
1120 fe_reg_r32(FE_REG_RX_MAX_CNT0),
1121 fe_reg_r32(FE_REG_RX_CALC_IDX0),
1122 fe_reg_r32(FE_REG_RX_DRX_IDX0));
1123
1124 if (!test_and_set_bit(FE_FLAG_RESET_PENDING, priv->pending_flags))
1125 schedule_work(&priv->pending_work);
1126 }
1127
1128 static irqreturn_t fe_handle_irq(int irq, void *dev)
1129 {
1130 struct fe_priv *priv = netdev_priv(dev);
1131 u32 status, int_mask;
1132
1133 status = fe_reg_r32(FE_REG_FE_INT_STATUS);
1134
1135 if (unlikely(!status))
1136 return IRQ_NONE;
1137
1138 int_mask = (priv->soc->rx_int | priv->soc->tx_int);
1139 if (likely(status & int_mask)) {
1140 if (likely(napi_schedule_prep(&priv->rx_napi))) {
1141 fe_int_disable(int_mask);
1142 __napi_schedule(&priv->rx_napi);
1143 }
1144 } else {
1145 fe_reg_w32(status, FE_REG_FE_INT_STATUS);
1146 }
1147
1148 return IRQ_HANDLED;
1149 }
1150
1151 #ifdef CONFIG_NET_POLL_CONTROLLER
1152 static void fe_poll_controller(struct net_device *dev)
1153 {
1154 struct fe_priv *priv = netdev_priv(dev);
1155 u32 int_mask = priv->soc->tx_int | priv->soc->rx_int;
1156
1157 fe_int_disable(int_mask);
1158 fe_handle_irq(dev->irq, dev);
1159 fe_int_enable(int_mask);
1160 }
1161 #endif
1162
1163 int fe_set_clock_cycle(struct fe_priv *priv)
1164 {
1165 unsigned long sysclk = priv->sysclk;
1166
1167 sysclk /= FE_US_CYC_CNT_DIVISOR;
1168 sysclk <<= FE_US_CYC_CNT_SHIFT;
1169
1170 fe_w32((fe_r32(FE_FE_GLO_CFG) &
1171 ~(FE_US_CYC_CNT_MASK << FE_US_CYC_CNT_SHIFT)) |
1172 sysclk,
1173 FE_FE_GLO_CFG);
1174 return 0;
1175 }
1176
1177 void fe_fwd_config(struct fe_priv *priv)
1178 {
1179 u32 fwd_cfg;
1180
1181 fwd_cfg = fe_r32(FE_GDMA1_FWD_CFG);
1182
1183 /* disable jumbo frame */
1184 if (priv->flags & FE_FLAG_JUMBO_FRAME)
1185 fwd_cfg &= ~FE_GDM1_JMB_EN;
1186
1187 /* set unicast/multicast/broadcast frame to cpu */
1188 fwd_cfg &= ~0xffff;
1189
1190 fe_w32(fwd_cfg, FE_GDMA1_FWD_CFG);
1191 }
1192
1193 static void fe_rxcsum_config(bool enable)
1194 {
1195 if (enable)
1196 fe_w32(fe_r32(FE_GDMA1_FWD_CFG) | (FE_GDM1_ICS_EN |
1197 FE_GDM1_TCS_EN | FE_GDM1_UCS_EN),
1198 FE_GDMA1_FWD_CFG);
1199 else
1200 fe_w32(fe_r32(FE_GDMA1_FWD_CFG) & ~(FE_GDM1_ICS_EN |
1201 FE_GDM1_TCS_EN | FE_GDM1_UCS_EN),
1202 FE_GDMA1_FWD_CFG);
1203 }
1204
1205 static void fe_txcsum_config(bool enable)
1206 {
1207 if (enable)
1208 fe_w32(fe_r32(FE_CDMA_CSG_CFG) | (FE_ICS_GEN_EN |
1209 FE_TCS_GEN_EN | FE_UCS_GEN_EN),
1210 FE_CDMA_CSG_CFG);
1211 else
1212 fe_w32(fe_r32(FE_CDMA_CSG_CFG) & ~(FE_ICS_GEN_EN |
1213 FE_TCS_GEN_EN | FE_UCS_GEN_EN),
1214 FE_CDMA_CSG_CFG);
1215 }
1216
1217 void fe_csum_config(struct fe_priv *priv)
1218 {
1219 struct net_device *dev = priv_netdev(priv);
1220
1221 fe_txcsum_config((dev->features & NETIF_F_IP_CSUM));
1222 fe_rxcsum_config((dev->features & NETIF_F_RXCSUM));
1223 }
1224
1225 static int fe_hw_init(struct net_device *dev)
1226 {
1227 struct fe_priv *priv = netdev_priv(dev);
1228 int i, err;
1229
1230 err = devm_request_irq(priv->dev, dev->irq, fe_handle_irq, 0,
1231 dev_name(priv->dev), dev);
1232 if (err)
1233 return err;
1234
1235 if (priv->soc->set_mac)
1236 priv->soc->set_mac(priv, dev->dev_addr);
1237 else
1238 fe_hw_set_macaddr(priv, dev->dev_addr);
1239
1240 /* disable delay interrupt */
1241 fe_reg_w32(0, FE_REG_DLY_INT_CFG);
1242
1243 fe_int_disable(priv->soc->tx_int | priv->soc->rx_int);
1244
1245 /* frame engine will push VLAN tag regarding to VIDX feild in Tx desc */
1246 if (fe_reg_table[FE_REG_FE_DMA_VID_BASE])
1247 for (i = 0; i < 16; i += 2)
1248 fe_w32(((i + 1) << 16) + i,
1249 fe_reg_table[FE_REG_FE_DMA_VID_BASE] +
1250 (i * 2));
1251
1252 if (priv->soc->fwd_config(priv))
1253 netdev_err(dev, "unable to get clock\n");
1254
1255 if (fe_reg_table[FE_REG_FE_RST_GL]) {
1256 fe_reg_w32(1, FE_REG_FE_RST_GL);
1257 fe_reg_w32(0, FE_REG_FE_RST_GL);
1258 }
1259
1260 return 0;
1261 }
1262
1263 static int fe_open(struct net_device *dev)
1264 {
1265 struct fe_priv *priv = netdev_priv(dev);
1266 unsigned long flags;
1267 u32 val;
1268 int err;
1269
1270 err = fe_init_dma(priv);
1271 if (err) {
1272 fe_free_dma(priv);
1273 return err;
1274 }
1275
1276 spin_lock_irqsave(&priv->page_lock, flags);
1277
1278 val = FE_TX_WB_DDONE | FE_RX_DMA_EN | FE_TX_DMA_EN;
1279 if (priv->flags & FE_FLAG_RX_2B_OFFSET)
1280 val |= FE_RX_2B_OFFSET;
1281 val |= priv->soc->pdma_glo_cfg;
1282 fe_reg_w32(val, FE_REG_PDMA_GLO_CFG);
1283
1284 spin_unlock_irqrestore(&priv->page_lock, flags);
1285
1286 if (priv->phy)
1287 priv->phy->start(priv);
1288
1289 if (priv->soc->has_carrier && priv->soc->has_carrier(priv))
1290 netif_carrier_on(dev);
1291
1292 napi_enable(&priv->rx_napi);
1293 fe_int_enable(priv->soc->tx_int | priv->soc->rx_int);
1294 netif_start_queue(dev);
1295
1296 return 0;
1297 }
1298
1299 static int fe_stop(struct net_device *dev)
1300 {
1301 struct fe_priv *priv = netdev_priv(dev);
1302 unsigned long flags;
1303 int i;
1304
1305 netif_tx_disable(dev);
1306 fe_int_disable(priv->soc->tx_int | priv->soc->rx_int);
1307 napi_disable(&priv->rx_napi);
1308
1309 if (priv->phy)
1310 priv->phy->stop(priv);
1311
1312 spin_lock_irqsave(&priv->page_lock, flags);
1313
1314 fe_reg_w32(fe_reg_r32(FE_REG_PDMA_GLO_CFG) &
1315 ~(FE_TX_WB_DDONE | FE_RX_DMA_EN | FE_TX_DMA_EN),
1316 FE_REG_PDMA_GLO_CFG);
1317 spin_unlock_irqrestore(&priv->page_lock, flags);
1318
1319 /* wait dma stop */
1320 for (i = 0; i < 10; i++) {
1321 if (fe_reg_r32(FE_REG_PDMA_GLO_CFG) &
1322 (FE_TX_DMA_BUSY | FE_RX_DMA_BUSY)) {
1323 msleep(20);
1324 continue;
1325 }
1326 break;
1327 }
1328
1329 fe_free_dma(priv);
1330
1331 return 0;
1332 }
1333
1334 static void fe_reset_phy(struct fe_priv *priv)
1335 {
1336 int err, msec = 30;
1337 struct gpio_desc *phy_reset;
1338
1339 phy_reset = devm_gpiod_get_optional(priv->dev, "phy-reset",
1340 GPIOD_OUT_HIGH);
1341 if (!phy_reset)
1342 return;
1343
1344 if (IS_ERR(phy_reset)) {
1345 dev_err(priv->dev, "Error acquiring reset gpio pins: %ld\n",
1346 PTR_ERR(phy_reset));
1347 return;
1348 }
1349
1350 err = of_property_read_u32(priv->dev->of_node, "phy-reset-duration",
1351 &msec);
1352 if (!err && msec > 1000)
1353 msec = 30;
1354
1355 if (msec > 20)
1356 msleep(msec);
1357 else
1358 usleep_range(msec * 1000, msec * 1000 + 1000);
1359
1360 gpiod_set_value(phy_reset, 0);
1361 }
1362
1363 static int __init fe_init(struct net_device *dev)
1364 {
1365 struct fe_priv *priv = netdev_priv(dev);
1366 struct device_node *port;
1367 int err;
1368
1369 if (priv->soc->reset_fe)
1370 priv->soc->reset_fe(priv);
1371 else
1372 fe_reset_fe(priv);
1373
1374 if (priv->soc->switch_init) {
1375 err = priv->soc->switch_init(priv);
1376 if (err) {
1377 if (err == -EPROBE_DEFER)
1378 return err;
1379
1380 netdev_err(dev, "failed to initialize switch core\n");
1381 return -ENODEV;
1382 }
1383 }
1384
1385 fe_reset_phy(priv);
1386
1387 of_get_mac_address(priv->dev->of_node, dev->dev_addr);
1388
1389 /* If the mac address is invalid, use random mac address */
1390 if (!is_valid_ether_addr(dev->dev_addr)) {
1391 eth_hw_addr_random(dev);
1392 dev_err(priv->dev, "generated random MAC address %pM\n",
1393 dev->dev_addr);
1394 }
1395
1396 err = fe_mdio_init(priv);
1397 if (err)
1398 return err;
1399
1400 if (priv->soc->port_init)
1401 for_each_child_of_node(priv->dev->of_node, port)
1402 if (of_device_is_compatible(port, "mediatek,eth-port") &&
1403 of_device_is_available(port))
1404 priv->soc->port_init(priv, port);
1405
1406 if (priv->phy) {
1407 err = priv->phy->connect(priv);
1408 if (err)
1409 goto err_phy_disconnect;
1410 }
1411
1412 err = fe_hw_init(dev);
1413 if (err)
1414 goto err_phy_disconnect;
1415
1416 if ((priv->flags & FE_FLAG_HAS_SWITCH) && priv->soc->switch_config)
1417 priv->soc->switch_config(priv);
1418
1419 return 0;
1420
1421 err_phy_disconnect:
1422 if (priv->phy)
1423 priv->phy->disconnect(priv);
1424 fe_mdio_cleanup(priv);
1425
1426 return err;
1427 }
1428
1429 static void fe_uninit(struct net_device *dev)
1430 {
1431 struct fe_priv *priv = netdev_priv(dev);
1432
1433 if (priv->phy)
1434 priv->phy->disconnect(priv);
1435 fe_mdio_cleanup(priv);
1436
1437 fe_reg_w32(0, FE_REG_FE_INT_ENABLE);
1438 free_irq(dev->irq, dev);
1439 }
1440
1441 static int fe_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1442 {
1443 struct fe_priv *priv = netdev_priv(dev);
1444
1445 if (!priv->phy_dev)
1446 return -ENODEV;
1447
1448
1449 return phy_mii_ioctl(priv->phy_dev, ifr, cmd);
1450 }
1451
1452 static int fe_change_mtu(struct net_device *dev, int new_mtu)
1453 {
1454 struct fe_priv *priv = netdev_priv(dev);
1455 int frag_size, old_mtu;
1456 u32 fwd_cfg;
1457
1458 old_mtu = dev->mtu;
1459 dev->mtu = new_mtu;
1460
1461 if (!(priv->flags & FE_FLAG_JUMBO_FRAME))
1462 return 0;
1463
1464 /* return early if the buffer sizes will not change */
1465 if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
1466 return 0;
1467 if (old_mtu > ETH_DATA_LEN && new_mtu > ETH_DATA_LEN)
1468 return 0;
1469
1470 if (new_mtu <= ETH_DATA_LEN)
1471 priv->rx_ring.frag_size = fe_max_frag_size(ETH_DATA_LEN);
1472 else
1473 priv->rx_ring.frag_size = PAGE_SIZE;
1474 priv->rx_ring.rx_buf_size = fe_max_buf_size(priv->rx_ring.frag_size);
1475
1476 if (!netif_running(dev))
1477 return 0;
1478
1479 fe_stop(dev);
1480 if (!IS_ENABLED(CONFIG_SOC_MT7621)) {
1481 fwd_cfg = fe_r32(FE_GDMA1_FWD_CFG);
1482 if (new_mtu <= ETH_DATA_LEN) {
1483 fwd_cfg &= ~FE_GDM1_JMB_EN;
1484 } else {
1485 frag_size = fe_max_frag_size(new_mtu);
1486 fwd_cfg &= ~(FE_GDM1_JMB_LEN_MASK << FE_GDM1_JMB_LEN_SHIFT);
1487 fwd_cfg |= (DIV_ROUND_UP(frag_size, 1024) <<
1488 FE_GDM1_JMB_LEN_SHIFT) | FE_GDM1_JMB_EN;
1489 }
1490 fe_w32(fwd_cfg, FE_GDMA1_FWD_CFG);
1491 }
1492
1493 return fe_open(dev);
1494 }
1495
1496 static const struct net_device_ops fe_netdev_ops = {
1497 .ndo_init = fe_init,
1498 .ndo_uninit = fe_uninit,
1499 .ndo_open = fe_open,
1500 .ndo_stop = fe_stop,
1501 .ndo_start_xmit = fe_start_xmit,
1502 .ndo_set_mac_address = fe_set_mac_address,
1503 .ndo_validate_addr = eth_validate_addr,
1504 .ndo_do_ioctl = fe_do_ioctl,
1505 .ndo_change_mtu = fe_change_mtu,
1506 .ndo_tx_timeout = fe_tx_timeout,
1507 .ndo_get_stats64 = fe_get_stats64,
1508 .ndo_vlan_rx_add_vid = fe_vlan_rx_add_vid,
1509 .ndo_vlan_rx_kill_vid = fe_vlan_rx_kill_vid,
1510 #ifdef CONFIG_NET_POLL_CONTROLLER
1511 .ndo_poll_controller = fe_poll_controller,
1512 #endif
1513 };
1514
1515 static void fe_reset_pending(struct fe_priv *priv)
1516 {
1517 struct net_device *dev = priv->netdev;
1518 int err;
1519
1520 rtnl_lock();
1521 fe_stop(dev);
1522
1523 err = fe_open(dev);
1524 if (err) {
1525 netif_alert(priv, ifup, dev,
1526 "Driver up/down cycle failed, closing device.\n");
1527 dev_close(dev);
1528 }
1529 rtnl_unlock();
1530 }
1531
1532 static const struct fe_work_t fe_work[] = {
1533 {FE_FLAG_RESET_PENDING, fe_reset_pending},
1534 };
1535
1536 static void fe_pending_work(struct work_struct *work)
1537 {
1538 struct fe_priv *priv = container_of(work, struct fe_priv, pending_work);
1539 int i;
1540 bool pending;
1541
1542 for (i = 0; i < ARRAY_SIZE(fe_work); i++) {
1543 pending = test_and_clear_bit(fe_work[i].bitnr,
1544 priv->pending_flags);
1545 if (pending)
1546 fe_work[i].action(priv);
1547 }
1548 }
1549
1550 static int fe_probe(struct platform_device *pdev)
1551 {
1552 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1553 const struct of_device_id *match;
1554 struct fe_soc_data *soc;
1555 struct net_device *netdev;
1556 struct fe_priv *priv;
1557 struct clk *sysclk;
1558 int err, napi_weight;
1559
1560 err = device_reset(&pdev->dev);
1561 if (err)
1562 dev_err(&pdev->dev, "failed to reset device\n");
1563
1564 match = of_match_device(of_fe_match, &pdev->dev);
1565 soc = (struct fe_soc_data *)match->data;
1566
1567 if (soc->reg_table)
1568 fe_reg_table = soc->reg_table;
1569 else
1570 soc->reg_table = fe_reg_table;
1571
1572 fe_base = devm_ioremap_resource(&pdev->dev, res);
1573 if (IS_ERR(fe_base)) {
1574 err = -EADDRNOTAVAIL;
1575 goto err_out;
1576 }
1577
1578 netdev = alloc_etherdev(sizeof(*priv));
1579 if (!netdev) {
1580 dev_err(&pdev->dev, "alloc_etherdev failed\n");
1581 err = -ENOMEM;
1582 goto err_iounmap;
1583 }
1584
1585 SET_NETDEV_DEV(netdev, &pdev->dev);
1586 netdev->netdev_ops = &fe_netdev_ops;
1587 netdev->base_addr = (unsigned long)fe_base;
1588
1589 netdev->irq = platform_get_irq(pdev, 0);
1590 if (netdev->irq < 0) {
1591 dev_err(&pdev->dev, "no IRQ resource found\n");
1592 err = -ENXIO;
1593 goto err_free_dev;
1594 }
1595
1596 priv = netdev_priv(netdev);
1597 spin_lock_init(&priv->page_lock);
1598 priv->rst_fe = devm_reset_control_get(&pdev->dev, "fe");
1599 if (IS_ERR(priv->rst_fe))
1600 priv->rst_fe = NULL;
1601
1602 if (soc->init_data)
1603 soc->init_data(soc, netdev);
1604 netdev->vlan_features = netdev->hw_features &
1605 ~(NETIF_F_HW_VLAN_CTAG_TX |
1606 NETIF_F_HW_VLAN_CTAG_RX);
1607 netdev->features |= netdev->hw_features;
1608
1609 if (IS_ENABLED(CONFIG_SOC_MT7621))
1610 netdev->max_mtu = 2048;
1611
1612 /* fake rx vlan filter func. to support tx vlan offload func */
1613 if (fe_reg_table[FE_REG_FE_DMA_VID_BASE])
1614 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
1615
1616 if (fe_reg_table[FE_REG_FE_COUNTER_BASE]) {
1617 priv->hw_stats = kzalloc(sizeof(*priv->hw_stats), GFP_KERNEL);
1618 if (!priv->hw_stats) {
1619 err = -ENOMEM;
1620 goto err_free_dev;
1621 }
1622 spin_lock_init(&priv->hw_stats->stats_lock);
1623 }
1624
1625 sysclk = devm_clk_get(&pdev->dev, NULL);
1626 if (!IS_ERR(sysclk)) {
1627 priv->sysclk = clk_get_rate(sysclk);
1628 } else if ((priv->flags & FE_FLAG_CALIBRATE_CLK)) {
1629 dev_err(&pdev->dev, "this soc needs a clk for calibration\n");
1630 err = -ENXIO;
1631 goto err_free_dev;
1632 }
1633
1634 priv->switch_np = of_parse_phandle(pdev->dev.of_node, "mediatek,switch", 0);
1635 if ((priv->flags & FE_FLAG_HAS_SWITCH) && !priv->switch_np) {
1636 dev_err(&pdev->dev, "failed to read switch phandle\n");
1637 err = -ENODEV;
1638 goto err_free_dev;
1639 }
1640
1641 priv->netdev = netdev;
1642 priv->dev = &pdev->dev;
1643 priv->soc = soc;
1644 priv->msg_enable = netif_msg_init(fe_msg_level, FE_DEFAULT_MSG_ENABLE);
1645 priv->rx_ring.frag_size = fe_max_frag_size(ETH_DATA_LEN);
1646 priv->rx_ring.rx_buf_size = fe_max_buf_size(priv->rx_ring.frag_size);
1647 priv->tx_ring.tx_ring_size = NUM_DMA_DESC;
1648 priv->rx_ring.rx_ring_size = NUM_DMA_DESC;
1649 INIT_WORK(&priv->pending_work, fe_pending_work);
1650 u64_stats_init(&priv->hw_stats->syncp);
1651
1652 napi_weight = 16;
1653 if (priv->flags & FE_FLAG_NAPI_WEIGHT) {
1654 napi_weight *= 4;
1655 priv->tx_ring.tx_ring_size *= 4;
1656 priv->rx_ring.rx_ring_size *= 4;
1657 }
1658 netif_napi_add(netdev, &priv->rx_napi, fe_poll, napi_weight);
1659 fe_set_ethtool_ops(netdev);
1660
1661 err = register_netdev(netdev);
1662 if (err) {
1663 dev_err(&pdev->dev, "error bringing up device\n");
1664 goto err_free_dev;
1665 }
1666
1667 platform_set_drvdata(pdev, netdev);
1668
1669 netif_info(priv, probe, netdev, "mediatek frame engine at 0x%08lx, irq %d\n",
1670 netdev->base_addr, netdev->irq);
1671
1672 return 0;
1673
1674 err_free_dev:
1675 free_netdev(netdev);
1676 err_iounmap:
1677 devm_iounmap(&pdev->dev, fe_base);
1678 err_out:
1679 return err;
1680 }
1681
1682 static int fe_remove(struct platform_device *pdev)
1683 {
1684 struct net_device *dev = platform_get_drvdata(pdev);
1685 struct fe_priv *priv = netdev_priv(dev);
1686
1687 netif_napi_del(&priv->rx_napi);
1688 kfree(priv->hw_stats);
1689
1690 cancel_work_sync(&priv->pending_work);
1691
1692 unregister_netdev(dev);
1693 free_netdev(dev);
1694 platform_set_drvdata(pdev, NULL);
1695
1696 return 0;
1697 }
1698
1699 static struct platform_driver fe_driver = {
1700 .probe = fe_probe,
1701 .remove = fe_remove,
1702 .driver = {
1703 .name = "mtk_soc_eth",
1704 .owner = THIS_MODULE,
1705 .of_match_table = of_fe_match,
1706 },
1707 };
1708
1709 module_platform_driver(fe_driver);
1710
1711 MODULE_LICENSE("GPL");
1712 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
1713 MODULE_DESCRIPTION("Ethernet driver for Ralink SoC");
1714 MODULE_VERSION(MTK_FE_DRV_VERSION);
OpenWrt Source Repository