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kernel: update 3.10 to 3.10.2
[openwrt/openwrt.git] / target / linux / ramips / patches-3.10 / 0016-NET-MIPS-add-ralink-SoC-ethernet-driver.patch
1 From ad11aedcc16574c0b3d3f5e40c67227d1846b94e Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Mon, 22 Apr 2013 23:20:03 +0200
4 Subject: [PATCH 16/33] NET: MIPS: add ralink SoC ethernet driver
5
6 Add support for Ralink FE and ESW.
7
8 Signed-off-by: John Crispin <blogic@openwrt.org>
9 ---
10 .../include/asm/mach-ralink/rt305x_esw_platform.h | 27 +
11 arch/mips/ralink/rt305x.c | 1 +
12 drivers/net/ethernet/Kconfig | 1 +
13 drivers/net/ethernet/Makefile | 1 +
14 drivers/net/ethernet/ralink/Kconfig | 31 +
15 drivers/net/ethernet/ralink/Makefile | 18 +
16 drivers/net/ethernet/ralink/esw_rt3052.c | 1463 ++++++++++++++++++++
17 drivers/net/ethernet/ralink/esw_rt3052.h | 32 +
18 drivers/net/ethernet/ralink/gsw_mt7620a.c | 1027 ++++++++++++++
19 drivers/net/ethernet/ralink/gsw_mt7620a.h | 29 +
20 drivers/net/ethernet/ralink/mdio.c | 245 ++++
21 drivers/net/ethernet/ralink/mdio.h | 29 +
22 drivers/net/ethernet/ralink/mdio_rt2880.c | 232 ++++
23 drivers/net/ethernet/ralink/mdio_rt2880.h | 26 +
24 drivers/net/ethernet/ralink/ralink_soc_eth.c | 735 ++++++++++
25 drivers/net/ethernet/ralink/ralink_soc_eth.h | 374 +++++
26 drivers/net/ethernet/ralink/soc_mt7620.c | 111 ++
27 drivers/net/ethernet/ralink/soc_rt2880.c | 51 +
28 drivers/net/ethernet/ralink/soc_rt305x.c | 113 ++
29 drivers/net/ethernet/ralink/soc_rt3883.c | 60 +
30 20 files changed, 4606 insertions(+)
31 create mode 100644 arch/mips/include/asm/mach-ralink/rt305x_esw_platform.h
32 create mode 100644 drivers/net/ethernet/ralink/Kconfig
33 create mode 100644 drivers/net/ethernet/ralink/Makefile
34 create mode 100644 drivers/net/ethernet/ralink/esw_rt3052.c
35 create mode 100644 drivers/net/ethernet/ralink/esw_rt3052.h
36 create mode 100644 drivers/net/ethernet/ralink/gsw_mt7620a.c
37 create mode 100644 drivers/net/ethernet/ralink/gsw_mt7620a.h
38 create mode 100644 drivers/net/ethernet/ralink/mdio.c
39 create mode 100644 drivers/net/ethernet/ralink/mdio.h
40 create mode 100644 drivers/net/ethernet/ralink/mdio_rt2880.c
41 create mode 100644 drivers/net/ethernet/ralink/mdio_rt2880.h
42 create mode 100644 drivers/net/ethernet/ralink/ralink_soc_eth.c
43 create mode 100644 drivers/net/ethernet/ralink/ralink_soc_eth.h
44 create mode 100644 drivers/net/ethernet/ralink/soc_mt7620.c
45 create mode 100644 drivers/net/ethernet/ralink/soc_rt2880.c
46 create mode 100644 drivers/net/ethernet/ralink/soc_rt305x.c
47 create mode 100644 drivers/net/ethernet/ralink/soc_rt3883.c
48
49 --- /dev/null
50 +++ b/arch/mips/include/asm/mach-ralink/rt305x_esw_platform.h
51 @@ -0,0 +1,27 @@
52 +/*
53 + * Ralink RT305x SoC platform device registration
54 + *
55 + * Copyright (C) 2010 Gabor Juhos <juhosg@openwrt.org>
56 + *
57 + * This program is free software; you can redistribute it and/or modify it
58 + * under the terms of the GNU General Public License version 2 as published
59 + * by the Free Software Foundation.
60 + */
61 +
62 +#ifndef _RT305X_ESW_PLATFORM_H
63 +#define _RT305X_ESW_PLATFORM_H
64 +
65 +enum {
66 + RT305X_ESW_VLAN_CONFIG_NONE = 0,
67 + RT305X_ESW_VLAN_CONFIG_LLLLW,
68 + RT305X_ESW_VLAN_CONFIG_WLLLL,
69 +};
70 +
71 +struct rt305x_esw_platform_data
72 +{
73 + u8 vlan_config;
74 + u32 reg_initval_fct2;
75 + u32 reg_initval_fpa2;
76 +};
77 +
78 +#endif /* _RT305X_ESW_PLATFORM_H */
79 --- a/arch/mips/ralink/rt305x.c
80 +++ b/arch/mips/ralink/rt305x.c
81 @@ -221,6 +221,7 @@ void __init ralink_clk_init(void)
82 }
83
84 ralink_clk_add("cpu", cpu_rate);
85 + ralink_clk_add("sys", sys_rate);
86 ralink_clk_add("10000b00.spi", sys_rate);
87 ralink_clk_add("10000100.timer", wdt_rate);
88 ralink_clk_add("10000120.watchdog", wdt_rate);
89 --- a/drivers/net/ethernet/Kconfig
90 +++ b/drivers/net/ethernet/Kconfig
91 @@ -135,6 +135,7 @@ config ETHOC
92 source "drivers/net/ethernet/packetengines/Kconfig"
93 source "drivers/net/ethernet/pasemi/Kconfig"
94 source "drivers/net/ethernet/qlogic/Kconfig"
95 +source "drivers/net/ethernet/ralink/Kconfig"
96 source "drivers/net/ethernet/realtek/Kconfig"
97 source "drivers/net/ethernet/renesas/Kconfig"
98 source "drivers/net/ethernet/rdc/Kconfig"
99 --- a/drivers/net/ethernet/Makefile
100 +++ b/drivers/net/ethernet/Makefile
101 @@ -53,6 +53,7 @@ obj-$(CONFIG_ETHOC) += ethoc.o
102 obj-$(CONFIG_NET_PACKET_ENGINE) += packetengines/
103 obj-$(CONFIG_NET_VENDOR_PASEMI) += pasemi/
104 obj-$(CONFIG_NET_VENDOR_QLOGIC) += qlogic/
105 +obj-$(CONFIG_NET_RALINK) += ralink/
106 obj-$(CONFIG_NET_VENDOR_REALTEK) += realtek/
107 obj-$(CONFIG_SH_ETH) += renesas/
108 obj-$(CONFIG_NET_VENDOR_RDC) += rdc/
109 --- /dev/null
110 +++ b/drivers/net/ethernet/ralink/Kconfig
111 @@ -0,0 +1,31 @@
112 +config NET_RALINK
113 + tristate "Ralink RT288X/RT3X5X/RT3662/RT3883/MT7620 ethernet driver"
114 + depends on RALINK
115 + help
116 + This driver supports the ethernet mac inside the ralink wisocs
117 +
118 +if NET_RALINK
119 +
120 +config NET_RALINK_MDIO
121 + def_bool NET_RALINK
122 + depends on (SOC_RT288X || SOC_RT3883 || SOC_MT7620)
123 + select PHYLIB
124 +
125 +config NET_RALINK_MDIO_RT2880
126 + def_bool NET_RALINK
127 + depends on (SOC_RT288X || SOC_RT3883)
128 + select NET_RALINK_MDIO
129 +
130 +config NET_RALINK_ESW_RT3052
131 + def_bool NET_RALINK
132 + depends on SOC_RT305X
133 + select PHYLIB
134 + select SWCONFIG
135 +
136 +config NET_RALINK_GSW_MT7620
137 + def_bool NET_RALINK
138 + depends on SOC_MT7620
139 + select NET_RALINK_MDIO
140 + select PHYLIB
141 + select SWCONFIG
142 +endif
143 --- /dev/null
144 +++ b/drivers/net/ethernet/ralink/Makefile
145 @@ -0,0 +1,18 @@
146 +#
147 +# Makefile for the Ralink SoCs built-in ethernet macs
148 +#
149 +
150 +ralink-eth-y += ralink_soc_eth.o
151 +
152 +ralink-eth-$(CONFIG_NET_RALINK_MDIO) += mdio.o
153 +ralink-eth-$(CONFIG_NET_RALINK_MDIO_RT2880) += mdio_rt2880.o
154 +
155 +ralink-eth-$(CONFIG_NET_RALINK_ESW_RT3052) += esw_rt3052.o
156 +ralink-eth-$(CONFIG_NET_RALINK_GSW_MT7620) += gsw_mt7620a.o
157 +
158 +ralink-eth-$(CONFIG_SOC_RT288X) += soc_rt2880.o
159 +ralink-eth-$(CONFIG_SOC_RT305X) += soc_rt305x.o
160 +ralink-eth-$(CONFIG_SOC_RT3883) += soc_rt3883.o
161 +ralink-eth-$(CONFIG_SOC_MT7620) += soc_mt7620.o
162 +
163 +obj-$(CONFIG_NET_RALINK) += ralink-eth.o
164 --- /dev/null
165 +++ b/drivers/net/ethernet/ralink/esw_rt3052.c
166 @@ -0,0 +1,1463 @@
167 +/*
168 + * This program is free software; you can redistribute it and/or modify
169 + * it under the terms of the GNU General Public License as published by
170 + * the Free Software Foundation; version 2 of the License
171 + *
172 + * This program is distributed in the hope that it will be useful,
173 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
174 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
175 + * GNU General Public License for more details.
176 + *
177 + * You should have received a copy of the GNU General Public License
178 + * along with this program; if not, write to the Free Software
179 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
180 + *
181 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
182 + */
183 +
184 +#include <linux/module.h>
185 +#include <linux/kernel.h>
186 +#include <linux/types.h>
187 +#include <linux/dma-mapping.h>
188 +#include <linux/init.h>
189 +#include <linux/skbuff.h>
190 +#include <linux/etherdevice.h>
191 +#include <linux/ethtool.h>
192 +#include <linux/platform_device.h>
193 +#include <linux/of_device.h>
194 +#include <linux/clk.h>
195 +#include <linux/of_net.h>
196 +#include <linux/of_mdio.h>
197 +
198 +#include <asm/mach-ralink/ralink_regs.h>
199 +
200 +#include "ralink_soc_eth.h"
201 +
202 +#include <linux/ioport.h>
203 +#include <linux/switch.h>
204 +#include <linux/mii.h>
205 +
206 +#include <ralink_regs.h>
207 +#include <asm/mach-ralink/rt305x.h>
208 +#include <asm/mach-ralink/rt305x_esw_platform.h>
209 +
210 +/*
211 + * HW limitations for this switch:
212 + * - No large frame support (PKT_MAX_LEN at most 1536)
213 + * - Can't have untagged vlan and tagged vlan on one port at the same time,
214 + * though this might be possible using the undocumented PPE.
215 + */
216 +
217 +#define RT305X_ESW_REG_ISR 0x00
218 +#define RT305X_ESW_REG_IMR 0x04
219 +#define RT305X_ESW_REG_FCT0 0x08
220 +#define RT305X_ESW_REG_PFC1 0x14
221 +#define RT305X_ESW_REG_ATS 0x24
222 +#define RT305X_ESW_REG_ATS0 0x28
223 +#define RT305X_ESW_REG_ATS1 0x2c
224 +#define RT305X_ESW_REG_ATS2 0x30
225 +#define RT305X_ESW_REG_PVIDC(_n) (0x40 + 4 * (_n))
226 +#define RT305X_ESW_REG_VLANI(_n) (0x50 + 4 * (_n))
227 +#define RT305X_ESW_REG_VMSC(_n) (0x70 + 4 * (_n))
228 +#define RT305X_ESW_REG_POA 0x80
229 +#define RT305X_ESW_REG_FPA 0x84
230 +#define RT305X_ESW_REG_SOCPC 0x8c
231 +#define RT305X_ESW_REG_POC0 0x90
232 +#define RT305X_ESW_REG_POC1 0x94
233 +#define RT305X_ESW_REG_POC2 0x98
234 +#define RT305X_ESW_REG_SGC 0x9c
235 +#define RT305X_ESW_REG_STRT 0xa0
236 +#define RT305X_ESW_REG_PCR0 0xc0
237 +#define RT305X_ESW_REG_PCR1 0xc4
238 +#define RT305X_ESW_REG_FPA2 0xc8
239 +#define RT305X_ESW_REG_FCT2 0xcc
240 +#define RT305X_ESW_REG_SGC2 0xe4
241 +#define RT305X_ESW_REG_P0LED 0xa4
242 +#define RT305X_ESW_REG_P1LED 0xa8
243 +#define RT305X_ESW_REG_P2LED 0xac
244 +#define RT305X_ESW_REG_P3LED 0xb0
245 +#define RT305X_ESW_REG_P4LED 0xb4
246 +#define RT305X_ESW_REG_PXPC(_x) (0xe8 + (4 * _x))
247 +#define RT305X_ESW_REG_P1PC 0xec
248 +#define RT305X_ESW_REG_P2PC 0xf0
249 +#define RT305X_ESW_REG_P3PC 0xf4
250 +#define RT305X_ESW_REG_P4PC 0xf8
251 +#define RT305X_ESW_REG_P5PC 0xfc
252 +
253 +#define RT305X_ESW_LED_LINK 0
254 +#define RT305X_ESW_LED_100M 1
255 +#define RT305X_ESW_LED_DUPLEX 2
256 +#define RT305X_ESW_LED_ACTIVITY 3
257 +#define RT305X_ESW_LED_COLLISION 4
258 +#define RT305X_ESW_LED_LINKACT 5
259 +#define RT305X_ESW_LED_DUPLCOLL 6
260 +#define RT305X_ESW_LED_10MACT 7
261 +#define RT305X_ESW_LED_100MACT 8
262 +/* Additional led states not in datasheet: */
263 +#define RT305X_ESW_LED_BLINK 10
264 +#define RT305X_ESW_LED_ON 12
265 +
266 +#define RT305X_ESW_LINK_S 25
267 +#define RT305X_ESW_DUPLEX_S 9
268 +#define RT305X_ESW_SPD_S 0
269 +
270 +#define RT305X_ESW_PCR0_WT_NWAY_DATA_S 16
271 +#define RT305X_ESW_PCR0_WT_PHY_CMD BIT(13)
272 +#define RT305X_ESW_PCR0_CPU_PHY_REG_S 8
273 +
274 +#define RT305X_ESW_PCR1_WT_DONE BIT(0)
275 +
276 +#define RT305X_ESW_ATS_TIMEOUT (5 * HZ)
277 +#define RT305X_ESW_PHY_TIMEOUT (5 * HZ)
278 +
279 +#define RT305X_ESW_PVIDC_PVID_M 0xfff
280 +#define RT305X_ESW_PVIDC_PVID_S 12
281 +
282 +#define RT305X_ESW_VLANI_VID_M 0xfff
283 +#define RT305X_ESW_VLANI_VID_S 12
284 +
285 +#define RT305X_ESW_VMSC_MSC_M 0xff
286 +#define RT305X_ESW_VMSC_MSC_S 8
287 +
288 +#define RT305X_ESW_SOCPC_DISUN2CPU_S 0
289 +#define RT305X_ESW_SOCPC_DISMC2CPU_S 8
290 +#define RT305X_ESW_SOCPC_DISBC2CPU_S 16
291 +#define RT305X_ESW_SOCPC_CRC_PADDING BIT(25)
292 +
293 +#define RT305X_ESW_POC0_EN_BP_S 0
294 +#define RT305X_ESW_POC0_EN_FC_S 8
295 +#define RT305X_ESW_POC0_DIS_RMC2CPU_S 16
296 +#define RT305X_ESW_POC0_DIS_PORT_M 0x7f
297 +#define RT305X_ESW_POC0_DIS_PORT_S 23
298 +
299 +#define RT305X_ESW_POC2_UNTAG_EN_M 0xff
300 +#define RT305X_ESW_POC2_UNTAG_EN_S 0
301 +#define RT305X_ESW_POC2_ENAGING_S 8
302 +#define RT305X_ESW_POC2_DIS_UC_PAUSE_S 16
303 +
304 +#define RT305X_ESW_SGC2_DOUBLE_TAG_M 0x7f
305 +#define RT305X_ESW_SGC2_DOUBLE_TAG_S 0
306 +#define RT305X_ESW_SGC2_LAN_PMAP_M 0x3f
307 +#define RT305X_ESW_SGC2_LAN_PMAP_S 24
308 +
309 +#define RT305X_ESW_PFC1_EN_VLAN_M 0xff
310 +#define RT305X_ESW_PFC1_EN_VLAN_S 16
311 +#define RT305X_ESW_PFC1_EN_TOS_S 24
312 +
313 +#define RT305X_ESW_VLAN_NONE 0xfff
314 +
315 +#define RT305X_ESW_GSC_BC_STROM_MASK 0x3
316 +#define RT305X_ESW_GSC_BC_STROM_SHIFT 4
317 +
318 +#define RT305X_ESW_GSC_LED_FREQ_MASK 0x3
319 +#define RT305X_ESW_GSC_LED_FREQ_SHIFT 23
320 +
321 +#define RT305X_ESW_POA_LINK_MASK 0x1f
322 +#define RT305X_ESW_POA_LINK_SHIFT 25
323 +
324 +#define RT305X_ESW_PORT_ST_CHG BIT(26)
325 +#define RT305X_ESW_PORT0 0
326 +#define RT305X_ESW_PORT1 1
327 +#define RT305X_ESW_PORT2 2
328 +#define RT305X_ESW_PORT3 3
329 +#define RT305X_ESW_PORT4 4
330 +#define RT305X_ESW_PORT5 5
331 +#define RT305X_ESW_PORT6 6
332 +
333 +#define RT305X_ESW_PORTS_NONE 0
334 +
335 +#define RT305X_ESW_PMAP_LLLLLL 0x3f
336 +#define RT305X_ESW_PMAP_LLLLWL 0x2f
337 +#define RT305X_ESW_PMAP_WLLLLL 0x3e
338 +
339 +#define RT305X_ESW_PORTS_INTERNAL \
340 + (BIT(RT305X_ESW_PORT0) | BIT(RT305X_ESW_PORT1) | \
341 + BIT(RT305X_ESW_PORT2) | BIT(RT305X_ESW_PORT3) | \
342 + BIT(RT305X_ESW_PORT4))
343 +
344 +#define RT305X_ESW_PORTS_NOCPU \
345 + (RT305X_ESW_PORTS_INTERNAL | BIT(RT305X_ESW_PORT5))
346 +
347 +#define RT305X_ESW_PORTS_CPU BIT(RT305X_ESW_PORT6)
348 +
349 +#define RT305X_ESW_PORTS_ALL \
350 + (RT305X_ESW_PORTS_NOCPU | RT305X_ESW_PORTS_CPU)
351 +
352 +#define RT305X_ESW_NUM_VLANS 16
353 +#define RT305X_ESW_NUM_VIDS 4096
354 +#define RT305X_ESW_NUM_PORTS 7
355 +#define RT305X_ESW_NUM_LANWAN 6
356 +#define RT305X_ESW_NUM_LEDS 5
357 +
358 +#define RT5350_ESW_REG_PXTPC(_x) (0x150 + (4 * _x))
359 +#define RT5350_EWS_REG_LED_POLARITY 0x168
360 +#define RT5350_RESET_EPHY BIT(24)
361 +#define SYSC_REG_RESET_CTRL 0x34
362 +
363 +enum {
364 + /* Global attributes. */
365 + RT305X_ESW_ATTR_ENABLE_VLAN,
366 + RT305X_ESW_ATTR_ALT_VLAN_DISABLE,
367 + RT305X_ESW_ATTR_BC_STATUS,
368 + RT305X_ESW_ATTR_LED_FREQ,
369 + /* Port attributes. */
370 + RT305X_ESW_ATTR_PORT_DISABLE,
371 + RT305X_ESW_ATTR_PORT_DOUBLETAG,
372 + RT305X_ESW_ATTR_PORT_UNTAG,
373 + RT305X_ESW_ATTR_PORT_LED,
374 + RT305X_ESW_ATTR_PORT_LAN,
375 + RT305X_ESW_ATTR_PORT_RECV_BAD,
376 + RT305X_ESW_ATTR_PORT_RECV_GOOD,
377 + RT5350_ESW_ATTR_PORT_TR_BAD,
378 + RT5350_ESW_ATTR_PORT_TR_GOOD,
379 +};
380 +
381 +struct esw_port {
382 + bool disable;
383 + bool doubletag;
384 + bool untag;
385 + u8 led;
386 + u16 pvid;
387 +};
388 +
389 +struct esw_vlan {
390 + u8 ports;
391 + u16 vid;
392 +};
393 +
394 +struct rt305x_esw {
395 + struct device *dev;
396 + void __iomem *base;
397 + int irq;
398 + const struct rt305x_esw_platform_data *pdata;
399 + /* Protects against concurrent register rmw operations. */
400 + spinlock_t reg_rw_lock;
401 +
402 + unsigned char port_map;
403 + unsigned int reg_initval_fct2;
404 + unsigned int reg_initval_fpa2;
405 + unsigned int reg_led_polarity;
406 +
407 +
408 + struct switch_dev swdev;
409 + bool global_vlan_enable;
410 + bool alt_vlan_disable;
411 + int bc_storm_protect;
412 + int led_frequency;
413 + struct esw_vlan vlans[RT305X_ESW_NUM_VLANS];
414 + struct esw_port ports[RT305X_ESW_NUM_PORTS];
415 +
416 +};
417 +
418 +static inline void esw_w32(struct rt305x_esw *esw, u32 val, unsigned reg)
419 +{
420 + __raw_writel(val, esw->base + reg);
421 +}
422 +
423 +static inline u32 esw_r32(struct rt305x_esw *esw, unsigned reg)
424 +{
425 + return __raw_readl(esw->base + reg);
426 +}
427 +
428 +static inline void esw_rmw_raw(struct rt305x_esw *esw, unsigned reg, unsigned long mask,
429 + unsigned long val)
430 +{
431 + unsigned long t;
432 +
433 + t = __raw_readl(esw->base + reg) & ~mask;
434 + __raw_writel(t | val, esw->base + reg);
435 +}
436 +
437 +static void esw_rmw(struct rt305x_esw *esw, unsigned reg, unsigned long mask,
438 + unsigned long val)
439 +{
440 + unsigned long flags;
441 +
442 + spin_lock_irqsave(&esw->reg_rw_lock, flags);
443 + esw_rmw_raw(esw, reg, mask, val);
444 + spin_unlock_irqrestore(&esw->reg_rw_lock, flags);
445 +}
446 +
447 +static u32 rt305x_mii_write(struct rt305x_esw *esw, u32 phy_addr, u32 phy_register,
448 + u32 write_data)
449 +{
450 + unsigned long t_start = jiffies;
451 + int ret = 0;
452 +
453 + while (1) {
454 + if (!(esw_r32(esw, RT305X_ESW_REG_PCR1) &
455 + RT305X_ESW_PCR1_WT_DONE))
456 + break;
457 + if (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) {
458 + ret = 1;
459 + goto out;
460 + }
461 + }
462 +
463 + write_data &= 0xffff;
464 + esw_w32(esw,
465 + (write_data << RT305X_ESW_PCR0_WT_NWAY_DATA_S) |
466 + (phy_register << RT305X_ESW_PCR0_CPU_PHY_REG_S) |
467 + (phy_addr) | RT305X_ESW_PCR0_WT_PHY_CMD,
468 + RT305X_ESW_REG_PCR0);
469 +
470 + t_start = jiffies;
471 + while (1) {
472 + if (esw_r32(esw, RT305X_ESW_REG_PCR1) &
473 + RT305X_ESW_PCR1_WT_DONE)
474 + break;
475 +
476 + if (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) {
477 + ret = 1;
478 + break;
479 + }
480 + }
481 +out:
482 + if (ret)
483 + printk(KERN_ERR "ramips_eth: MDIO timeout\n");
484 + return ret;
485 +}
486 +
487 +static unsigned esw_get_vlan_id(struct rt305x_esw *esw, unsigned vlan)
488 +{
489 + unsigned s;
490 + unsigned val;
491 +
492 + s = RT305X_ESW_VLANI_VID_S * (vlan % 2);
493 + val = esw_r32(esw, RT305X_ESW_REG_VLANI(vlan / 2));
494 + val = (val >> s) & RT305X_ESW_VLANI_VID_M;
495 +
496 + return val;
497 +}
498 +
499 +static void esw_set_vlan_id(struct rt305x_esw *esw, unsigned vlan, unsigned vid)
500 +{
501 + unsigned s;
502 +
503 + s = RT305X_ESW_VLANI_VID_S * (vlan % 2);
504 + esw_rmw(esw,
505 + RT305X_ESW_REG_VLANI(vlan / 2),
506 + RT305X_ESW_VLANI_VID_M << s,
507 + (vid & RT305X_ESW_VLANI_VID_M) << s);
508 +}
509 +
510 +static unsigned esw_get_pvid(struct rt305x_esw *esw, unsigned port)
511 +{
512 + unsigned s, val;
513 +
514 + s = RT305X_ESW_PVIDC_PVID_S * (port % 2);
515 + val = esw_r32(esw, RT305X_ESW_REG_PVIDC(port / 2));
516 + return (val >> s) & RT305X_ESW_PVIDC_PVID_M;
517 +}
518 +
519 +static void esw_set_pvid(struct rt305x_esw *esw, unsigned port, unsigned pvid)
520 +{
521 + unsigned s;
522 +
523 + s = RT305X_ESW_PVIDC_PVID_S * (port % 2);
524 + esw_rmw(esw,
525 + RT305X_ESW_REG_PVIDC(port / 2),
526 + RT305X_ESW_PVIDC_PVID_M << s,
527 + (pvid & RT305X_ESW_PVIDC_PVID_M) << s);
528 +}
529 +
530 +static unsigned esw_get_vmsc(struct rt305x_esw *esw, unsigned vlan)
531 +{
532 + unsigned s, val;
533 +
534 + s = RT305X_ESW_VMSC_MSC_S * (vlan % 4);
535 + val = esw_r32(esw, RT305X_ESW_REG_VMSC(vlan / 4));
536 + val = (val >> s) & RT305X_ESW_VMSC_MSC_M;
537 +
538 + return val;
539 +}
540 +
541 +static void esw_set_vmsc(struct rt305x_esw *esw, unsigned vlan, unsigned msc)
542 +{
543 + unsigned s;
544 +
545 + s = RT305X_ESW_VMSC_MSC_S * (vlan % 4);
546 + esw_rmw(esw,
547 + RT305X_ESW_REG_VMSC(vlan / 4),
548 + RT305X_ESW_VMSC_MSC_M << s,
549 + (msc & RT305X_ESW_VMSC_MSC_M) << s);
550 +}
551 +
552 +static unsigned esw_get_port_disable(struct rt305x_esw *esw)
553 +{
554 + unsigned reg;
555 + reg = esw_r32(esw, RT305X_ESW_REG_POC0);
556 + return (reg >> RT305X_ESW_POC0_DIS_PORT_S) &
557 + RT305X_ESW_POC0_DIS_PORT_M;
558 +}
559 +
560 +static void esw_set_port_disable(struct rt305x_esw *esw, unsigned disable_mask)
561 +{
562 + unsigned old_mask;
563 + unsigned enable_mask;
564 + unsigned changed;
565 + int i;
566 +
567 + old_mask = esw_get_port_disable(esw);
568 + changed = old_mask ^ disable_mask;
569 + enable_mask = old_mask & disable_mask;
570 +
571 + /* enable before writing to MII */
572 + esw_rmw(esw, RT305X_ESW_REG_POC0,
573 + (RT305X_ESW_POC0_DIS_PORT_M <<
574 + RT305X_ESW_POC0_DIS_PORT_S),
575 + enable_mask << RT305X_ESW_POC0_DIS_PORT_S);
576 +
577 + for (i = 0; i < RT305X_ESW_NUM_LEDS; i++) {
578 + if (!(changed & (1 << i)))
579 + continue;
580 + if (disable_mask & (1 << i)) {
581 + /* disable */
582 + rt305x_mii_write(esw, i, MII_BMCR,
583 + BMCR_PDOWN);
584 + } else {
585 + /* enable */
586 + rt305x_mii_write(esw, i, MII_BMCR,
587 + BMCR_FULLDPLX |
588 + BMCR_ANENABLE |
589 + BMCR_ANRESTART |
590 + BMCR_SPEED100);
591 + }
592 + }
593 +
594 + /* disable after writing to MII */
595 + esw_rmw(esw, RT305X_ESW_REG_POC0,
596 + (RT305X_ESW_POC0_DIS_PORT_M <<
597 + RT305X_ESW_POC0_DIS_PORT_S),
598 + disable_mask << RT305X_ESW_POC0_DIS_PORT_S);
599 +}
600 +
601 +static void esw_set_gsc(struct rt305x_esw *esw)
602 +{
603 + esw_rmw(esw, RT305X_ESW_REG_SGC,
604 + RT305X_ESW_GSC_BC_STROM_MASK << RT305X_ESW_GSC_BC_STROM_SHIFT,
605 + esw->bc_storm_protect << RT305X_ESW_GSC_BC_STROM_SHIFT);
606 + esw_rmw(esw, RT305X_ESW_REG_SGC,
607 + RT305X_ESW_GSC_LED_FREQ_MASK << RT305X_ESW_GSC_LED_FREQ_SHIFT,
608 + esw->led_frequency << RT305X_ESW_GSC_LED_FREQ_SHIFT);
609 +}
610 +
611 +static int esw_apply_config(struct switch_dev *dev);
612 +
613 +static void esw_hw_init(struct rt305x_esw *esw)
614 +{
615 + int i;
616 + u8 port_disable = 0;
617 + u8 port_map = RT305X_ESW_PMAP_LLLLLL;
618 +
619 + /* vodoo from original driver */
620 + esw_w32(esw, 0xC8A07850, RT305X_ESW_REG_FCT0);
621 + esw_w32(esw, 0x00000000, RT305X_ESW_REG_SGC2);
622 + /* Port priority 1 for all ports, vlan enabled. */
623 + esw_w32(esw, 0x00005555 |
624 + (RT305X_ESW_PORTS_ALL << RT305X_ESW_PFC1_EN_VLAN_S),
625 + RT305X_ESW_REG_PFC1);
626 +
627 + /* Enable Back Pressure, and Flow Control */
628 + esw_w32(esw,
629 + ((RT305X_ESW_PORTS_ALL << RT305X_ESW_POC0_EN_BP_S) |
630 + (RT305X_ESW_PORTS_ALL << RT305X_ESW_POC0_EN_FC_S)),
631 + RT305X_ESW_REG_POC0);
632 +
633 + /* Enable Aging, and VLAN TAG removal */
634 + esw_w32(esw,
635 + ((RT305X_ESW_PORTS_ALL << RT305X_ESW_POC2_ENAGING_S) |
636 + (RT305X_ESW_PORTS_NOCPU << RT305X_ESW_POC2_UNTAG_EN_S)),
637 + RT305X_ESW_REG_POC2);
638 +
639 + if (esw->reg_initval_fct2)
640 + esw_w32(esw, esw->reg_initval_fct2, RT305X_ESW_REG_FCT2);
641 + else
642 + esw_w32(esw, esw->pdata->reg_initval_fct2, RT305X_ESW_REG_FCT2);
643 +
644 + /*
645 + * 300s aging timer, max packet len 1536, broadcast storm prevention
646 + * disabled, disable collision abort, mac xor48 hash, 10 packet back
647 + * pressure jam, GMII disable was_transmit, back pressure disabled,
648 + * 30ms led flash, unmatched IGMP as broadcast, rmc tb fault to all
649 + * ports.
650 + */
651 + esw_w32(esw, 0x0008a301, RT305X_ESW_REG_SGC);
652 +
653 + /* Setup SoC Port control register */
654 + esw_w32(esw,
655 + (RT305X_ESW_SOCPC_CRC_PADDING |
656 + (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISUN2CPU_S) |
657 + (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISMC2CPU_S) |
658 + (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISBC2CPU_S)),
659 + RT305X_ESW_REG_SOCPC);
660 +
661 + if (esw->reg_initval_fpa2)
662 + esw_w32(esw, esw->reg_initval_fpa2, RT305X_ESW_REG_FPA2);
663 + else
664 + esw_w32(esw, esw->pdata->reg_initval_fpa2, RT305X_ESW_REG_FPA2);
665 + esw_w32(esw, 0x00000000, RT305X_ESW_REG_FPA);
666 +
667 + /* Force Link/Activity on ports */
668 + esw_w32(esw, 0x00000005, RT305X_ESW_REG_P0LED);
669 + esw_w32(esw, 0x00000005, RT305X_ESW_REG_P1LED);
670 + esw_w32(esw, 0x00000005, RT305X_ESW_REG_P2LED);
671 + esw_w32(esw, 0x00000005, RT305X_ESW_REG_P3LED);
672 + esw_w32(esw, 0x00000005, RT305X_ESW_REG_P4LED);
673 +
674 + /* Copy disabled port configuration from bootloader setup */
675 + port_disable = esw_get_port_disable(esw);
676 + for (i = 0; i < 6; i++)
677 + esw->ports[i].disable = (port_disable & (1 << i)) != 0;
678 +
679 + if (soc_is_rt3352()) {
680 + /* reset EPHY */
681 + u32 val = rt_sysc_r32(SYSC_REG_RESET_CTRL);
682 + rt_sysc_w32(val | RT5350_RESET_EPHY, SYSC_REG_RESET_CTRL);
683 + rt_sysc_w32(val, SYSC_REG_RESET_CTRL);
684 +
685 + rt305x_mii_write(esw, 0, 31, 0x8000);
686 + for (i = 0; i < 5; i++) {
687 + if (esw->ports[i].disable) {
688 + rt305x_mii_write(esw, i, MII_BMCR, BMCR_PDOWN);
689 + } else {
690 + rt305x_mii_write(esw, i, MII_BMCR,
691 + BMCR_FULLDPLX |
692 + BMCR_ANENABLE |
693 + BMCR_SPEED100);
694 + }
695 + /* TX10 waveform coefficient LSB=0 disable PHY */
696 + rt305x_mii_write(esw, i, 26, 0x1601);
697 + /* TX100/TX10 AD/DA current bias */
698 + rt305x_mii_write(esw, i, 29, 0x7016);
699 + /* TX100 slew rate control */
700 + rt305x_mii_write(esw, i, 30, 0x0038);
701 + }
702 +
703 + /* select global register */
704 + rt305x_mii_write(esw, 0, 31, 0x0);
705 + /* enlarge agcsel threshold 3 and threshold 2 */
706 + rt305x_mii_write(esw, 0, 1, 0x4a40);
707 + /* enlarge agcsel threshold 5 and threshold 4 */
708 + rt305x_mii_write(esw, 0, 2, 0x6254);
709 + /* enlarge agcsel threshold */
710 + rt305x_mii_write(esw, 0, 3, 0xa17f);
711 + rt305x_mii_write(esw, 0,12, 0x7eaa);
712 + /* longer TP_IDL tail length */
713 + rt305x_mii_write(esw, 0, 14, 0x65);
714 + /* increased squelch pulse count threshold. */
715 + rt305x_mii_write(esw, 0, 16, 0x0684);
716 + /* set TX10 signal amplitude threshold to minimum */
717 + rt305x_mii_write(esw, 0, 17, 0x0fe0);
718 + /* set squelch amplitude to higher threshold */
719 + rt305x_mii_write(esw, 0, 18, 0x40ba);
720 + /* tune TP_IDL tail and head waveform, enable power down slew rate control */
721 + rt305x_mii_write(esw, 0, 22, 0x253f);
722 + /* set PLL/Receive bias current are calibrated */
723 + rt305x_mii_write(esw, 0, 27, 0x2fda);
724 + /* change PLL/Receive bias current to internal(RT3350) */
725 + rt305x_mii_write(esw, 0, 28, 0xc410);
726 + /* change PLL bias current to internal(RT3052_MP3) */
727 + rt305x_mii_write(esw, 0, 29, 0x598b);
728 + /* select local register */
729 + rt305x_mii_write(esw, 0, 31, 0x8000);
730 + } else if (soc_is_rt5350()) {
731 + /* reset EPHY */
732 + u32 val = rt_sysc_r32(SYSC_REG_RESET_CTRL);
733 + rt_sysc_w32(val | RT5350_RESET_EPHY, SYSC_REG_RESET_CTRL);
734 + rt_sysc_w32(val, SYSC_REG_RESET_CTRL);
735 +
736 + /* set the led polarity */
737 + esw_w32(esw, esw->reg_led_polarity & 0x1F, RT5350_EWS_REG_LED_POLARITY);
738 +
739 + /* local registers */
740 + rt305x_mii_write(esw, 0, 31, 0x8000);
741 + for (i = 0; i < 5; i++) {
742 + if (esw->ports[i].disable) {
743 + rt305x_mii_write(esw, i, MII_BMCR, BMCR_PDOWN);
744 + } else {
745 + rt305x_mii_write(esw, i, MII_BMCR,
746 + BMCR_FULLDPLX |
747 + BMCR_ANENABLE |
748 + BMCR_SPEED100);
749 + }
750 + /* TX10 waveform coefficient LSB=0 disable PHY */
751 + rt305x_mii_write(esw, i, 26, 0x1601);
752 + /* TX100/TX10 AD/DA current bias */
753 + rt305x_mii_write(esw, i, 29, 0x7015);
754 + /* TX100 slew rate control */
755 + rt305x_mii_write(esw, i, 30, 0x0038);
756 + }
757 +
758 + /* global registers */
759 + rt305x_mii_write(esw, 0, 31, 0x0);
760 + /* enlarge agcsel threshold 3 and threshold 2 */
761 + rt305x_mii_write(esw, 0, 1, 0x4a40);
762 + /* enlarge agcsel threshold 5 and threshold 4 */
763 + rt305x_mii_write(esw, 0, 2, 0x6254);
764 + /* enlarge agcsel threshold 6 */
765 + rt305x_mii_write(esw, 0, 3, 0xa17f);
766 + rt305x_mii_write(esw, 0, 12, 0x7eaa);
767 + /* longer TP_IDL tail length */
768 + rt305x_mii_write(esw, 0, 14, 0x65);
769 + /* increased squelch pulse count threshold. */
770 + rt305x_mii_write(esw, 0, 16, 0x0684);
771 + /* set TX10 signal amplitude threshold to minimum */
772 + rt305x_mii_write(esw, 0, 17, 0x0fe0);
773 + /* set squelch amplitude to higher threshold */
774 + rt305x_mii_write(esw, 0, 18, 0x40ba);
775 + /* tune TP_IDL tail and head waveform, enable power down slew rate control */
776 + rt305x_mii_write(esw, 0, 22, 0x253f);
777 + /* set PLL/Receive bias current are calibrated */
778 + rt305x_mii_write(esw, 0, 27, 0x2fda);
779 + /* change PLL/Receive bias current to internal(RT3350) */
780 + rt305x_mii_write(esw, 0, 28, 0xc410);
781 + /* change PLL bias current to internal(RT3052_MP3) */
782 + rt305x_mii_write(esw, 0, 29, 0x598b);
783 + /* select local register */
784 + rt305x_mii_write(esw, 0, 31, 0x8000);
785 + } else {
786 + rt305x_mii_write(esw, 0, 31, 0x8000);
787 + for (i = 0; i < 5; i++) {
788 + if (esw->ports[i].disable) {
789 + rt305x_mii_write(esw, i, MII_BMCR, BMCR_PDOWN);
790 + } else {
791 + rt305x_mii_write(esw, i, MII_BMCR,
792 + BMCR_FULLDPLX |
793 + BMCR_ANENABLE |
794 + BMCR_SPEED100);
795 + }
796 + /* TX10 waveform coefficient */
797 + rt305x_mii_write(esw, i, 26, 0x1601);
798 + /* TX100/TX10 AD/DA current bias */
799 + rt305x_mii_write(esw, i, 29, 0x7058);
800 + /* TX100 slew rate control */
801 + rt305x_mii_write(esw, i, 30, 0x0018);
802 + }
803 +
804 + /* PHY IOT */
805 + /* select global register */
806 + rt305x_mii_write(esw, 0, 31, 0x0);
807 + /* tune TP_IDL tail and head waveform */
808 + rt305x_mii_write(esw, 0, 22, 0x052f);
809 + /* set TX10 signal amplitude threshold to minimum */
810 + rt305x_mii_write(esw, 0, 17, 0x0fe0);
811 + /* set squelch amplitude to higher threshold */
812 + rt305x_mii_write(esw, 0, 18, 0x40ba);
813 + /* longer TP_IDL tail length */
814 + rt305x_mii_write(esw, 0, 14, 0x65);
815 + /* select local register */
816 + rt305x_mii_write(esw, 0, 31, 0x8000);
817 + }
818 +
819 + if (esw->port_map)
820 + port_map = esw->port_map;
821 + else
822 + port_map = RT305X_ESW_PMAP_LLLLLL;
823 +
824 + /*
825 + * Unused HW feature, but still nice to be consistent here...
826 + * This is also exported to userspace ('lan' attribute) so it's
827 + * conveniently usable to decide which ports go into the wan vlan by
828 + * default.
829 + */
830 + esw_rmw(esw, RT305X_ESW_REG_SGC2,
831 + RT305X_ESW_SGC2_LAN_PMAP_M << RT305X_ESW_SGC2_LAN_PMAP_S,
832 + port_map << RT305X_ESW_SGC2_LAN_PMAP_S);
833 +
834 + /* make the switch leds blink */
835 + for (i = 0; i < RT305X_ESW_NUM_LEDS; i++)
836 + esw->ports[i].led = 0x05;
837 +
838 + /* Apply the empty config. */
839 + esw_apply_config(&esw->swdev);
840 +
841 + /* Only unmask the port change interrupt */
842 + esw_w32(esw, ~RT305X_ESW_PORT_ST_CHG, RT305X_ESW_REG_IMR);
843 +}
844 +
845 +static irqreturn_t esw_interrupt(int irq, void *_esw)
846 +{
847 + struct rt305x_esw *esw = (struct rt305x_esw *) _esw;
848 + u32 status;
849 +
850 + status = esw_r32(esw, RT305X_ESW_REG_ISR);
851 + if (status & RT305X_ESW_PORT_ST_CHG) {
852 + u32 link = esw_r32(esw, RT305X_ESW_REG_POA);
853 + link >>= RT305X_ESW_POA_LINK_SHIFT;
854 + link &= RT305X_ESW_POA_LINK_MASK;
855 + dev_info(esw->dev, "link changed 0x%02X\n", link);
856 + }
857 + esw_w32(esw, status, RT305X_ESW_REG_ISR);
858 +
859 + return IRQ_HANDLED;
860 +}
861 +
862 +static int esw_apply_config(struct switch_dev *dev)
863 +{
864 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
865 + int i;
866 + u8 disable = 0;
867 + u8 doubletag = 0;
868 + u8 en_vlan = 0;
869 + u8 untag = 0;
870 +
871 + for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {
872 + u32 vid, vmsc;
873 + if (esw->global_vlan_enable) {
874 + vid = esw->vlans[i].vid;
875 + vmsc = esw->vlans[i].ports;
876 + } else {
877 + vid = RT305X_ESW_VLAN_NONE;
878 + vmsc = RT305X_ESW_PORTS_NONE;
879 + }
880 + esw_set_vlan_id(esw, i, vid);
881 + esw_set_vmsc(esw, i, vmsc);
882 + }
883 +
884 + for (i = 0; i < RT305X_ESW_NUM_PORTS; i++) {
885 + u32 pvid;
886 + disable |= esw->ports[i].disable << i;
887 + if (esw->global_vlan_enable) {
888 + doubletag |= esw->ports[i].doubletag << i;
889 + en_vlan |= 1 << i;
890 + untag |= esw->ports[i].untag << i;
891 + pvid = esw->ports[i].pvid;
892 + } else {
893 + int x = esw->alt_vlan_disable ? 0 : 1;
894 + doubletag |= x << i;
895 + en_vlan |= x << i;
896 + untag |= x << i;
897 + pvid = 0;
898 + }
899 + esw_set_pvid(esw, i, pvid);
900 + if (i < RT305X_ESW_NUM_LEDS)
901 + esw_w32(esw, esw->ports[i].led,
902 + RT305X_ESW_REG_P0LED + 4*i);
903 + }
904 +
905 + esw_set_gsc(esw);
906 + esw_set_port_disable(esw, disable);
907 + esw_rmw(esw, RT305X_ESW_REG_SGC2,
908 + (RT305X_ESW_SGC2_DOUBLE_TAG_M <<
909 + RT305X_ESW_SGC2_DOUBLE_TAG_S),
910 + doubletag << RT305X_ESW_SGC2_DOUBLE_TAG_S);
911 + esw_rmw(esw, RT305X_ESW_REG_PFC1,
912 + RT305X_ESW_PFC1_EN_VLAN_M << RT305X_ESW_PFC1_EN_VLAN_S,
913 + en_vlan << RT305X_ESW_PFC1_EN_VLAN_S);
914 + esw_rmw(esw, RT305X_ESW_REG_POC2,
915 + RT305X_ESW_POC2_UNTAG_EN_M << RT305X_ESW_POC2_UNTAG_EN_S,
916 + untag << RT305X_ESW_POC2_UNTAG_EN_S);
917 +
918 + if (!esw->global_vlan_enable) {
919 + /*
920 + * Still need to put all ports into vlan 0 or they'll be
921 + * isolated.
922 + * NOTE: vlan 0 is special, no vlan tag is prepended
923 + */
924 + esw_set_vlan_id(esw, 0, 0);
925 + esw_set_vmsc(esw, 0, RT305X_ESW_PORTS_ALL);
926 + }
927 +
928 + return 0;
929 +}
930 +
931 +static int esw_reset_switch(struct switch_dev *dev)
932 +{
933 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
934 +
935 + esw->global_vlan_enable = 0;
936 + memset(esw->ports, 0, sizeof(esw->ports));
937 + memset(esw->vlans, 0, sizeof(esw->vlans));
938 + esw_hw_init(esw);
939 +
940 + return 0;
941 +}
942 +
943 +static int esw_get_vlan_enable(struct switch_dev *dev,
944 + const struct switch_attr *attr,
945 + struct switch_val *val)
946 +{
947 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
948 +
949 + val->value.i = esw->global_vlan_enable;
950 +
951 + return 0;
952 +}
953 +
954 +static int esw_set_vlan_enable(struct switch_dev *dev,
955 + const struct switch_attr *attr,
956 + struct switch_val *val)
957 +{
958 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
959 +
960 + esw->global_vlan_enable = val->value.i != 0;
961 +
962 + return 0;
963 +}
964 +
965 +static int esw_get_alt_vlan_disable(struct switch_dev *dev,
966 + const struct switch_attr *attr,
967 + struct switch_val *val)
968 +{
969 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
970 +
971 + val->value.i = esw->alt_vlan_disable;
972 +
973 + return 0;
974 +}
975 +
976 +static int esw_set_alt_vlan_disable(struct switch_dev *dev,
977 + const struct switch_attr *attr,
978 + struct switch_val *val)
979 +{
980 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
981 +
982 + esw->alt_vlan_disable = val->value.i != 0;
983 +
984 + return 0;
985 +}
986 +
987 +static int
988 +rt305x_esw_set_bc_status(struct switch_dev *dev,
989 + const struct switch_attr *attr,
990 + struct switch_val *val)
991 +{
992 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
993 +
994 + esw->bc_storm_protect = val->value.i & RT305X_ESW_GSC_BC_STROM_MASK;
995 +
996 + return 0;
997 +}
998 +
999 +static int
1000 +rt305x_esw_get_bc_status(struct switch_dev *dev,
1001 + const struct switch_attr *attr,
1002 + struct switch_val *val)
1003 +{
1004 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1005 +
1006 + val->value.i = esw->bc_storm_protect;
1007 +
1008 + return 0;
1009 +}
1010 +
1011 +static int
1012 +rt305x_esw_set_led_freq(struct switch_dev *dev,
1013 + const struct switch_attr *attr,
1014 + struct switch_val *val)
1015 +{
1016 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1017 +
1018 + esw->led_frequency = val->value.i & RT305X_ESW_GSC_LED_FREQ_MASK;
1019 +
1020 + return 0;
1021 +}
1022 +
1023 +static int
1024 +rt305x_esw_get_led_freq(struct switch_dev *dev,
1025 + const struct switch_attr *attr,
1026 + struct switch_val *val)
1027 +{
1028 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1029 +
1030 + val->value.i = esw->led_frequency;
1031 +
1032 + return 0;
1033 +}
1034 +
1035 +static int esw_get_port_link(struct switch_dev *dev,
1036 + int port,
1037 + struct switch_port_link *link)
1038 +{
1039 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1040 + u32 speed, poa;
1041 +
1042 + if (port < 0 || port >= RT305X_ESW_NUM_PORTS)
1043 + return -EINVAL;
1044 +
1045 + poa = esw_r32(esw, RT305X_ESW_REG_POA) >> port;
1046 +
1047 + link->link = (poa >> RT305X_ESW_LINK_S) & 1;
1048 + link->duplex = (poa >> RT305X_ESW_DUPLEX_S) & 1;
1049 + if (port < RT305X_ESW_NUM_LEDS) {
1050 + speed = (poa >> RT305X_ESW_SPD_S) & 1;
1051 + } else {
1052 + if (port == RT305X_ESW_NUM_PORTS - 1)
1053 + poa >>= 1;
1054 + speed = (poa >> RT305X_ESW_SPD_S) & 3;
1055 + }
1056 + switch (speed) {
1057 + case 0:
1058 + link->speed = SWITCH_PORT_SPEED_10;
1059 + break;
1060 + case 1:
1061 + link->speed = SWITCH_PORT_SPEED_100;
1062 + break;
1063 + case 2:
1064 + case 3: /* forced gige speed can be 2 or 3 */
1065 + link->speed = SWITCH_PORT_SPEED_1000;
1066 + break;
1067 + default:
1068 + link->speed = SWITCH_PORT_SPEED_UNKNOWN;
1069 + break;
1070 + }
1071 +
1072 + return 0;
1073 +}
1074 +
1075 +static int esw_get_port_bool(struct switch_dev *dev,
1076 + const struct switch_attr *attr,
1077 + struct switch_val *val)
1078 +{
1079 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1080 + int idx = val->port_vlan;
1081 + u32 x, reg, shift;
1082 +
1083 + if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS)
1084 + return -EINVAL;
1085 +
1086 + switch (attr->id) {
1087 + case RT305X_ESW_ATTR_PORT_DISABLE:
1088 + reg = RT305X_ESW_REG_POC0;
1089 + shift = RT305X_ESW_POC0_DIS_PORT_S;
1090 + break;
1091 + case RT305X_ESW_ATTR_PORT_DOUBLETAG:
1092 + reg = RT305X_ESW_REG_SGC2;
1093 + shift = RT305X_ESW_SGC2_DOUBLE_TAG_S;
1094 + break;
1095 + case RT305X_ESW_ATTR_PORT_UNTAG:
1096 + reg = RT305X_ESW_REG_POC2;
1097 + shift = RT305X_ESW_POC2_UNTAG_EN_S;
1098 + break;
1099 + case RT305X_ESW_ATTR_PORT_LAN:
1100 + reg = RT305X_ESW_REG_SGC2;
1101 + shift = RT305X_ESW_SGC2_LAN_PMAP_S;
1102 + if (idx >= RT305X_ESW_NUM_LANWAN)
1103 + return -EINVAL;
1104 + break;
1105 + default:
1106 + return -EINVAL;
1107 + }
1108 +
1109 + x = esw_r32(esw, reg);
1110 + val->value.i = (x >> (idx + shift)) & 1;
1111 +
1112 + return 0;
1113 +}
1114 +
1115 +static int esw_set_port_bool(struct switch_dev *dev,
1116 + const struct switch_attr *attr,
1117 + struct switch_val *val)
1118 +{
1119 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1120 + int idx = val->port_vlan;
1121 +
1122 + if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS ||
1123 + val->value.i < 0 || val->value.i > 1)
1124 + return -EINVAL;
1125 +
1126 + switch (attr->id) {
1127 + case RT305X_ESW_ATTR_PORT_DISABLE:
1128 + esw->ports[idx].disable = val->value.i;
1129 + break;
1130 + case RT305X_ESW_ATTR_PORT_DOUBLETAG:
1131 + esw->ports[idx].doubletag = val->value.i;
1132 + break;
1133 + case RT305X_ESW_ATTR_PORT_UNTAG:
1134 + esw->ports[idx].untag = val->value.i;
1135 + break;
1136 + default:
1137 + return -EINVAL;
1138 + }
1139 +
1140 + return 0;
1141 +}
1142 +
1143 +static int esw_get_port_recv_badgood(struct switch_dev *dev,
1144 + const struct switch_attr *attr,
1145 + struct switch_val *val)
1146 +{
1147 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1148 + int idx = val->port_vlan;
1149 + int shift = attr->id == RT305X_ESW_ATTR_PORT_RECV_GOOD ? 0 : 16;
1150 + u32 reg;
1151 +
1152 + if (idx < 0 || idx >= RT305X_ESW_NUM_LANWAN)
1153 + return -EINVAL;
1154 + reg = esw_r32(esw, RT305X_ESW_REG_PXPC(idx));
1155 + val->value.i = (reg >> shift) & 0xffff;
1156 +
1157 + return 0;
1158 +}
1159 +
1160 +static int
1161 +esw_get_port_tr_badgood(struct switch_dev *dev,
1162 + const struct switch_attr *attr,
1163 + struct switch_val *val)
1164 +{
1165 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1166 +
1167 + int idx = val->port_vlan;
1168 + int shift = attr->id == RT5350_ESW_ATTR_PORT_TR_GOOD ? 0 : 16;
1169 + u32 reg;
1170 +
1171 + if (!soc_is_rt5350())
1172 + return -EINVAL;
1173 +
1174 + if (idx < 0 || idx >= RT305X_ESW_NUM_LANWAN)
1175 + return -EINVAL;
1176 +
1177 + reg = esw_r32(esw, RT5350_ESW_REG_PXTPC(idx));
1178 + val->value.i = (reg >> shift) & 0xffff;
1179 +
1180 + return 0;
1181 +}
1182 +
1183 +static int esw_get_port_led(struct switch_dev *dev,
1184 + const struct switch_attr *attr,
1185 + struct switch_val *val)
1186 +{
1187 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1188 + int idx = val->port_vlan;
1189 +
1190 + if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS ||
1191 + idx >= RT305X_ESW_NUM_LEDS)
1192 + return -EINVAL;
1193 +
1194 + val->value.i = esw_r32(esw, RT305X_ESW_REG_P0LED + 4*idx);
1195 +
1196 + return 0;
1197 +}
1198 +
1199 +static int esw_set_port_led(struct switch_dev *dev,
1200 + const struct switch_attr *attr,
1201 + struct switch_val *val)
1202 +{
1203 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1204 + int idx = val->port_vlan;
1205 +
1206 + if (idx < 0 || idx >= RT305X_ESW_NUM_LEDS)
1207 + return -EINVAL;
1208 +
1209 + esw->ports[idx].led = val->value.i;
1210 +
1211 + return 0;
1212 +}
1213 +
1214 +static int esw_get_port_pvid(struct switch_dev *dev, int port, int *val)
1215 +{
1216 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1217 +
1218 + if (port >= RT305X_ESW_NUM_PORTS)
1219 + return -EINVAL;
1220 +
1221 + *val = esw_get_pvid(esw, port);
1222 +
1223 + return 0;
1224 +}
1225 +
1226 +static int esw_set_port_pvid(struct switch_dev *dev, int port, int val)
1227 +{
1228 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1229 +
1230 + if (port >= RT305X_ESW_NUM_PORTS)
1231 + return -EINVAL;
1232 +
1233 + esw->ports[port].pvid = val;
1234 +
1235 + return 0;
1236 +}
1237 +
1238 +static int esw_get_vlan_ports(struct switch_dev *dev, struct switch_val *val)
1239 +{
1240 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1241 + u32 vmsc, poc2;
1242 + int vlan_idx = -1;
1243 + int i;
1244 +
1245 + val->len = 0;
1246 +
1247 + if (val->port_vlan < 0 || val->port_vlan >= RT305X_ESW_NUM_VIDS)
1248 + return -EINVAL;
1249 +
1250 + /* valid vlan? */
1251 + for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {
1252 + if (esw_get_vlan_id(esw, i) == val->port_vlan &&
1253 + esw_get_vmsc(esw, i) != RT305X_ESW_PORTS_NONE) {
1254 + vlan_idx = i;
1255 + break;
1256 + }
1257 + }
1258 +
1259 + if (vlan_idx == -1)
1260 + return -EINVAL;
1261 +
1262 + vmsc = esw_get_vmsc(esw, vlan_idx);
1263 + poc2 = esw_r32(esw, RT305X_ESW_REG_POC2);
1264 +
1265 + for (i = 0; i < RT305X_ESW_NUM_PORTS; i++) {
1266 + struct switch_port *p;
1267 + int port_mask = 1 << i;
1268 +
1269 + if (!(vmsc & port_mask))
1270 + continue;
1271 +
1272 + p = &val->value.ports[val->len++];
1273 + p->id = i;
1274 + if (poc2 & (port_mask << RT305X_ESW_POC2_UNTAG_EN_S))
1275 + p->flags = 0;
1276 + else
1277 + p->flags = 1 << SWITCH_PORT_FLAG_TAGGED;
1278 + }
1279 +
1280 + return 0;
1281 +}
1282 +
1283 +static int esw_set_vlan_ports(struct switch_dev *dev, struct switch_val *val)
1284 +{
1285 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1286 + int ports;
1287 + int vlan_idx = -1;
1288 + int i;
1289 +
1290 + if (val->port_vlan < 0 || val->port_vlan >= RT305X_ESW_NUM_VIDS ||
1291 + val->len > RT305X_ESW_NUM_PORTS)
1292 + return -EINVAL;
1293 +
1294 + /* one of the already defined vlans? */
1295 + for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {
1296 + if (esw->vlans[i].vid == val->port_vlan &&
1297 + esw->vlans[i].ports != RT305X_ESW_PORTS_NONE) {
1298 + vlan_idx = i;
1299 + break;
1300 + }
1301 + }
1302 +
1303 + /* select a free slot */
1304 + for (i = 0; vlan_idx == -1 && i < RT305X_ESW_NUM_VLANS; i++) {
1305 + if (esw->vlans[i].ports == RT305X_ESW_PORTS_NONE)
1306 + vlan_idx = i;
1307 + }
1308 +
1309 + /* bail if all slots are in use */
1310 + if (vlan_idx == -1)
1311 + return -EINVAL;
1312 +
1313 + ports = RT305X_ESW_PORTS_NONE;
1314 + for (i = 0; i < val->len; i++) {
1315 + struct switch_port *p = &val->value.ports[i];
1316 + int port_mask = 1 << p->id;
1317 + bool untagged = !(p->flags & (1 << SWITCH_PORT_FLAG_TAGGED));
1318 +
1319 + if (p->id >= RT305X_ESW_NUM_PORTS)
1320 + return -EINVAL;
1321 +
1322 + ports |= port_mask;
1323 + esw->ports[p->id].untag = untagged;
1324 + }
1325 + esw->vlans[vlan_idx].ports = ports;
1326 + if (ports == RT305X_ESW_PORTS_NONE)
1327 + esw->vlans[vlan_idx].vid = RT305X_ESW_VLAN_NONE;
1328 + else
1329 + esw->vlans[vlan_idx].vid = val->port_vlan;
1330 +
1331 + return 0;
1332 +}
1333 +
1334 +static const struct switch_attr esw_global[] = {
1335 + {
1336 + .type = SWITCH_TYPE_INT,
1337 + .name = "enable_vlan",
1338 + .description = "VLAN mode (1:enabled)",
1339 + .max = 1,
1340 + .id = RT305X_ESW_ATTR_ENABLE_VLAN,
1341 + .get = esw_get_vlan_enable,
1342 + .set = esw_set_vlan_enable,
1343 + },
1344 + {
1345 + .type = SWITCH_TYPE_INT,
1346 + .name = "alternate_vlan_disable",
1347 + .description = "Use en_vlan instead of doubletag to disable"
1348 + " VLAN mode",
1349 + .max = 1,
1350 + .id = RT305X_ESW_ATTR_ALT_VLAN_DISABLE,
1351 + .get = esw_get_alt_vlan_disable,
1352 + .set = esw_set_alt_vlan_disable,
1353 + },
1354 + {
1355 + .type = SWITCH_TYPE_INT,
1356 + .name = "bc_storm_protect",
1357 + .description = "Global broadcast storm protection (0:Disable, 1:64 blocks, 2:96 blocks, 3:128 blocks)",
1358 + .max = 3,
1359 + .id = RT305X_ESW_ATTR_BC_STATUS,
1360 + .get = rt305x_esw_get_bc_status,
1361 + .set = rt305x_esw_set_bc_status,
1362 + },
1363 + {
1364 + .type = SWITCH_TYPE_INT,
1365 + .name = "led_frequency",
1366 + .description = "LED Flash frequency (0:30mS, 1:60mS, 2:240mS, 3:480mS)",
1367 + .max = 3,
1368 + .id = RT305X_ESW_ATTR_LED_FREQ,
1369 + .get = rt305x_esw_get_led_freq,
1370 + .set = rt305x_esw_set_led_freq,
1371 + }
1372 +};
1373 +
1374 +static const struct switch_attr esw_port[] = {
1375 + {
1376 + .type = SWITCH_TYPE_INT,
1377 + .name = "disable",
1378 + .description = "Port state (1:disabled)",
1379 + .max = 1,
1380 + .id = RT305X_ESW_ATTR_PORT_DISABLE,
1381 + .get = esw_get_port_bool,
1382 + .set = esw_set_port_bool,
1383 + },
1384 + {
1385 + .type = SWITCH_TYPE_INT,
1386 + .name = "doubletag",
1387 + .description = "Double tagging for incoming vlan packets "
1388 + "(1:enabled)",
1389 + .max = 1,
1390 + .id = RT305X_ESW_ATTR_PORT_DOUBLETAG,
1391 + .get = esw_get_port_bool,
1392 + .set = esw_set_port_bool,
1393 + },
1394 + {
1395 + .type = SWITCH_TYPE_INT,
1396 + .name = "untag",
1397 + .description = "Untag (1:strip outgoing vlan tag)",
1398 + .max = 1,
1399 + .id = RT305X_ESW_ATTR_PORT_UNTAG,
1400 + .get = esw_get_port_bool,
1401 + .set = esw_set_port_bool,
1402 + },
1403 + {
1404 + .type = SWITCH_TYPE_INT,
1405 + .name = "led",
1406 + .description = "LED mode (0:link, 1:100m, 2:duplex, 3:activity,"
1407 + " 4:collision, 5:linkact, 6:duplcoll, 7:10mact,"
1408 + " 8:100mact, 10:blink, 11:off, 12:on)",
1409 + .max = 15,
1410 + .id = RT305X_ESW_ATTR_PORT_LED,
1411 + .get = esw_get_port_led,
1412 + .set = esw_set_port_led,
1413 + },
1414 + {
1415 + .type = SWITCH_TYPE_INT,
1416 + .name = "lan",
1417 + .description = "HW port group (0:wan, 1:lan)",
1418 + .max = 1,
1419 + .id = RT305X_ESW_ATTR_PORT_LAN,
1420 + .get = esw_get_port_bool,
1421 + },
1422 + {
1423 + .type = SWITCH_TYPE_INT,
1424 + .name = "recv_bad",
1425 + .description = "Receive bad packet counter",
1426 + .id = RT305X_ESW_ATTR_PORT_RECV_BAD,
1427 + .get = esw_get_port_recv_badgood,
1428 + },
1429 + {
1430 + .type = SWITCH_TYPE_INT,
1431 + .name = "recv_good",
1432 + .description = "Receive good packet counter",
1433 + .id = RT305X_ESW_ATTR_PORT_RECV_GOOD,
1434 + .get = esw_get_port_recv_badgood,
1435 + },
1436 + {
1437 + .type = SWITCH_TYPE_INT,
1438 + .name = "tr_bad",
1439 +
1440 + .description = "Transmit bad packet counter. rt5350 only",
1441 + .id = RT5350_ESW_ATTR_PORT_TR_BAD,
1442 + .get = esw_get_port_tr_badgood,
1443 + },
1444 + {
1445 + .type = SWITCH_TYPE_INT,
1446 + .name = "tr_good",
1447 +
1448 + .description = "Transmit good packet counter. rt5350 only",
1449 + .id = RT5350_ESW_ATTR_PORT_TR_GOOD,
1450 + .get = esw_get_port_tr_badgood,
1451 + },
1452 +};
1453 +
1454 +static const struct switch_attr esw_vlan[] = {
1455 +};
1456 +
1457 +static const struct switch_dev_ops esw_ops = {
1458 + .attr_global = {
1459 + .attr = esw_global,
1460 + .n_attr = ARRAY_SIZE(esw_global),
1461 + },
1462 + .attr_port = {
1463 + .attr = esw_port,
1464 + .n_attr = ARRAY_SIZE(esw_port),
1465 + },
1466 + .attr_vlan = {
1467 + .attr = esw_vlan,
1468 + .n_attr = ARRAY_SIZE(esw_vlan),
1469 + },
1470 + .get_vlan_ports = esw_get_vlan_ports,
1471 + .set_vlan_ports = esw_set_vlan_ports,
1472 + .get_port_pvid = esw_get_port_pvid,
1473 + .set_port_pvid = esw_set_port_pvid,
1474 + .get_port_link = esw_get_port_link,
1475 + .apply_config = esw_apply_config,
1476 + .reset_switch = esw_reset_switch,
1477 +};
1478 +
1479 +static struct rt305x_esw_platform_data rt3050_esw_data = {
1480 + /* All ports are LAN ports. */
1481 + .vlan_config = RT305X_ESW_VLAN_CONFIG_NONE,
1482 + .reg_initval_fct2 = 0x00d6500c,
1483 + /*
1484 + * ext phy base addr 31, enable port 5 polling, rx/tx clock skew 1,
1485 + * turbo mii off, rgmi 3.3v off
1486 + * port5: disabled
1487 + * port6: enabled, gige, full-duplex, rx/tx-flow-control
1488 + */
1489 + .reg_initval_fpa2 = 0x3f502b28,
1490 +};
1491 +
1492 +static const struct of_device_id ralink_esw_match[] = {
1493 + { .compatible = "ralink,rt3050-esw", .data = &rt3050_esw_data },
1494 + {},
1495 +};
1496 +MODULE_DEVICE_TABLE(of, ralink_esw_match);
1497 +
1498 +static int esw_probe(struct platform_device *pdev)
1499 +{
1500 + struct device_node *np = pdev->dev.of_node;
1501 + const struct rt305x_esw_platform_data *pdata;
1502 + const __be32 *port_map, *reg_init;
1503 + struct rt305x_esw *esw;
1504 + struct switch_dev *swdev;
1505 + struct resource *res, *irq;
1506 + int err;
1507 +
1508 + pdata = pdev->dev.platform_data;
1509 + if (!pdata) {
1510 + const struct of_device_id *match;
1511 + match = of_match_device(ralink_esw_match, &pdev->dev);
1512 + if (match)
1513 + pdata = (struct rt305x_esw_platform_data *) match->data;
1514 + }
1515 + if (!pdata)
1516 + return -EINVAL;
1517 +
1518 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1519 + if (!res) {
1520 + dev_err(&pdev->dev, "no memory resource found\n");
1521 + return -ENOMEM;
1522 + }
1523 +
1524 + irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1525 + if (!irq) {
1526 + dev_err(&pdev->dev, "no irq resource found\n");
1527 + return -ENOMEM;
1528 + }
1529 +
1530 + esw = kzalloc(sizeof(struct rt305x_esw), GFP_KERNEL);
1531 + if (!esw) {
1532 + dev_err(&pdev->dev, "no memory for private data\n");
1533 + return -ENOMEM;
1534 + }
1535 +
1536 + esw->dev = &pdev->dev;
1537 + esw->irq = irq->start;
1538 + esw->base = ioremap(res->start, resource_size(res));
1539 + if (!esw->base) {
1540 + dev_err(&pdev->dev, "ioremap failed\n");
1541 + err = -ENOMEM;
1542 + goto free_esw;
1543 + }
1544 +
1545 + port_map = of_get_property(np, "ralink,portmap", NULL);
1546 + if (port_map)
1547 + esw->port_map = be32_to_cpu(*port_map);
1548 +
1549 + reg_init = of_get_property(np, "ralink,fct2", NULL);
1550 + if (reg_init)
1551 + esw->reg_initval_fct2 = be32_to_cpu(*reg_init);
1552 +
1553 + reg_init = of_get_property(np, "ralink,fpa2", NULL);
1554 + if (reg_init)
1555 + esw->reg_initval_fpa2 = be32_to_cpu(*reg_init);
1556 +
1557 + reg_init = of_get_property(np, "ralink,led_polarity", NULL);
1558 + if (reg_init)
1559 + esw->reg_led_polarity = be32_to_cpu(*reg_init);
1560 +
1561 + swdev = &esw->swdev;
1562 + swdev->of_node = pdev->dev.of_node;
1563 + swdev->name = "rt305x-esw";
1564 + swdev->alias = "rt305x";
1565 + swdev->cpu_port = RT305X_ESW_PORT6;
1566 + swdev->ports = RT305X_ESW_NUM_PORTS;
1567 + swdev->vlans = RT305X_ESW_NUM_VIDS;
1568 + swdev->ops = &esw_ops;
1569 +
1570 + err = register_switch(swdev, NULL);
1571 + if (err < 0) {
1572 + dev_err(&pdev->dev, "register_switch failed\n");
1573 + goto unmap_base;
1574 + }
1575 +
1576 + platform_set_drvdata(pdev, esw);
1577 +
1578 + esw->pdata = pdata;
1579 + spin_lock_init(&esw->reg_rw_lock);
1580 +
1581 + esw_hw_init(esw);
1582 +
1583 + esw_w32(esw, RT305X_ESW_PORT_ST_CHG, RT305X_ESW_REG_ISR);
1584 + esw_w32(esw, ~RT305X_ESW_PORT_ST_CHG, RT305X_ESW_REG_IMR);
1585 + request_irq(esw->irq, esw_interrupt, 0, "esw", esw);
1586 +
1587 + return 0;
1588 +
1589 +unmap_base:
1590 + iounmap(esw->base);
1591 +free_esw:
1592 + kfree(esw);
1593 + return err;
1594 +}
1595 +
1596 +static int esw_remove(struct platform_device *pdev)
1597 +{
1598 + struct rt305x_esw *esw;
1599 +
1600 + esw = platform_get_drvdata(pdev);
1601 + if (esw) {
1602 + unregister_switch(&esw->swdev);
1603 + platform_set_drvdata(pdev, NULL);
1604 + iounmap(esw->base);
1605 + kfree(esw);
1606 + }
1607 +
1608 + return 0;
1609 +}
1610 +
1611 +static struct platform_driver esw_driver = {
1612 + .probe = esw_probe,
1613 + .remove = esw_remove,
1614 + .driver = {
1615 + .name = "rt305x-esw",
1616 + .owner = THIS_MODULE,
1617 + .of_match_table = ralink_esw_match,
1618 + },
1619 +};
1620 +
1621 +int __init rtesw_init(void)
1622 +{
1623 + return platform_driver_register(&esw_driver);
1624 +}
1625 +
1626 +void rtesw_exit(void)
1627 +{
1628 + platform_driver_unregister(&esw_driver);
1629 +}
1630 --- /dev/null
1631 +++ b/drivers/net/ethernet/ralink/esw_rt3052.h
1632 @@ -0,0 +1,32 @@
1633 +/*
1634 + * This program is free software; you can redistribute it and/or modify
1635 + * it under the terms of the GNU General Public License as published by
1636 + * the Free Software Foundation; version 2 of the License
1637 + *
1638 + * This program is distributed in the hope that it will be useful,
1639 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1640 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1641 + * GNU General Public License for more details.
1642 + *
1643 + * You should have received a copy of the GNU General Public License
1644 + * along with this program; if not, write to the Free Software
1645 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
1646 + *
1647 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
1648 + */
1649 +
1650 +#ifndef _RALINK_ESW_RT3052_H__
1651 +#define _RALINK_ESW_RT3052_H__
1652 +
1653 +#ifdef CONFIG_NET_RALINK_ESW_RT3052
1654 +
1655 +int __init rtesw_init(void);
1656 +void rtesw_exit(void);
1657 +
1658 +#else
1659 +
1660 +static inline int __init rtesw_init(void) { return 0; }
1661 +static inline void rtesw_exit(void) { }
1662 +
1663 +#endif
1664 +#endif
1665 --- /dev/null
1666 +++ b/drivers/net/ethernet/ralink/gsw_mt7620a.c
1667 @@ -0,0 +1,1027 @@
1668 +/*
1669 + * This program is free software; you can redistribute it and/or modify
1670 + * it under the terms of the GNU General Public License as published by
1671 + * the Free Software Foundation; version 2 of the License
1672 + *
1673 + * This program is distributed in the hope that it will be useful,
1674 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1675 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1676 + * GNU General Public License for more details.
1677 + *
1678 + * You should have received a copy of the GNU General Public License
1679 + * along with this program; if not, write to the Free Software
1680 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
1681 + *
1682 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
1683 + */
1684 +
1685 +#include <linux/module.h>
1686 +#include <linux/kernel.h>
1687 +#include <linux/types.h>
1688 +#include <linux/dma-mapping.h>
1689 +#include <linux/init.h>
1690 +#include <linux/skbuff.h>
1691 +#include <linux/etherdevice.h>
1692 +#include <linux/ethtool.h>
1693 +#include <linux/platform_device.h>
1694 +#include <linux/of_device.h>
1695 +#include <linux/clk.h>
1696 +#include <linux/of_net.h>
1697 +#include <linux/of_mdio.h>
1698 +#include <linux/of_irq.h>
1699 +#include <linux/of_address.h>
1700 +#include <linux/switch.h>
1701 +
1702 +#include <asm/mach-ralink/ralink_regs.h>
1703 +
1704 +#include "ralink_soc_eth.h"
1705 +
1706 +#include <linux/ioport.h>
1707 +#include <linux/switch.h>
1708 +#include <linux/mii.h>
1709 +
1710 +#include <ralink_regs.h>
1711 +#include <asm/mach-ralink/mt7620.h>
1712 +
1713 +#include "ralink_soc_eth.h"
1714 +#include "gsw_mt7620a.h"
1715 +#include "mdio.h"
1716 +
1717 +#define GSW_REG_PHY_TIMEOUT (5 * HZ)
1718 +
1719 +#define MT7620A_GSW_REG_PIAC 0x7004
1720 +
1721 +#define GSW_NUM_VLANS 16
1722 +#define GSW_NUM_VIDS 4096
1723 +#define GSW_NUM_PORTS 7
1724 +#define GSW_PORT6 6
1725 +
1726 +#define GSW_MDIO_ACCESS BIT(31)
1727 +#define GSW_MDIO_READ BIT(19)
1728 +#define GSW_MDIO_WRITE BIT(18)
1729 +#define GSW_MDIO_START BIT(16)
1730 +#define GSW_MDIO_ADDR_SHIFT 20
1731 +#define GSW_MDIO_REG_SHIFT 25
1732 +
1733 +#define GSW_REG_PORT_PMCR(x) (0x3000 + (x * 0x100))
1734 +#define GSW_REG_PORT_STATUS(x) (0x3008 + (x * 0x100))
1735 +#define GSW_REG_SMACCR0 0x3fE4
1736 +#define GSW_REG_SMACCR1 0x3fE8
1737 +#define GSW_REG_CKGCR 0x3ff0
1738 +
1739 +#define GSW_REG_IMR 0x7008
1740 +#define GSW_REG_ISR 0x700c
1741 +
1742 +#define SYSC_REG_CFG1 0x14
1743 +
1744 +#define PORT_IRQ_ST_CHG 0x7f
1745 +
1746 +#define GSW_VLAN_VTCR 0x90
1747 +#define GSW_VLAN_VTCR_VID_M 0xfff
1748 +#define GSW_VLAN_ID(_x) (0x100 + (4 * (_x)))
1749 +#define GSW_VLAN_ID_VID_S 12
1750 +#define GSW_VLAN_ID_VID_M 0xfff
1751 +
1752 +#define GSW_VAWD1 0x94
1753 +#define GSW_VAWD1_VTAG_EN BIT(28)
1754 +#define GSW_VAWD1_PORTM_S 16
1755 +#define GSW_VAWD1_PORTM_M 0xff
1756 +
1757 +#define GSW_VAWD2 0x98
1758 +#define GSW_VAWD2_PORTT_S 16
1759 +#define GSW_VAWD2_PORTT_M 0xff
1760 +
1761 +#define GSW_VTIM(_x) (0x100 + (4 * (_x)))
1762 +#define GSW_VTIM_M 0xfff
1763 +#define GSW_VTIM_S 12
1764 +
1765 +#define GSW_REG_PCR(x) (0x2004 + (x * 0x100))
1766 +#define GSW_REG_PCR_EG_TAG_S 28
1767 +#define GSW_REG_PCR_EG_TAG_M 0x3
1768 +
1769 +#define SYSCFG1 0x14
1770 +
1771 +#define ESW_PHY_POLLING 0x7000
1772 +
1773 +#define PMCR_IPG BIT(18)
1774 +#define PMCR_MAC_MODE BIT(16)
1775 +#define PMCR_FORCE BIT(15)
1776 +#define PMCR_TX_EN BIT(14)
1777 +#define PMCR_RX_EN BIT(13)
1778 +#define PMCR_BACKOFF BIT(9)
1779 +#define PMCR_BACKPRES BIT(8)
1780 +#define PMCR_RX_FC BIT(5)
1781 +#define PMCR_TX_FC BIT(4)
1782 +#define PMCR_SPEED(_x) (_x << 2)
1783 +#define PMCR_DUPLEX BIT(1)
1784 +#define PMCR_LINK BIT(0)
1785 +
1786 +#define PHY_AN_EN BIT(31)
1787 +#define PHY_PRE_EN BIT(30)
1788 +#define PMY_MDC_CONF(_x) ((_x & 0x3f) << 24)
1789 +
1790 +enum {
1791 + /* Global attributes. */
1792 + GSW_ATTR_ENABLE_VLAN,
1793 + /* Port attributes. */
1794 + GSW_ATTR_PORT_UNTAG,
1795 +};
1796 +
1797 +enum {
1798 + PORT4_EPHY = 0,
1799 + PORT4_EXT,
1800 +};
1801 +
1802 +struct gsw_port {
1803 + bool disable;
1804 + bool untag;
1805 + u16 pvid;
1806 +};
1807 +
1808 +struct gsw_vlan {
1809 + u8 ports;
1810 + u16 vid;
1811 +};
1812 +
1813 +struct mt7620_gsw {
1814 + struct device *dev;
1815 + void __iomem *base;
1816 + int irq;
1817 +
1818 + struct switch_dev swdev;
1819 + bool global_vlan_enable;
1820 + struct gsw_vlan vlans[GSW_NUM_VLANS];
1821 + struct gsw_port ports[GSW_NUM_PORTS];
1822 + long unsigned int autopoll;
1823 + int port4;
1824 +};
1825 +
1826 +static inline void gsw_w32(struct mt7620_gsw *gsw, u32 val, unsigned reg)
1827 +{
1828 + iowrite32(val, gsw->base + reg);
1829 +}
1830 +
1831 +static inline u32 gsw_r32(struct mt7620_gsw *gsw, unsigned reg)
1832 +{
1833 + return ioread32(gsw->base + reg);
1834 +}
1835 +
1836 +static int mt7620_mii_busy_wait(struct mt7620_gsw *gsw)
1837 +{
1838 + unsigned long t_start = jiffies;
1839 +
1840 + while (1) {
1841 + if (!(gsw_r32(gsw, MT7620A_GSW_REG_PIAC) & GSW_MDIO_ACCESS))
1842 + return 0;
1843 + if (time_after(jiffies, t_start + GSW_REG_PHY_TIMEOUT)) {
1844 + break;
1845 + }
1846 + }
1847 +
1848 + printk(KERN_ERR "mdio: MDIO timeout\n");
1849 + return -1;
1850 +}
1851 +
1852 +static u32 _mt7620_mii_write(struct mt7620_gsw *gsw, u32 phy_addr, u32 phy_register,
1853 + u32 write_data)
1854 +{
1855 + if (mt7620_mii_busy_wait(gsw))
1856 + return -1;
1857 +
1858 + write_data &= 0xffff;
1859 +
1860 + gsw_w32(gsw, GSW_MDIO_ACCESS | GSW_MDIO_START | GSW_MDIO_WRITE |
1861 + (phy_register << GSW_MDIO_REG_SHIFT) |
1862 + (phy_addr << GSW_MDIO_ADDR_SHIFT) | write_data,
1863 + MT7620A_GSW_REG_PIAC);
1864 +
1865 + if (mt7620_mii_busy_wait(gsw))
1866 + return -1;
1867 +
1868 + return 0;
1869 +}
1870 +
1871 +int mt7620_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val)
1872 +{
1873 + struct fe_priv *priv = bus->priv;
1874 + struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
1875 +
1876 + return _mt7620_mii_write(gsw, phy_addr, phy_reg, val);
1877 +}
1878 +
1879 +int mt7620_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)
1880 +{
1881 + struct fe_priv *priv = bus->priv;
1882 + struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
1883 + u32 d;
1884 +
1885 + if (mt7620_mii_busy_wait(gsw))
1886 + return 0xffff;
1887 +
1888 + gsw_w32(gsw, GSW_MDIO_ACCESS | GSW_MDIO_START | GSW_MDIO_READ |
1889 + (phy_reg << GSW_MDIO_REG_SHIFT) |
1890 + (phy_addr << GSW_MDIO_ADDR_SHIFT),
1891 + MT7620A_GSW_REG_PIAC);
1892 +
1893 + if (mt7620_mii_busy_wait(gsw))
1894 + return 0xffff;
1895 +
1896 + d = gsw_r32(gsw, MT7620A_GSW_REG_PIAC) & 0xffff;
1897 +
1898 + return d;
1899 +}
1900 +
1901 +static unsigned char *fe_speed_str(int speed)
1902 +{
1903 + switch (speed) {
1904 + case 2:
1905 + case SPEED_1000:
1906 + return "1000";
1907 + case 1:
1908 + case SPEED_100:
1909 + return "100";
1910 + case 0:
1911 + case SPEED_10:
1912 + return "10";
1913 + }
1914 +
1915 + return "? ";
1916 +}
1917 +
1918 +int mt7620a_has_carrier(struct fe_priv *priv)
1919 +{
1920 + struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
1921 + int i;
1922 +
1923 + for (i = 0; i < GSW_PORT6; i++)
1924 + if (gsw_r32(gsw, GSW_REG_PORT_STATUS(i)) & 0x1)
1925 + return 1;
1926 + return 0;
1927 +}
1928 +
1929 +static void mt7620a_handle_carrier(struct fe_priv *priv)
1930 +{
1931 + if (!priv->phy)
1932 + return;
1933 +
1934 + if (mt7620a_has_carrier(priv))
1935 + netif_carrier_on(priv->netdev);
1936 + else
1937 + netif_carrier_off(priv->netdev);
1938 +}
1939 +
1940 +void mt7620_mdio_link_adjust(struct fe_priv *priv, int port)
1941 +{
1942 + if (priv->link[port])
1943 + netdev_info(priv->netdev, "port %d link up (%sMbps/%s duplex)\n",
1944 + port, fe_speed_str(priv->phy->speed[port]),
1945 + (DUPLEX_FULL == priv->phy->duplex[port]) ? "Full" : "Half");
1946 + else
1947 + netdev_info(priv->netdev, "port %d link down\n", port);
1948 + mt7620a_handle_carrier(priv);
1949 +}
1950 +
1951 +static irqreturn_t gsw_interrupt(int irq, void *_priv)
1952 +{
1953 + struct fe_priv *priv = (struct fe_priv *) _priv;
1954 + struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
1955 + u32 status;
1956 + int i, max = (gsw->port4 == PORT4_EPHY) ? (4) : (3);
1957 +
1958 + status = gsw_r32(gsw, GSW_REG_ISR);
1959 + if (status & PORT_IRQ_ST_CHG)
1960 + for (i = 0; i <= max; i++) {
1961 + u32 status = gsw_r32(gsw, GSW_REG_PORT_STATUS(i));
1962 + int link = status & 0x1;
1963 +
1964 + if (link != priv->link[i]) {
1965 + if (link)
1966 + netdev_info(priv->netdev, "port %d link up (%sMbps/%s duplex)\n",
1967 + i, fe_speed_str((status >> 2) & 3),
1968 + (status & 0x2) ? "Full" : "Half");
1969 + else
1970 + netdev_info(priv->netdev, "port %d link down\n", i);
1971 + }
1972 +
1973 + priv->link[i] = link;
1974 + }
1975 + mt7620a_handle_carrier(priv);
1976 +
1977 + gsw_w32(gsw, status, GSW_REG_ISR);
1978 +
1979 + return IRQ_HANDLED;
1980 +}
1981 +
1982 +static int mt7620_is_bga(void)
1983 +{
1984 + u32 bga = rt_sysc_r32(0x0c);
1985 +
1986 + return (bga >> 16) & 1;
1987 +}
1988 +
1989 +static void gsw_auto_poll(struct mt7620_gsw *gsw)
1990 +{
1991 + int phy;
1992 + int lsb = -1, msb = 0;
1993 +
1994 + for_each_set_bit(phy, &gsw->autopoll, 32) {
1995 + if (lsb < 0)
1996 + lsb = phy;
1997 + msb = phy;
1998 + }
1999 +
2000 + gsw_w32(gsw, PHY_AN_EN | PHY_PRE_EN | PMY_MDC_CONF(5) | (msb << 8) | lsb, ESW_PHY_POLLING);
2001 +}
2002 +
2003 +void mt7620_port_init(struct fe_priv *priv, struct device_node *np)
2004 +{
2005 + struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
2006 + const __be32 *_id = of_get_property(np, "reg", NULL);
2007 + int phy_mode, size, id;
2008 + int shift = 12;
2009 + u32 val, mask = 0;
2010 + int min = (gsw->port4 == PORT4_EPHY) ? (5) : (4);
2011 +
2012 + if (!_id || (be32_to_cpu(*_id) < min) || (be32_to_cpu(*_id) > 5)) {
2013 + if (_id)
2014 + pr_err("%s: invalid port id %d\n", np->name, be32_to_cpu(*_id));
2015 + else
2016 + pr_err("%s: invalid port id\n", np->name);
2017 + return;
2018 + }
2019 +
2020 + id = be32_to_cpu(*_id);
2021 +
2022 + if (id == 4)
2023 + shift = 14;
2024 +
2025 + priv->phy->phy_fixed[id] = of_get_property(np, "ralink,fixed-link", &size);
2026 + if (priv->phy->phy_fixed[id] && (size != (4 * sizeof(*priv->phy->phy_fixed[id])))) {
2027 + pr_err("%s: invalid fixed link property\n", np->name);
2028 + priv->phy->phy_fixed[id] = NULL;
2029 + return;
2030 + }
2031 +
2032 + phy_mode = of_get_phy_mode(np);
2033 + switch (phy_mode) {
2034 + case PHY_INTERFACE_MODE_RGMII:
2035 + mask = 0;
2036 + break;
2037 + case PHY_INTERFACE_MODE_MII:
2038 + mask = 1;
2039 + break;
2040 + case PHY_INTERFACE_MODE_RMII:
2041 + mask = 2;
2042 + break;
2043 + default:
2044 + dev_err(priv->device, "port %d - invalid phy mode\n", priv->phy->speed[id]);
2045 + return;
2046 + }
2047 +
2048 + priv->phy->phy_node[id] = of_parse_phandle(np, "phy-handle", 0);
2049 + if (!priv->phy->phy_node[id] && !priv->phy->phy_fixed[id])
2050 + return;
2051 +
2052 + val = rt_sysc_r32(SYSCFG1);
2053 + val &= ~(3 << shift);
2054 + val |= mask << shift;
2055 + rt_sysc_w32(val, SYSCFG1);
2056 +
2057 + if (priv->phy->phy_fixed[id]) {
2058 + const __be32 *link = priv->phy->phy_fixed[id];
2059 + int tx_fc = be32_to_cpup(link++);
2060 + int rx_fc = be32_to_cpup(link++);
2061 + u32 val = 0;
2062 +
2063 + priv->phy->speed[id] = be32_to_cpup(link++);
2064 + priv->phy->duplex[id] = be32_to_cpup(link++);
2065 + priv->link[id] = 1;
2066 +
2067 + switch (priv->phy->speed[id]) {
2068 + case SPEED_10:
2069 + val = 0;
2070 + break;
2071 + case SPEED_100:
2072 + val = 1;
2073 + break;
2074 + case SPEED_1000:
2075 + val = 2;
2076 + break;
2077 + default:
2078 + dev_err(priv->device, "invalid link speed: %d\n", priv->phy->speed[id]);
2079 + priv->phy->phy_fixed[id] = 0;
2080 + return;
2081 + }
2082 + val = PMCR_SPEED(val);
2083 + val |= PMCR_LINK | PMCR_BACKPRES | PMCR_BACKOFF | PMCR_RX_EN |
2084 + PMCR_TX_EN | PMCR_FORCE | PMCR_MAC_MODE | PMCR_IPG;
2085 + if (tx_fc)
2086 + val |= PMCR_TX_FC;
2087 + if (rx_fc)
2088 + val |= PMCR_RX_FC;
2089 + if (priv->phy->duplex[id])
2090 + val |= PMCR_DUPLEX;
2091 + gsw_w32(gsw, val, GSW_REG_PORT_PMCR(id));
2092 + dev_info(priv->device, "using fixed link parameters\n");
2093 + return;
2094 + }
2095 +
2096 + if (priv->phy->phy_node[id] && priv->mii_bus->phy_map[id]) {
2097 + u32 val = PMCR_BACKPRES | PMCR_BACKOFF | PMCR_RX_EN |
2098 + PMCR_TX_EN | PMCR_MAC_MODE | PMCR_IPG;
2099 +
2100 + gsw_w32(gsw, val, GSW_REG_PORT_PMCR(id));
2101 + fe_connect_phy_node(priv, priv->phy->phy_node[id]);
2102 + gsw->autopoll |= BIT(id);
2103 + gsw_auto_poll(gsw);
2104 + return;
2105 + }
2106 +}
2107 +
2108 +static void gsw_hw_init(struct mt7620_gsw *gsw)
2109 +{
2110 + u32 is_BGA = mt7620_is_bga();
2111 +
2112 + rt_sysc_w32(rt_sysc_r32(SYSC_REG_CFG1) | BIT(8), SYSC_REG_CFG1);
2113 + gsw_w32(gsw, gsw_r32(gsw, GSW_REG_CKGCR) & ~(0x3 << 4), GSW_REG_CKGCR);
2114 +
2115 + /*correct PHY setting L3.0 BGA*/
2116 + _mt7620_mii_write(gsw, 1, 31, 0x4000); //global, page 4
2117 +
2118 + _mt7620_mii_write(gsw, 1, 17, 0x7444);
2119 + if (is_BGA)
2120 + _mt7620_mii_write(gsw, 1, 19, 0x0114);
2121 + else
2122 + _mt7620_mii_write(gsw, 1, 19, 0x0117);
2123 +
2124 + _mt7620_mii_write(gsw, 1, 22, 0x10cf);
2125 + _mt7620_mii_write(gsw, 1, 25, 0x6212);
2126 + _mt7620_mii_write(gsw, 1, 26, 0x0777);
2127 + _mt7620_mii_write(gsw, 1, 29, 0x4000);
2128 + _mt7620_mii_write(gsw, 1, 28, 0xc077);
2129 + _mt7620_mii_write(gsw, 1, 24, 0x0000);
2130 +
2131 + _mt7620_mii_write(gsw, 1, 31, 0x3000); //global, page 3
2132 + _mt7620_mii_write(gsw, 1, 17, 0x4838);
2133 +
2134 + _mt7620_mii_write(gsw, 1, 31, 0x2000); //global, page 2
2135 + if (is_BGA) {
2136 + _mt7620_mii_write(gsw, 1, 21, 0x0515);
2137 + _mt7620_mii_write(gsw, 1, 22, 0x0053);
2138 + _mt7620_mii_write(gsw, 1, 23, 0x00bf);
2139 + _mt7620_mii_write(gsw, 1, 24, 0x0aaf);
2140 + _mt7620_mii_write(gsw, 1, 25, 0x0fad);
2141 + _mt7620_mii_write(gsw, 1, 26, 0x0fc1);
2142 + } else {
2143 + _mt7620_mii_write(gsw, 1, 21, 0x0517);
2144 + _mt7620_mii_write(gsw, 1, 22, 0x0fd2);
2145 + _mt7620_mii_write(gsw, 1, 23, 0x00bf);
2146 + _mt7620_mii_write(gsw, 1, 24, 0x0aab);
2147 + _mt7620_mii_write(gsw, 1, 25, 0x00ae);
2148 + _mt7620_mii_write(gsw, 1, 26, 0x0fff);
2149 + }
2150 + _mt7620_mii_write(gsw, 1, 31, 0x1000); //global, page 1
2151 + _mt7620_mii_write(gsw, 1, 17, 0xe7f8);
2152 +
2153 + _mt7620_mii_write(gsw, 1, 31, 0x8000); //local, page 0
2154 + _mt7620_mii_write(gsw, 0, 30, 0xa000);
2155 + _mt7620_mii_write(gsw, 1, 30, 0xa000);
2156 + _mt7620_mii_write(gsw, 2, 30, 0xa000);
2157 + _mt7620_mii_write(gsw, 3, 30, 0xa000);
2158 +
2159 + _mt7620_mii_write(gsw, 0, 4, 0x05e1);
2160 + _mt7620_mii_write(gsw, 1, 4, 0x05e1);
2161 + _mt7620_mii_write(gsw, 2, 4, 0x05e1);
2162 + _mt7620_mii_write(gsw, 3, 4, 0x05e1);
2163 + _mt7620_mii_write(gsw, 1, 31, 0xa000); //local, page 2
2164 + _mt7620_mii_write(gsw, 0, 16, 0x1111);
2165 + _mt7620_mii_write(gsw, 1, 16, 0x1010);
2166 + _mt7620_mii_write(gsw, 2, 16, 0x1515);
2167 + _mt7620_mii_write(gsw, 3, 16, 0x0f0f);
2168 +
2169 + /* CPU Port6 Force Link 1G, FC ON */
2170 + gsw_w32(gsw, 0x5e33b, GSW_REG_PORT_PMCR(6));
2171 + /* Set Port6 CPU Port */
2172 + gsw_w32(gsw, 0x7f7f7fe0, 0x0010);
2173 +
2174 +// GSW_VAWD2
2175 +
2176 + /* setup port 4 */
2177 + if (gsw->port4 == PORT4_EPHY) {
2178 + u32 val = rt_sysc_r32(SYSCFG1);
2179 + val |= 3 << 14;
2180 + rt_sysc_w32(val, SYSCFG1);
2181 + _mt7620_mii_write(gsw, 4, 30, 0xa000);
2182 + _mt7620_mii_write(gsw, 4, 4, 0x05e1);
2183 + _mt7620_mii_write(gsw, 4, 16, 0x1313);
2184 + pr_info("gsw: setting port4 to ephy mode\n");
2185 + }
2186 +}
2187 +
2188 +static int gsw_reset_switch(struct switch_dev *dev)
2189 +{
2190 + struct mt7620_gsw *gsw = container_of(dev, struct mt7620_gsw, swdev);
2191 +
2192 + gsw->global_vlan_enable = 0;
2193 + memset(gsw->ports, 0, sizeof(gsw->ports));
2194 + memset(gsw->vlans, 0, sizeof(gsw->vlans));
2195 + gsw_hw_init(gsw);
2196 +
2197 + return 0;
2198 +}
2199 +
2200 +static int gsw_get_vlan_enable(struct switch_dev *dev,
2201 + const struct switch_attr *attr,
2202 + struct switch_val *val)
2203 +{
2204 + struct mt7620_gsw *gsw = container_of(dev, struct mt7620_gsw, swdev);
2205 +
2206 + val->value.i = gsw->global_vlan_enable;
2207 +
2208 + return 0;
2209 +}
2210 +
2211 +static int gsw_set_vlan_enable(struct switch_dev *dev,
2212 + const struct switch_attr *attr,
2213 + struct switch_val *val)
2214 +{
2215 + struct mt7620_gsw *gsw = container_of(dev, struct mt7620_gsw, swdev);
2216 +
2217 + gsw->global_vlan_enable = val->value.i != 0;
2218 +
2219 + return 0;
2220 +}
2221 +
2222 +static unsigned gsw_get_pvid(struct mt7620_gsw *gsw, unsigned port)
2223 +{
2224 + unsigned s, val;
2225 +
2226 + s = GSW_VTIM_S * (port % 2);
2227 + val = gsw_r32(gsw, GSW_VTIM(port / 2));
2228 +
2229 + return (val >> s) & GSW_VTIM_M;
2230 +}
2231 +
2232 +static void gsw_set_pvid(struct mt7620_gsw *gsw, unsigned port, unsigned pvid)
2233 +{
2234 + unsigned s, val;
2235 +
2236 + s = GSW_VTIM_S * (port % 2);
2237 + val = gsw_r32(gsw, GSW_VTIM(port / 2));
2238 + val &= ~(GSW_VTIM_M << s);
2239 + val |= (pvid && GSW_VTIM_M) << s;
2240 + gsw_w32(gsw, val, GSW_VTIM(port / 2));
2241 +}
2242 +
2243 +static int gsw_get_port_bool(struct switch_dev *dev,
2244 + const struct switch_attr *attr,
2245 + struct switch_val *val)
2246 +{
2247 + struct mt7620_gsw *gsw = container_of(dev, struct mt7620_gsw, swdev);
2248 + int idx = val->port_vlan;
2249 +
2250 + if (idx < 0 || idx >= GSW_NUM_PORTS)
2251 + return -EINVAL;
2252 +
2253 + switch (attr->id) {
2254 + case GSW_ATTR_PORT_UNTAG:
2255 + return gsw->ports[idx].untag;
2256 + }
2257 +
2258 + return -EINVAL;
2259 +}
2260 +
2261 +static int gsw_get_port_pvid(struct switch_dev *dev, int port, int *val)
2262 +{
2263 + struct mt7620_gsw *gsw = container_of(dev, struct mt7620_gsw, swdev);
2264 +
2265 + if (port >= GSW_NUM_PORTS)
2266 + return -EINVAL;
2267 +
2268 + *val = gsw_get_pvid(gsw, port);
2269 +
2270 + return 0;
2271 +}
2272 +
2273 +static int gsw_set_port_pvid(struct switch_dev *dev, int port, int val)
2274 +{
2275 + struct mt7620_gsw *gsw = container_of(dev, struct mt7620_gsw, swdev);
2276 +
2277 + if (port >= GSW_NUM_PORTS)
2278 + return -EINVAL;
2279 +
2280 + gsw->ports[port].pvid = val;
2281 +
2282 + return 0;
2283 +}
2284 +
2285 +static void gsw_set_vtcr(struct switch_dev *dev, u32 vid)
2286 +{
2287 + struct mt7620_gsw *gsw = container_of(dev, struct mt7620_gsw, swdev);
2288 + int retry = 1000;
2289 +
2290 + gsw_w32(gsw, 0x80000000 | (BIT(vid) & GSW_VLAN_VTCR_VID_M), GSW_VLAN_VTCR);
2291 + while (retry-- && (gsw_r32(gsw, GSW_VLAN_VTCR) & 0x80000000))
2292 + ;
2293 +}
2294 +
2295 +static void gsw_apply_vtcr(struct switch_dev *dev, u32 vid)
2296 +{
2297 + struct mt7620_gsw *gsw = container_of(dev, struct mt7620_gsw, swdev);
2298 + int retry = 1000;
2299 +
2300 + gsw_w32(gsw, 0x80001000 | (BIT(vid) & GSW_VLAN_VTCR_VID_M), GSW_VLAN_VTCR);
2301 + while (retry-- && (gsw_r32(gsw, GSW_VLAN_VTCR) & 0x80000000))
2302 + ;
2303 +}
2304 +
2305 +static unsigned gsw_get_vlan_id(struct mt7620_gsw *gsw, unsigned vlan)
2306 +{
2307 + unsigned s;
2308 + unsigned val;
2309 +
2310 + s = GSW_VLAN_ID_VID_S * (vlan % 2);
2311 + val = gsw_r32(gsw, GSW_VLAN_ID(vlan / 2));
2312 + val = (val >> s) & GSW_VLAN_ID_VID_M;
2313 +
2314 + return val;
2315 +}
2316 +
2317 +static void gsw_set_vlan_id(struct mt7620_gsw *gsw, unsigned vlan, unsigned vid)
2318 +{
2319 + unsigned s;
2320 + unsigned val;
2321 +
2322 + s = GSW_VLAN_ID_VID_S * (vlan % 2);
2323 + val = gsw_r32(gsw, GSW_VLAN_ID(vlan / 2));
2324 + val &= ~(GSW_VLAN_ID_VID_M << s);
2325 + val |= (vid << s);
2326 + gsw_w32(gsw, val, GSW_VLAN_ID(vlan / 2));
2327 +}
2328 +
2329 +static void gsw_vlan_tagging_enable(struct mt7620_gsw *gsw, unsigned vlan, unsigned enable)
2330 +{
2331 + unsigned val;
2332 +
2333 + val = gsw_r32(gsw, GSW_VAWD1);
2334 + if (enable)
2335 + val |= GSW_VAWD1_VTAG_EN;
2336 + else
2337 + val &= ~GSW_VAWD1_VTAG_EN;
2338 + gsw_w32(gsw, val, GSW_VAWD1);
2339 +}
2340 +
2341 +static unsigned gsw_get_port_member(struct mt7620_gsw *gsw, unsigned vlan)
2342 +{
2343 + unsigned val;
2344 +
2345 + gsw_set_vtcr(&gsw->swdev, vlan);
2346 +
2347 + val = gsw_r32(gsw, GSW_VAWD1);
2348 + val = (val >> GSW_VAWD1_PORTM_S) & GSW_VAWD1_PORTM_M;
2349 +
2350 + return val;
2351 +}
2352 +
2353 +static void gsw_set_port_member(struct mt7620_gsw *gsw, unsigned vlan, unsigned member)
2354 +{
2355 + unsigned val;
2356 +
2357 + val = gsw_r32(gsw, GSW_VAWD1);
2358 + val = ~(GSW_VAWD1_PORTM_M << GSW_VAWD1_PORTM_S);
2359 + val |= (member & GSW_VAWD1_PORTM_M) << GSW_VAWD1_PORTM_S;
2360 + gsw_w32(gsw, val, GSW_VAWD1);
2361 +}
2362 +
2363 +static unsigned gsw_get_port_tag(struct mt7620_gsw *gsw, unsigned port)
2364 +{
2365 + unsigned val;
2366 +
2367 + val = gsw_r32(gsw, GSW_REG_PCR(port));
2368 + val >>= GSW_REG_PCR_EG_TAG_S;
2369 + val &= GSW_REG_PCR_EG_TAG_M;
2370 +
2371 + return !!val;
2372 +}
2373 +
2374 +static void gsw_set_port_untag(struct mt7620_gsw *gsw, unsigned port, unsigned untag)
2375 +{
2376 + unsigned val;
2377 +
2378 + val = gsw_r32(gsw, GSW_REG_PCR(port));
2379 + if (!untag)
2380 + untag = 0x2;
2381 + else
2382 + untag = 0;
2383 + val &= ~(GSW_REG_PCR_EG_TAG_M << GSW_REG_PCR_EG_TAG_S);
2384 + val |= (untag & GSW_REG_PCR_EG_TAG_M) << GSW_REG_PCR_EG_TAG_S;
2385 + gsw_w32(gsw, val, GSW_REG_PCR(port));
2386 +}
2387 +
2388 +static int gsw_get_vlan_ports(struct switch_dev *dev, struct switch_val *val)
2389 +{
2390 + struct mt7620_gsw *gsw = container_of(dev, struct mt7620_gsw, swdev);
2391 + int vlan_idx = -1;
2392 + u32 member;
2393 + int i;
2394 +
2395 + val->len = 0;
2396 +
2397 + if (val->port_vlan < 0 || val->port_vlan >= GSW_NUM_VIDS)
2398 + return -EINVAL;
2399 +
2400 + /* valid vlan? */
2401 + for (i = 0; i < GSW_NUM_VLANS; i++) {
2402 + if (gsw_get_vlan_id(gsw, i) != val->port_vlan)
2403 + continue;
2404 + member = gsw_get_port_member(gsw, i);
2405 + vlan_idx = i;
2406 + break;
2407 + }
2408 +
2409 + if (vlan_idx == -1)
2410 + return -EINVAL;
2411 +
2412 + for (i = 0; i < GSW_NUM_PORTS; i++) {
2413 + struct switch_port *p;
2414 + int port_mask = 1 << i;
2415 +
2416 + if (!(member & port_mask))
2417 + continue;
2418 +
2419 + p = &val->value.ports[val->len++];
2420 + p->id = i;
2421 + if (gsw_get_port_tag(gsw, i))
2422 + p->flags = 1 << SWITCH_PORT_FLAG_TAGGED;
2423 + else
2424 + p->flags = 0;
2425 + }
2426 +
2427 + return 0;
2428 +}
2429 +
2430 +static int gsw_set_vlan_ports(struct switch_dev *dev, struct switch_val *val)
2431 +{
2432 + struct mt7620_gsw *gsw = container_of(dev, struct mt7620_gsw, swdev);
2433 + int ports;
2434 + int vlan_idx = -1;
2435 + int i;
2436 +
2437 + if (val->port_vlan < 0 || val->port_vlan >= GSW_NUM_VIDS ||
2438 + val->len > GSW_NUM_PORTS)
2439 + return -EINVAL;
2440 +
2441 + /* one of the already defined vlans? */
2442 + for (i = 0; i < GSW_NUM_VLANS; i++) {
2443 + if (gsw->vlans[i].vid == val->port_vlan &&
2444 + gsw->vlans[i].ports) {
2445 + vlan_idx = i;
2446 + break;
2447 + }
2448 + }
2449 +
2450 + /* select a free slot */
2451 + for (i = 0; vlan_idx == -1 && i < GSW_NUM_VLANS; i++) {
2452 + if (!gsw->vlans[i].ports)
2453 + vlan_idx = i;
2454 + }
2455 +
2456 + /* bail if all slots are in use */
2457 + if (vlan_idx == -1)
2458 + return -EINVAL;
2459 +
2460 + ports = 0;
2461 + for (i = 0; i < val->len; i++) {
2462 + struct switch_port *p = &val->value.ports[i];
2463 + int port_mask = 1 << p->id;
2464 + bool untagged = !(p->flags & (1 << SWITCH_PORT_FLAG_TAGGED));
2465 +
2466 + if (p->id >= GSW_NUM_PORTS)
2467 + return -EINVAL;
2468 +
2469 + ports |= port_mask;
2470 + gsw->ports[p->id].untag = untagged;
2471 + }
2472 + gsw->vlans[vlan_idx].ports = ports;
2473 + if (!ports)
2474 + gsw->vlans[vlan_idx].vid = 0xfff;
2475 + else
2476 + gsw->vlans[vlan_idx].vid = val->port_vlan;
2477 +
2478 + return 0;
2479 +}
2480 +
2481 +static int gsw_apply_config(struct switch_dev *dev)
2482 +{
2483 + struct mt7620_gsw *gsw = container_of(dev, struct mt7620_gsw, swdev);
2484 + int i;
2485 +
2486 + for (i = 0; i < GSW_NUM_VLANS; i++) {
2487 + gsw_set_vtcr(&gsw->swdev, i);
2488 + if (gsw->global_vlan_enable) {
2489 + gsw_set_vlan_id(gsw, i, gsw->vlans[i].vid);
2490 + gsw_set_port_member(gsw, i, gsw->vlans[i].ports);
2491 + gsw_vlan_tagging_enable(gsw, i, 1);
2492 + } else {
2493 + gsw_set_vlan_id(gsw, i, 0xfff);
2494 + gsw_set_port_member(gsw, i, 0);
2495 + gsw_vlan_tagging_enable(gsw, i, 0);
2496 + }
2497 + gsw_apply_vtcr(&gsw->swdev, i);
2498 + }
2499 +
2500 + for (i = 0; i < GSW_NUM_PORTS; i++) {
2501 + if (gsw->global_vlan_enable) {
2502 + gsw_set_port_untag(gsw, i, !gsw->ports[i].untag);
2503 + gsw_set_pvid(gsw, i, gsw->ports[i].pvid);
2504 + } else {
2505 + gsw_set_port_untag(gsw, i, 0);
2506 + gsw_set_pvid(gsw, i, 0);
2507 + }
2508 + }
2509 +
2510 + if (!gsw->global_vlan_enable)
2511 + gsw_set_vlan_id(gsw, 0, 0);
2512 +
2513 + return 0;
2514 +}
2515 +
2516 +static int gsw_get_port_link(struct switch_dev *dev,
2517 + int port,
2518 + struct switch_port_link *link)
2519 +{
2520 + struct mt7620_gsw *gsw = container_of(dev, struct mt7620_gsw, swdev);
2521 + u32 status;
2522 +
2523 + if (port < 0 || port >= GSW_NUM_PORTS)
2524 + return -EINVAL;
2525 +
2526 + status = gsw_r32(gsw, GSW_REG_PORT_STATUS(port));
2527 + link->link = status & 0x1;
2528 + link->duplex = (status >> 1) & 1;
2529 +
2530 + switch ((status >> 2) & 0x3) {
2531 + case 0:
2532 + link->speed = SWITCH_PORT_SPEED_10;
2533 + break;
2534 + case 1:
2535 + link->speed = SWITCH_PORT_SPEED_100;
2536 + break;
2537 + case 2:
2538 + case 3: // forced gige speed can be 2 or 3
2539 + link->speed = SWITCH_PORT_SPEED_1000;
2540 + break;
2541 + }
2542 +
2543 + return 0;
2544 +}
2545 +
2546 +static int gsw_set_port_bool(struct switch_dev *dev,
2547 + const struct switch_attr *attr,
2548 + struct switch_val *val)
2549 +{
2550 + struct mt7620_gsw *gsw = container_of(dev, struct mt7620_gsw, swdev);
2551 + int idx = val->port_vlan;
2552 +
2553 + if (idx < 0 || idx >= GSW_NUM_PORTS ||
2554 + val->value.i < 0 || val->value.i > 1)
2555 + return -EINVAL;
2556 +
2557 + switch (attr->id) {
2558 + case GSW_ATTR_PORT_UNTAG:
2559 + gsw->ports[idx].untag = val->value.i;
2560 + break;
2561 + default:
2562 + return -EINVAL;
2563 + }
2564 +
2565 + return 0;
2566 +}
2567 +
2568 +static const struct switch_attr gsw_global[] = {
2569 + {
2570 + .type = SWITCH_TYPE_INT,
2571 + .name = "enable_vlan",
2572 + .description = "VLAN mode (1:enabled)",
2573 + .max = 1,
2574 + .id = GSW_ATTR_ENABLE_VLAN,
2575 + .get = gsw_get_vlan_enable,
2576 + .set = gsw_set_vlan_enable,
2577 + },
2578 +};
2579 +
2580 +static const struct switch_attr gsw_port[] = {
2581 + {
2582 + .type = SWITCH_TYPE_INT,
2583 + .name = "untag",
2584 + .description = "Untag (1:strip outgoing vlan tag)",
2585 + .max = 1,
2586 + .id = GSW_ATTR_PORT_UNTAG,
2587 + .get = gsw_get_port_bool,
2588 + .set = gsw_set_port_bool,
2589 + },
2590 +};
2591 +
2592 +static const struct switch_attr gsw_vlan[] = {
2593 +};
2594 +
2595 +static const struct switch_dev_ops gsw_ops = {
2596 + .attr_global = {
2597 + .attr = gsw_global,
2598 + .n_attr = ARRAY_SIZE(gsw_global),
2599 + },
2600 + .attr_port = {
2601 + .attr = gsw_port,
2602 + .n_attr = ARRAY_SIZE(gsw_port),
2603 + },
2604 + .attr_vlan = {
2605 + .attr = gsw_vlan,
2606 + .n_attr = ARRAY_SIZE(gsw_vlan),
2607 + },
2608 + .get_vlan_ports = gsw_get_vlan_ports,
2609 + .set_vlan_ports = gsw_set_vlan_ports,
2610 + .get_port_pvid = gsw_get_port_pvid,
2611 + .set_port_pvid = gsw_set_port_pvid,
2612 + .get_port_link = gsw_get_port_link,
2613 + .apply_config = gsw_apply_config,
2614 + .reset_switch = gsw_reset_switch,
2615 +};
2616 +
2617 +void mt7620_set_mac(struct fe_priv *priv, unsigned char *mac)
2618 +{
2619 + struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
2620 + unsigned long flags;
2621 +
2622 + spin_lock_irqsave(&priv->page_lock, flags);
2623 + gsw_w32(gsw, (mac[0] << 8) | mac[1], GSW_REG_SMACCR1);
2624 + gsw_w32(gsw, (mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
2625 + GSW_REG_SMACCR0);
2626 + spin_unlock_irqrestore(&priv->page_lock, flags);
2627 +}
2628 +
2629 +static struct of_device_id gsw_match[] = {
2630 + { .compatible = "ralink,mt7620a-gsw" },
2631 + {}
2632 +};
2633 +
2634 +int mt7620_gsw_probe(struct fe_priv *priv)
2635 +{
2636 + struct mt7620_gsw *gsw;
2637 + struct device_node *np;
2638 + struct switch_dev *swdev;
2639 + const char *port4 = NULL;
2640 +
2641 + np = of_find_matching_node(NULL, gsw_match);
2642 + if (!np) {
2643 + dev_err(priv->device, "no gsw node found\n");
2644 + return -EINVAL;
2645 + }
2646 + np = of_node_get(np);
2647 +
2648 + gsw = devm_kzalloc(priv->device, sizeof(struct mt7620_gsw), GFP_KERNEL);
2649 + if (!gsw) {
2650 + dev_err(priv->device, "no gsw memory for private data\n");
2651 + return -ENOMEM;
2652 + }
2653 +
2654 + gsw->irq = irq_of_parse_and_map(np, 0);
2655 + if (!gsw->irq) {
2656 + dev_err(priv->device, "no gsw irq resource found\n");
2657 + return -ENOMEM;
2658 + }
2659 +
2660 + gsw->base = of_iomap(np, 0);
2661 + if (!gsw->base) {
2662 + dev_err(priv->device, "gsw ioremap failed\n");
2663 + }
2664 +
2665 + gsw->dev = priv->device;
2666 + priv->soc->swpriv = gsw;
2667 +
2668 + swdev = &gsw->swdev;
2669 + swdev->of_node = np;
2670 + swdev->name = "mt7620a-gsw";
2671 + swdev->alias = "mt7620x";
2672 + swdev->cpu_port = GSW_PORT6;
2673 + swdev->ports = GSW_NUM_PORTS;
2674 + swdev->vlans = GSW_NUM_VLANS;
2675 + swdev->ops = &gsw_ops;
2676 +
2677 + if (register_switch(swdev, NULL))
2678 + dev_err(priv->device, "register_switch failed\n");
2679 +
2680 + of_property_read_string(np, "ralink,port4", &port4);
2681 + if (port4 && !strcmp(port4, "ephy"))
2682 + gsw->port4 = PORT4_EPHY;
2683 + else if (port4 && !strcmp(port4, "gmac"))
2684 + gsw->port4 = PORT4_EXT;
2685 + else
2686 + WARN_ON(port4);
2687 +
2688 + gsw_hw_init(gsw);
2689 +
2690 + gsw_w32(gsw, ~PORT_IRQ_ST_CHG, GSW_REG_IMR);
2691 + request_irq(gsw->irq, gsw_interrupt, 0, "gsw", priv);
2692 +
2693 + return 0;
2694 +}
2695 --- /dev/null
2696 +++ b/drivers/net/ethernet/ralink/gsw_mt7620a.h
2697 @@ -0,0 +1,29 @@
2698 +/*
2699 + * This program is free software; you can redistribute it and/or modify
2700 + * it under the terms of the GNU General Public License as published by
2701 + * the Free Software Foundation; version 2 of the License
2702 + *
2703 + * This program is distributed in the hope that it will be useful,
2704 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2705 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2706 + * GNU General Public License for more details.
2707 + *
2708 + * You should have received a copy of the GNU General Public License
2709 + * along with this program; if not, write to the Free Software
2710 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
2711 + *
2712 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
2713 + */
2714 +
2715 +#ifndef _RALINK_GSW_MT7620_H__
2716 +#define _RALINK_GSW_MT7620_H__
2717 +
2718 +extern int mt7620_gsw_probe(struct fe_priv *priv);
2719 +extern void mt7620_set_mac(struct fe_priv *priv, unsigned char *mac);
2720 +extern int mt7620_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val);
2721 +extern int mt7620_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg);
2722 +extern void mt7620_mdio_link_adjust(struct fe_priv *priv, int port);
2723 +extern void mt7620_port_init(struct fe_priv *priv, struct device_node *np);
2724 +extern int mt7620a_has_carrier(struct fe_priv *priv);
2725 +
2726 +#endif
2727 --- /dev/null
2728 +++ b/drivers/net/ethernet/ralink/mdio.c
2729 @@ -0,0 +1,245 @@
2730 +/*
2731 + * This program is free software; you can redistribute it and/or modify
2732 + * it under the terms of the GNU General Public License as published by
2733 + * the Free Software Foundation; version 2 of the License
2734 + *
2735 + * This program is distributed in the hope that it will be useful,
2736 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2737 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2738 + * GNU General Public License for more details.
2739 + *
2740 + * You should have received a copy of the GNU General Public License
2741 + * along with this program; if not, write to the Free Software
2742 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
2743 + *
2744 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
2745 + */
2746 +
2747 +#include <linux/module.h>
2748 +#include <linux/kernel.h>
2749 +#include <linux/types.h>
2750 +#include <linux/dma-mapping.h>
2751 +#include <linux/init.h>
2752 +#include <linux/skbuff.h>
2753 +#include <linux/etherdevice.h>
2754 +#include <linux/ethtool.h>
2755 +#include <linux/platform_device.h>
2756 +#include <linux/phy.h>
2757 +#include <linux/of_device.h>
2758 +#include <linux/clk.h>
2759 +#include <linux/of_net.h>
2760 +#include <linux/of_mdio.h>
2761 +
2762 +#include "ralink_soc_eth.h"
2763 +#include "mdio.h"
2764 +
2765 +static int fe_mdio_reset(struct mii_bus *bus)
2766 +{
2767 + /* TODO */
2768 + return 0;
2769 +}
2770 +
2771 +static void fe_phy_link_adjust(struct net_device *dev)
2772 +{
2773 + struct fe_priv *priv = netdev_priv(dev);
2774 + unsigned long flags;
2775 + int i;
2776 +
2777 + spin_lock_irqsave(&priv->phy->lock, flags);
2778 + for (i = 0; i < 8; i++) {
2779 + if (priv->phy->phy_node[i]) {
2780 + struct phy_device *phydev = priv->phy->phy[i];
2781 + int status_change = 0;
2782 +
2783 + if (phydev->link)
2784 + if (priv->phy->duplex[i] != phydev->duplex ||
2785 + priv->phy->speed[i] != phydev->speed)
2786 + status_change = 1;
2787 +
2788 + if (phydev->link != priv->link[i])
2789 + status_change = 1;
2790 +
2791 + switch (phydev->speed) {
2792 + case SPEED_1000:
2793 + case SPEED_100:
2794 + case SPEED_10:
2795 + priv->link[i] = phydev->link;
2796 + priv->phy->duplex[i] = phydev->duplex;
2797 + priv->phy->speed[i] = phydev->speed;
2798 +
2799 + if (status_change && priv->soc->mdio_adjust_link)
2800 + priv->soc->mdio_adjust_link(priv, i);
2801 + break;
2802 + }
2803 + }
2804 + }
2805 + spin_unlock_irqrestore(&priv->phy->lock, flags);
2806 +}
2807 +
2808 +int fe_connect_phy_node(struct fe_priv *priv, struct device_node *phy_node)
2809 +{
2810 + const __be32 *_port = NULL;
2811 + struct phy_device *phydev;
2812 + int phy_mode, port;
2813 +
2814 + _port = of_get_property(phy_node, "reg", NULL);
2815 +
2816 + if (!_port || (be32_to_cpu(*_port) >= 8)) {
2817 + pr_err("%s: invalid port id\n", phy_node->name);
2818 + return -EINVAL;
2819 + }
2820 + port = be32_to_cpu(*_port);
2821 + phy_mode = of_get_phy_mode(phy_node);
2822 + if (phy_mode < 0) {
2823 + dev_err(priv->device, "incorrect phy-mode %d\n", phy_mode);
2824 + priv->phy->phy_node[port] = NULL;
2825 + return -EINVAL;
2826 + }
2827 +
2828 + phydev = of_phy_connect(priv->netdev, phy_node, fe_phy_link_adjust,
2829 + 0, phy_mode);
2830 + if (IS_ERR(phydev)) {
2831 + dev_err(priv->device, "could not connect to PHY\n");
2832 + priv->phy->phy_node[port] = NULL;
2833 + return PTR_ERR(phydev);
2834 + }
2835 +
2836 + phydev->supported &= PHY_GBIT_FEATURES;
2837 + phydev->advertising = phydev->supported;
2838 + phydev->no_auto_carrier_off = 1;
2839 +
2840 + dev_info(priv->device,
2841 + "connected port %d to PHY at %s [uid=%08x, driver=%s]\n",
2842 + port, dev_name(&phydev->dev), phydev->phy_id,
2843 + phydev->drv->name);
2844 +
2845 + priv->phy->phy[port] = phydev;
2846 + priv->link[port] = 0;
2847 +
2848 + return 0;
2849 +}
2850 +
2851 +static int fe_phy_connect(struct fe_priv *priv)
2852 +{
2853 + return 0;
2854 +}
2855 +
2856 +static void fe_phy_disconnect(struct fe_priv *priv)
2857 +{
2858 + unsigned long flags;
2859 + int i;
2860 +
2861 + for (i = 0; i < 8; i++)
2862 + if (priv->phy->phy_fixed[i]) {
2863 + spin_lock_irqsave(&priv->phy->lock, flags);
2864 + priv->link[i] = 0;
2865 + if (priv->soc->mdio_adjust_link)
2866 + priv->soc->mdio_adjust_link(priv, i);
2867 + spin_unlock_irqrestore(&priv->phy->lock, flags);
2868 + } else if (priv->phy->phy[i]) {
2869 + phy_disconnect(priv->phy->phy[i]);
2870 + }
2871 +}
2872 +
2873 +static void fe_phy_start(struct fe_priv *priv)
2874 +{
2875 + unsigned long flags;
2876 + int i;
2877 +
2878 + for (i = 0; i < 8; i++) {
2879 + if (priv->phy->phy_fixed[i]) {
2880 + spin_lock_irqsave(&priv->phy->lock, flags);
2881 + priv->link[i] = 1;
2882 + if (priv->soc->mdio_adjust_link)
2883 + priv->soc->mdio_adjust_link(priv, i);
2884 + spin_unlock_irqrestore(&priv->phy->lock, flags);
2885 + } else if (priv->phy->phy[i]) {
2886 + phy_start(priv->phy->phy[i]);
2887 + }
2888 + }
2889 +}
2890 +
2891 +static void fe_phy_stop(struct fe_priv *priv)
2892 +{
2893 + unsigned long flags;
2894 + int i;
2895 +
2896 + for (i = 0; i < 8; i++)
2897 + if (priv->phy->phy_fixed[i]) {
2898 + spin_lock_irqsave(&priv->phy->lock, flags);
2899 + priv->link[i] = 0;
2900 + if (priv->soc->mdio_adjust_link)
2901 + priv->soc->mdio_adjust_link(priv, i);
2902 + spin_unlock_irqrestore(&priv->phy->lock, flags);
2903 + } else if (priv->phy->phy[i]) {
2904 + phy_stop(priv->phy->phy[i]);
2905 + }
2906 +}
2907 +
2908 +static struct fe_phy phy_ralink = {
2909 + .connect = fe_phy_connect,
2910 + .disconnect = fe_phy_disconnect,
2911 + .start = fe_phy_start,
2912 + .stop = fe_phy_stop,
2913 +};
2914 +
2915 +int fe_mdio_init(struct fe_priv *priv)
2916 +{
2917 + struct device_node *mii_np;
2918 + int err;
2919 +
2920 + if (!priv->soc->mdio_read || !priv->soc->mdio_write)
2921 + return 0;
2922 +
2923 + spin_lock_init(&phy_ralink.lock);
2924 + priv->phy = &phy_ralink;
2925 +
2926 + mii_np = of_get_child_by_name(priv->device->of_node, "mdio-bus");
2927 + if (!mii_np) {
2928 + dev_err(priv->device, "no %s child node found", "mdio-bus");
2929 + return -ENODEV;
2930 + }
2931 +
2932 + if (!of_device_is_available(mii_np)) {
2933 + err = 0;
2934 + goto err_put_node;
2935 + }
2936 +
2937 + priv->mii_bus = mdiobus_alloc();
2938 + if (priv->mii_bus == NULL) {
2939 + err = -ENOMEM;
2940 + goto err_put_node;
2941 + }
2942 +
2943 + priv->mii_bus->name = "mdio";
2944 + priv->mii_bus->read = priv->soc->mdio_read;
2945 + priv->mii_bus->write = priv->soc->mdio_write;
2946 + priv->mii_bus->reset = fe_mdio_reset;
2947 + priv->mii_bus->irq = priv->mii_irq;
2948 + priv->mii_bus->priv = priv;
2949 + priv->mii_bus->parent = priv->device;
2950 +
2951 + snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s", mii_np->name);
2952 + err = of_mdiobus_register(priv->mii_bus, mii_np);
2953 + if (err)
2954 + goto err_free_bus;
2955 +
2956 + return 0;
2957 +
2958 +err_free_bus:
2959 + kfree(priv->mii_bus);
2960 +err_put_node:
2961 + of_node_put(mii_np);
2962 + priv->mii_bus = NULL;
2963 + return err;
2964 +}
2965 +
2966 +void fe_mdio_cleanup(struct fe_priv *priv)
2967 +{
2968 + if (!priv->mii_bus)
2969 + return;
2970 +
2971 + mdiobus_unregister(priv->mii_bus);
2972 + of_node_put(priv->mii_bus->dev.of_node);
2973 + kfree(priv->mii_bus);
2974 +}
2975 --- /dev/null
2976 +++ b/drivers/net/ethernet/ralink/mdio.h
2977 @@ -0,0 +1,29 @@
2978 +/*
2979 + * This program is free software; you can redistribute it and/or modify
2980 + * it under the terms of the GNU General Public License as published by
2981 + * the Free Software Foundation; version 2 of the License
2982 + *
2983 + * This program is distributed in the hope that it will be useful,
2984 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2985 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2986 + * GNU General Public License for more details.
2987 + *
2988 + * You should have received a copy of the GNU General Public License
2989 + * along with this program; if not, write to the Free Software
2990 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
2991 + *
2992 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
2993 + */
2994 +
2995 +#ifndef _RALINK_MDIO_H__
2996 +#define _RALINK_MDIO_H__
2997 +
2998 +#ifdef CONFIG_NET_RALINK_MDIO
2999 +extern int fe_mdio_init(struct fe_priv *priv);
3000 +extern void fe_mdio_cleanup(struct fe_priv *priv);
3001 +extern int fe_connect_phy_node(struct fe_priv *priv, struct device_node *phy_node);
3002 +#else
3003 +static inline int fe_mdio_init(struct fe_priv *priv) { return 0; }
3004 +static inline void fe_mdio_cleanup(struct fe_priv *priv) {}
3005 +#endif
3006 +#endif
3007 --- /dev/null
3008 +++ b/drivers/net/ethernet/ralink/mdio_rt2880.c
3009 @@ -0,0 +1,232 @@
3010 +/*
3011 + * This program is free software; you can redistribute it and/or modify
3012 + * it under the terms of the GNU General Public License as published by
3013 + * the Free Software Foundation; version 2 of the License
3014 + *
3015 + * This program is distributed in the hope that it will be useful,
3016 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3017 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3018 + * GNU General Public License for more details.
3019 + *
3020 + * You should have received a copy of the GNU General Public License
3021 + * along with this program; if not, write to the Free Software
3022 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
3023 + *
3024 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
3025 + */
3026 +
3027 +#include <linux/module.h>
3028 +#include <linux/kernel.h>
3029 +#include <linux/types.h>
3030 +#include <linux/dma-mapping.h>
3031 +#include <linux/init.h>
3032 +#include <linux/skbuff.h>
3033 +#include <linux/etherdevice.h>
3034 +#include <linux/ethtool.h>
3035 +#include <linux/platform_device.h>
3036 +#include <linux/phy.h>
3037 +#include <linux/of_device.h>
3038 +#include <linux/clk.h>
3039 +#include <linux/of_net.h>
3040 +#include <linux/of_mdio.h>
3041 +
3042 +#include "ralink_soc_eth.h"
3043 +#include "mdio_rt2880.h"
3044 +#include "mdio.h"
3045 +
3046 +#define FE_MDIO_RETRY 1000
3047 +
3048 +static unsigned char *rt2880_speed_str(struct fe_priv *priv)
3049 +{
3050 + switch (priv->phy->speed[0]) {
3051 + case SPEED_1000:
3052 + return "1000";
3053 + case SPEED_100:
3054 + return "100";
3055 + case SPEED_10:
3056 + return "10";
3057 + }
3058 +
3059 + return "?";
3060 +}
3061 +
3062 +void rt2880_mdio_link_adjust(struct fe_priv *priv, int port)
3063 +{
3064 + u32 mdio_cfg;
3065 +
3066 + if (!priv->link[0]) {
3067 + netif_carrier_off(priv->netdev);
3068 + netdev_info(priv->netdev, "link down\n");
3069 + return;
3070 + }
3071 +
3072 + mdio_cfg = FE_MDIO_CFG_TX_CLK_SKEW_200 |
3073 + FE_MDIO_CFG_RX_CLK_SKEW_200 |
3074 + FE_MDIO_CFG_GP1_FRC_EN;
3075 +
3076 + if (priv->phy->duplex[0] == DUPLEX_FULL)
3077 + mdio_cfg |= FE_MDIO_CFG_GP1_DUPLEX;
3078 +
3079 + if (priv->phy->tx_fc[0])
3080 + mdio_cfg |= FE_MDIO_CFG_GP1_FC_TX;
3081 +
3082 + if (priv->phy->rx_fc[0])
3083 + mdio_cfg |= FE_MDIO_CFG_GP1_FC_RX;
3084 +
3085 + switch (priv->phy->speed[0]) {
3086 + case SPEED_10:
3087 + mdio_cfg |= FE_MDIO_CFG_GP1_SPEED_10;
3088 + break;
3089 + case SPEED_100:
3090 + mdio_cfg |= FE_MDIO_CFG_GP1_SPEED_100;
3091 + break;
3092 + case SPEED_1000:
3093 + mdio_cfg |= FE_MDIO_CFG_GP1_SPEED_1000;
3094 + break;
3095 + default:
3096 + BUG();
3097 + }
3098 +
3099 + fe_w32(mdio_cfg, FE_MDIO_CFG);
3100 +
3101 + netif_carrier_on(priv->netdev);
3102 + netdev_info(priv->netdev, "link up (%sMbps/%s duplex)\n",
3103 + rt2880_speed_str(priv),
3104 + (DUPLEX_FULL == priv->phy->duplex[0]) ? "Full" : "Half");
3105 +}
3106 +
3107 +static int rt2880_mdio_wait_ready(struct fe_priv *priv)
3108 +{
3109 + int retries;
3110 +
3111 + retries = FE_MDIO_RETRY;
3112 + while (1) {
3113 + u32 t;
3114 +
3115 + t = fe_r32(FE_MDIO_ACCESS);
3116 + if ((t & (0x1 << 31)) == 0)
3117 + return 0;
3118 +
3119 + if (retries-- == 0)
3120 + break;
3121 +
3122 + udelay(1);
3123 + }
3124 +
3125 + dev_err(priv->device, "MDIO operation timed out\n");
3126 + return -ETIMEDOUT;
3127 +}
3128 +
3129 +int rt2880_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)
3130 +{
3131 + struct fe_priv *priv = bus->priv;
3132 + int err;
3133 + u32 t;
3134 +
3135 + err = rt2880_mdio_wait_ready(priv);
3136 + if (err)
3137 + return 0xffff;
3138 +
3139 + t = (phy_addr << 24) | (phy_reg << 16);
3140 + fe_w32(t, FE_MDIO_ACCESS);
3141 + t |= (1 << 31);
3142 + fe_w32(t, FE_MDIO_ACCESS);
3143 +
3144 + err = rt2880_mdio_wait_ready(priv);
3145 + if (err)
3146 + return 0xffff;
3147 +
3148 + pr_info("%s: addr=%04x, reg=%04x, value=%04x\n", __func__,
3149 + phy_addr, phy_reg, fe_r32(FE_MDIO_ACCESS) & 0xffff);
3150 +
3151 + return fe_r32(FE_MDIO_ACCESS) & 0xffff;
3152 +}
3153 +
3154 +int rt2880_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val)
3155 +{
3156 + struct fe_priv *priv = bus->priv;
3157 + int err;
3158 + u32 t;
3159 +
3160 + pr_info("%s: addr=%04x, reg=%04x, value=%04x\n", __func__,
3161 + phy_addr, phy_reg, fe_r32(FE_MDIO_ACCESS) & 0xffff);
3162 +
3163 + err = rt2880_mdio_wait_ready(priv);
3164 + if (err)
3165 + return err;
3166 +
3167 + t = (1 << 30) | (phy_addr << 24) | (phy_reg << 16) | val;
3168 + fe_w32(t, FE_MDIO_ACCESS);
3169 + t |= (1 << 31);
3170 + fe_w32(t, FE_MDIO_ACCESS);
3171 +
3172 + return rt2880_mdio_wait_ready(priv);
3173 +}
3174 +
3175 +void rt2880_port_init(struct fe_priv *priv, struct device_node *np)
3176 +{
3177 + const __be32 *id = of_get_property(np, "reg", NULL);
3178 + const __be32 *link;
3179 + int size;
3180 + int phy_mode;
3181 +
3182 + if (!id || (be32_to_cpu(*id) != 0)) {
3183 + pr_err("%s: invalid port id\n", np->name);
3184 + return;
3185 + }
3186 +
3187 + priv->phy->phy_fixed[0] = of_get_property(np, "ralink,fixed-link", &size);
3188 + if (priv->phy->phy_fixed[0] && (size != (4 * sizeof(*priv->phy->phy_fixed[0])))) {
3189 + pr_err("%s: invalid fixed link property\n", np->name);
3190 + priv->phy->phy_fixed[0] = NULL;
3191 + return;
3192 + }
3193 +
3194 + phy_mode = of_get_phy_mode(np);
3195 + switch (phy_mode) {
3196 + case PHY_INTERFACE_MODE_RGMII:
3197 + break;
3198 + case PHY_INTERFACE_MODE_MII:
3199 + break;
3200 + case PHY_INTERFACE_MODE_RMII:
3201 + break;
3202 + default:
3203 + if (!priv->phy->phy_fixed[0])
3204 + dev_err(priv->device, "port %d - invalid phy mode\n", priv->phy->speed[0]);
3205 + break;
3206 + }
3207 +
3208 + priv->phy->phy_node[0] = of_parse_phandle(np, "phy-handle", 0);
3209 + if (!priv->phy->phy_node[0] && !priv->phy->phy_fixed[0])
3210 + return;
3211 +
3212 + if (priv->phy->phy_fixed[0]) {
3213 + link = priv->phy->phy_fixed[0];
3214 + priv->phy->speed[0] = be32_to_cpup(link++);
3215 + priv->phy->duplex[0] = be32_to_cpup(link++);
3216 + priv->phy->tx_fc[0] = be32_to_cpup(link++);
3217 + priv->phy->rx_fc[0] = be32_to_cpup(link++);
3218 +
3219 + priv->link[0] = 1;
3220 + switch (priv->phy->speed[0]) {
3221 + case SPEED_10:
3222 + break;
3223 + case SPEED_100:
3224 + break;
3225 + case SPEED_1000:
3226 + break;
3227 + default:
3228 + dev_err(priv->device, "invalid link speed: %d\n", priv->phy->speed[0]);
3229 + priv->phy->phy_fixed[0] = 0;
3230 + return;
3231 + }
3232 + dev_info(priv->device, "using fixed link parameters\n");
3233 + rt2880_mdio_link_adjust(priv, 0);
3234 + return;
3235 + }
3236 + if (priv->phy->phy_node[0] && priv->mii_bus->phy_map[0]) {
3237 + fe_connect_phy_node(priv, priv->phy->phy_node[0]);
3238 + }
3239 +
3240 + return;
3241 +}
3242 --- /dev/null
3243 +++ b/drivers/net/ethernet/ralink/mdio_rt2880.h
3244 @@ -0,0 +1,26 @@
3245 +/*
3246 + * This program is free software; you can redistribute it and/or modify
3247 + * it under the terms of the GNU General Public License as published by
3248 + * the Free Software Foundation; version 2 of the License
3249 + *
3250 + * This program is distributed in the hope that it will be useful,
3251 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3252 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3253 + * GNU General Public License for more details.
3254 + *
3255 + * You should have received a copy of the GNU General Public License
3256 + * along with this program; if not, write to the Free Software
3257 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
3258 + *
3259 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
3260 + */
3261 +
3262 +#ifndef _RALINK_MDIO_RT2880_H__
3263 +#define _RALINK_MDIO_RT2880_H__
3264 +
3265 +void rt2880_mdio_link_adjust(struct fe_priv *priv, int port);
3266 +int rt2880_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg);
3267 +int rt2880_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val);
3268 +void rt2880_port_init(struct fe_priv *priv, struct device_node *np);
3269 +
3270 +#endif
3271 --- /dev/null
3272 +++ b/drivers/net/ethernet/ralink/ralink_soc_eth.c
3273 @@ -0,0 +1,735 @@
3274 +/*
3275 + * This program is free software; you can redistribute it and/or modify
3276 + * it under the terms of the GNU General Public License as published by
3277 + * the Free Software Foundation; version 2 of the License
3278 + *
3279 + * This program is distributed in the hope that it will be useful,
3280 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3281 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3282 + * GNU General Public License for more details.
3283 + *
3284 + * You should have received a copy of the GNU General Public License
3285 + * along with this program; if not, write to the Free Software
3286 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
3287 + *
3288 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
3289 + */
3290 +
3291 +#include <linux/module.h>
3292 +#include <linux/kernel.h>
3293 +#include <linux/types.h>
3294 +#include <linux/dma-mapping.h>
3295 +#include <linux/init.h>
3296 +#include <linux/skbuff.h>
3297 +#include <linux/etherdevice.h>
3298 +#include <linux/ethtool.h>
3299 +#include <linux/platform_device.h>
3300 +#include <linux/of_device.h>
3301 +#include <linux/clk.h>
3302 +#include <linux/of_net.h>
3303 +#include <linux/of_mdio.h>
3304 +#include <linux/if_vlan.h>
3305 +
3306 +#include <asm/mach-ralink/ralink_regs.h>
3307 +
3308 +#include "ralink_soc_eth.h"
3309 +#include "esw_rt3052.h"
3310 +#include "mdio.h"
3311 +
3312 +#define TX_TIMEOUT (20 * HZ / 100)
3313 +#define MAX_RX_LENGTH 1536
3314 +
3315 +static const u32 fe_reg_table_default[FE_REG_COUNT] = {
3316 + [FE_REG_PDMA_GLO_CFG] = FE_PDMA_GLO_CFG,
3317 + [FE_REG_PDMA_RST_CFG] = FE_PDMA_RST_CFG,
3318 + [FE_REG_DLY_INT_CFG] = FE_DLY_INT_CFG,
3319 + [FE_REG_TX_BASE_PTR0] = FE_TX_BASE_PTR0,
3320 + [FE_REG_TX_MAX_CNT0] = FE_TX_MAX_CNT0,
3321 + [FE_REG_TX_CTX_IDX0] = FE_TX_CTX_IDX0,
3322 + [FE_REG_RX_BASE_PTR0] = FE_RX_BASE_PTR0,
3323 + [FE_REG_RX_MAX_CNT0] = FE_RX_MAX_CNT0,
3324 + [FE_REG_RX_CALC_IDX0] = FE_RX_CALC_IDX0,
3325 + [FE_REG_FE_INT_ENABLE] = FE_FE_INT_ENABLE,
3326 + [FE_REG_FE_INT_STATUS] = FE_FE_INT_STATUS,
3327 +};
3328 +
3329 +static const u32 *fe_reg_table = fe_reg_table_default;
3330 +
3331 +static void __iomem *fe_base = 0;
3332 +
3333 +void fe_w32(u32 val, unsigned reg)
3334 +{
3335 + __raw_writel(val, fe_base + reg);
3336 +}
3337 +
3338 +u32 fe_r32(unsigned reg)
3339 +{
3340 + return __raw_readl(fe_base + reg);
3341 +}
3342 +
3343 +static inline void fe_reg_w32(u32 val, enum fe_reg reg)
3344 +{
3345 + fe_w32(val, fe_reg_table[reg]);
3346 +}
3347 +
3348 +static inline u32 fe_reg_r32(enum fe_reg reg)
3349 +{
3350 + return fe_r32(fe_reg_table[reg]);
3351 +}
3352 +
3353 +static inline void fe_int_disable(u32 mask)
3354 +{
3355 + fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE) & ~mask,
3356 + FE_REG_FE_INT_ENABLE);
3357 + /* flush write */
3358 + fe_reg_r32(FE_REG_FE_INT_ENABLE);
3359 +}
3360 +
3361 +static inline void fe_int_enable(u32 mask)
3362 +{
3363 + fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE) | mask,
3364 + FE_REG_FE_INT_ENABLE);
3365 + /* flush write */
3366 + fe_reg_r32(FE_REG_FE_INT_ENABLE);
3367 +}
3368 +
3369 +static inline void fe_hw_set_macaddr(struct fe_priv *priv, unsigned char *mac)
3370 +{
3371 + unsigned long flags;
3372 +
3373 + spin_lock_irqsave(&priv->page_lock, flags);
3374 + fe_w32((mac[0] << 8) | mac[1], FE_GDMA1_MAC_ADRH);
3375 + fe_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
3376 + FE_GDMA1_MAC_ADRL);
3377 + spin_unlock_irqrestore(&priv->page_lock, flags);
3378 +}
3379 +
3380 +static int fe_set_mac_address(struct net_device *dev, void *p)
3381 +{
3382 + int ret = eth_mac_addr(dev, p);
3383 +
3384 + if (!ret) {
3385 + struct fe_priv *priv = netdev_priv(dev);
3386 +
3387 + if (priv->soc->set_mac)
3388 + priv->soc->set_mac(priv, dev->dev_addr);
3389 + else
3390 + fe_hw_set_macaddr(priv, p);
3391 + }
3392 +
3393 + return ret;
3394 +}
3395 +
3396 +static struct sk_buff* fe_alloc_skb(struct fe_priv *priv)
3397 +{
3398 + struct sk_buff *skb;
3399 +
3400 + skb = netdev_alloc_skb(priv->netdev, MAX_RX_LENGTH + NET_IP_ALIGN);
3401 + if (!skb)
3402 + return NULL;
3403 +
3404 + skb_reserve(skb, NET_IP_ALIGN);
3405 +
3406 + return skb;
3407 +}
3408 +
3409 +static int fe_alloc_rx(struct fe_priv *priv)
3410 +{
3411 + int size = NUM_DMA_DESC * sizeof(struct fe_rx_dma);
3412 + int i;
3413 +
3414 + priv->rx_dma = dma_alloc_coherent(&priv->netdev->dev, size,
3415 + &priv->rx_phys, GFP_ATOMIC);
3416 + if (!priv->rx_dma)
3417 + return -ENOMEM;
3418 +
3419 + memset(priv->rx_dma, 0, size);
3420 +
3421 + for (i = 0; i < NUM_DMA_DESC; i++) {
3422 + priv->rx_skb[i] = fe_alloc_skb(priv);
3423 + if (!priv->rx_skb[i])
3424 + return -ENOMEM;
3425 + }
3426 +
3427 + for (i = 0; i < NUM_DMA_DESC; i++) {
3428 + dma_addr_t dma_addr = dma_map_single(&priv->netdev->dev,
3429 + priv->rx_skb[i]->data,
3430 + MAX_RX_LENGTH,
3431 + DMA_FROM_DEVICE);
3432 + priv->rx_dma[i].rxd1 = (unsigned int) dma_addr;
3433 +
3434 + if (priv->soc->rx_dma)
3435 + priv->soc->rx_dma(priv, i, MAX_RX_LENGTH);
3436 + else
3437 + priv->rx_dma[i].rxd2 = RX_DMA_LSO;
3438 + }
3439 + wmb();
3440 +
3441 + fe_reg_w32(priv->rx_phys, FE_REG_RX_BASE_PTR0);
3442 + fe_reg_w32(NUM_DMA_DESC, FE_REG_RX_MAX_CNT0);
3443 + fe_reg_w32((NUM_DMA_DESC - 1), FE_REG_RX_CALC_IDX0);
3444 + fe_reg_w32(FE_PST_DRX_IDX0, FE_REG_PDMA_RST_CFG);
3445 +
3446 + return 0;
3447 +}
3448 +
3449 +static int fe_alloc_tx(struct fe_priv *priv)
3450 +{
3451 + int size = NUM_DMA_DESC * sizeof(struct fe_tx_dma);
3452 + int i;
3453 +
3454 + priv->tx_free_idx = 0;
3455 +
3456 + priv->tx_dma = dma_alloc_coherent(&priv->netdev->dev, size,
3457 + &priv->tx_phys, GFP_ATOMIC);
3458 + if (!priv->tx_dma)
3459 + return -ENOMEM;
3460 +
3461 + memset(priv->tx_dma, 0, size);
3462 +
3463 + for (i = 0; i < NUM_DMA_DESC; i++) {
3464 + if (priv->soc->tx_dma) {
3465 + priv->soc->tx_dma(priv, i, 0);
3466 + continue;
3467 + }
3468 +
3469 + priv->tx_dma[i].txd2 = TX_DMA_LSO | TX_DMA_DONE;
3470 + priv->tx_dma[i].txd4 = TX_DMA_QN(3) | TX_DMA_PN(1);
3471 + }
3472 +
3473 + fe_reg_w32(priv->tx_phys, FE_REG_TX_BASE_PTR0);
3474 + fe_reg_w32(NUM_DMA_DESC, FE_REG_TX_MAX_CNT0);
3475 + fe_reg_w32(0, FE_REG_TX_CTX_IDX0);
3476 + fe_reg_w32(FE_PST_DTX_IDX0, FE_REG_PDMA_RST_CFG);
3477 +
3478 + return 0;
3479 +}
3480 +
3481 +static void fe_free_dma(struct fe_priv *priv)
3482 +{
3483 + int i;
3484 +
3485 + for (i = 0; i < NUM_DMA_DESC; i++) {
3486 + if (priv->rx_skb[i]) {
3487 + dma_unmap_single(&priv->netdev->dev, priv->rx_dma[i].rxd1,
3488 + MAX_RX_LENGTH, DMA_FROM_DEVICE);
3489 + dev_kfree_skb_any(priv->rx_skb[i]);
3490 + priv->rx_skb[i] = NULL;
3491 + }
3492 +
3493 + if (priv->tx_skb[i]) {
3494 + dev_kfree_skb_any(priv->tx_skb[i]);
3495 + priv->tx_skb[i] = NULL;
3496 + }
3497 + }
3498 +
3499 + if (priv->rx_dma) {
3500 + int size = NUM_DMA_DESC * sizeof(struct fe_rx_dma);
3501 + dma_free_coherent(&priv->netdev->dev, size, priv->rx_dma,
3502 + priv->rx_phys);
3503 + }
3504 +
3505 + if (priv->tx_dma) {
3506 + int size = NUM_DMA_DESC * sizeof(struct fe_tx_dma);
3507 + dma_free_coherent(&priv->netdev->dev, size, priv->tx_dma,
3508 + priv->tx_phys);
3509 + }
3510 +
3511 + netdev_reset_queue(priv->netdev);
3512 +}
3513 +
3514 +static int fe_start_xmit(struct sk_buff *skb, struct net_device *dev)
3515 +{
3516 + struct fe_priv *priv = netdev_priv(dev);
3517 + dma_addr_t mapped_addr;
3518 + u32 tx_next;
3519 + u32 tx;
3520 +
3521 + if (priv->soc->min_pkt_len) {
3522 + if (skb->len < priv->soc->min_pkt_len) {
3523 + if (skb_padto(skb, priv->soc->min_pkt_len)) {
3524 + printk(KERN_ERR
3525 + "fe_eth: skb_padto failed\n");
3526 + kfree_skb(skb);
3527 + return 0;
3528 + }
3529 + skb_put(skb, priv->soc->min_pkt_len - skb->len);
3530 + }
3531 + }
3532 +
3533 + dev->trans_start = jiffies;
3534 + mapped_addr = dma_map_single(&priv->netdev->dev, skb->data,
3535 + skb->len, DMA_TO_DEVICE);
3536 +
3537 + spin_lock(&priv->page_lock);
3538 +
3539 + tx = fe_reg_r32(FE_REG_TX_CTX_IDX0);
3540 + tx_next = (tx + 1) % NUM_DMA_DESC;
3541 +
3542 + if ((priv->tx_skb[tx]) || (priv->tx_skb[tx_next]) ||
3543 + !(priv->tx_dma[tx].txd2 & TX_DMA_DONE) ||
3544 + !(priv->tx_dma[tx_next].txd2 & TX_DMA_DONE))
3545 + {
3546 + spin_unlock(&priv->page_lock);
3547 + dev->stats.tx_dropped++;
3548 + kfree_skb(skb);
3549 +
3550 + return NETDEV_TX_OK;
3551 + }
3552 +
3553 + priv->tx_skb[tx] = skb;
3554 + priv->tx_dma[tx].txd1 = (unsigned int) mapped_addr;
3555 + wmb();
3556 + if (priv->soc->tx_dma)
3557 + priv->soc->tx_dma(priv, tx, skb->len);
3558 + else
3559 + priv->tx_dma[tx].txd2 = TX_DMA_LSO | TX_DMA_PLEN0(skb->len);
3560 +
3561 + if (skb->ip_summed == CHECKSUM_PARTIAL)
3562 + priv->tx_dma[tx].txd4 |= TX_DMA_CHKSUM;
3563 + else
3564 + priv->tx_dma[tx].txd4 &= ~TX_DMA_CHKSUM;
3565 +
3566 + priv->tx_dma[tx].txd4 &= ~0x80;
3567 +
3568 + dev->stats.tx_packets++;
3569 + dev->stats.tx_bytes += skb->len;
3570 +
3571 + fe_reg_w32(tx_next, FE_REG_TX_CTX_IDX0);
3572 + netdev_sent_queue(dev, skb->len);
3573 +
3574 + spin_unlock(&priv->page_lock);
3575 +
3576 + return NETDEV_TX_OK;
3577 +}
3578 +
3579 +static int fe_poll_rx(struct napi_struct *napi, int budget)
3580 +{
3581 + struct fe_priv *priv = container_of(napi, struct fe_priv, rx_napi);
3582 + int idx = fe_reg_r32(FE_REG_RX_CALC_IDX0);
3583 + int complete = 0;
3584 + int rx = 0;
3585 +
3586 + while ((rx < budget) && !complete) {
3587 + idx = (idx + 1) % NUM_DMA_DESC;
3588 +
3589 + if (priv->rx_dma[idx].rxd2 & RX_DMA_DONE) {
3590 + struct sk_buff *new_skb = fe_alloc_skb(priv);
3591 +
3592 + if (new_skb) {
3593 + int pktlen = RX_DMA_PLEN0(priv->rx_dma[idx].rxd2);
3594 + dma_addr_t dma_addr;
3595 +
3596 + dma_unmap_single(&priv->netdev->dev, priv->rx_dma[idx].rxd1,
3597 + MAX_RX_LENGTH, DMA_FROM_DEVICE);
3598 +
3599 + skb_put(priv->rx_skb[idx], pktlen);
3600 + priv->rx_skb[idx]->dev = priv->netdev;
3601 + priv->rx_skb[idx]->protocol = eth_type_trans(priv->rx_skb[idx], priv->netdev);
3602 + if (priv->rx_dma[idx].rxd4 & priv->soc->checksum_bit)
3603 + priv->rx_skb[idx]->ip_summed = CHECKSUM_UNNECESSARY;
3604 + else
3605 + priv->rx_skb[idx]->ip_summed = CHECKSUM_NONE;
3606 + priv->netdev->stats.rx_packets++;
3607 + priv->netdev->stats.rx_bytes += pktlen;
3608 + netif_receive_skb(priv->rx_skb[idx]);
3609 +
3610 + priv->rx_skb[idx] = new_skb;
3611 +
3612 + dma_addr = dma_map_single(&priv->netdev->dev,
3613 + new_skb->data,
3614 + MAX_RX_LENGTH,
3615 + DMA_FROM_DEVICE);
3616 + priv->rx_dma[idx].rxd1 = (unsigned int) dma_addr;
3617 + wmb();
3618 + } else {
3619 + priv->netdev->stats.rx_dropped++;
3620 + }
3621 +
3622 + if (priv->soc->rx_dma)
3623 + priv->soc->rx_dma(priv, idx, MAX_RX_LENGTH);
3624 + else
3625 + priv->rx_dma[idx].rxd2 = RX_DMA_LSO;
3626 + fe_reg_w32(idx, FE_REG_RX_CALC_IDX0);
3627 +
3628 + rx++;
3629 + } else {
3630 + complete = 1;
3631 + }
3632 + }
3633 +
3634 + if (complete) {
3635 + napi_complete(&priv->rx_napi);
3636 + fe_int_enable(priv->soc->rx_dly_int);
3637 + }
3638 +
3639 + return rx;
3640 +}
3641 +
3642 +static void fe_tx_housekeeping(unsigned long ptr)
3643 +{
3644 + struct net_device *dev = (struct net_device*)ptr;
3645 + struct fe_priv *priv = netdev_priv(dev);
3646 + unsigned int bytes_compl = 0;
3647 + unsigned int pkts_compl = 0;
3648 +
3649 + spin_lock(&priv->page_lock);
3650 + while (1) {
3651 + struct fe_tx_dma *txd;
3652 +
3653 + txd = &priv->tx_dma[priv->tx_free_idx];
3654 +
3655 + if (!(txd->txd2 & TX_DMA_DONE) || !(priv->tx_skb[priv->tx_free_idx]))
3656 + break;
3657 +
3658 + bytes_compl += priv->tx_skb[priv->tx_free_idx]->len;
3659 + pkts_compl++;
3660 +
3661 + dev_kfree_skb_irq(priv->tx_skb[priv->tx_free_idx]);
3662 + priv->tx_skb[priv->tx_free_idx] = NULL;
3663 + priv->tx_free_idx++;
3664 + if (priv->tx_free_idx >= NUM_DMA_DESC)
3665 + priv->tx_free_idx = 0;
3666 + }
3667 +
3668 + netdev_completed_queue(priv->netdev, pkts_compl, bytes_compl);
3669 + spin_unlock(&priv->page_lock);
3670 +
3671 + fe_int_enable(priv->soc->tx_dly_int);
3672 +}
3673 +
3674 +static void fe_tx_timeout(struct net_device *dev)
3675 +{
3676 + struct fe_priv *priv = netdev_priv(dev);
3677 +
3678 + tasklet_schedule(&priv->tx_tasklet);
3679 + priv->netdev->stats.tx_errors++;
3680 + netdev_err(dev, "transmit timed out, waking up the queue\n");
3681 + netif_wake_queue(dev);
3682 +}
3683 +
3684 +static irqreturn_t fe_handle_irq(int irq, void *dev)
3685 +{
3686 + struct fe_priv *priv = netdev_priv(dev);
3687 + unsigned int status;
3688 + unsigned int mask;
3689 +
3690 + status = fe_reg_r32(FE_REG_FE_INT_STATUS);
3691 + mask = fe_reg_r32(FE_REG_FE_INT_ENABLE);
3692 +
3693 + if (!(status & mask))
3694 + return IRQ_NONE;
3695 +
3696 + if (status & priv->soc->rx_dly_int) {
3697 + fe_int_disable(priv->soc->rx_dly_int);
3698 + napi_schedule(&priv->rx_napi);
3699 + }
3700 +
3701 + if (status & priv->soc->tx_dly_int) {
3702 + fe_int_disable(priv->soc->tx_dly_int);
3703 + tasklet_schedule(&priv->tx_tasklet);
3704 + }
3705 +
3706 + fe_reg_w32(status, FE_REG_FE_INT_STATUS);
3707 +
3708 + return IRQ_HANDLED;
3709 +}
3710 +
3711 +static int fe_hw_init(struct net_device *dev)
3712 +{
3713 + struct fe_priv *priv = netdev_priv(dev);
3714 + int err;
3715 +
3716 + err = devm_request_irq(priv->device, dev->irq, fe_handle_irq, 0,
3717 + dev_name(priv->device), dev);
3718 + if (err)
3719 + return err;
3720 +
3721 + err = fe_alloc_rx(priv);
3722 + if (!err)
3723 + err = fe_alloc_tx(priv);
3724 + if (err)
3725 + return err;
3726 +
3727 + if (priv->soc->set_mac)
3728 + priv->soc->set_mac(priv, dev->dev_addr);
3729 + else
3730 + fe_hw_set_macaddr(priv, dev->dev_addr);
3731 +
3732 + fe_reg_w32(FE_DELAY_INIT, FE_REG_DLY_INT_CFG);
3733 +
3734 + fe_int_disable(priv->soc->tx_dly_int | priv->soc->rx_dly_int);
3735 +
3736 + tasklet_init(&priv->tx_tasklet, fe_tx_housekeeping, (unsigned long)dev);
3737 +
3738 + if (priv->soc->fwd_config) {
3739 + priv->soc->fwd_config(priv);
3740 + } else {
3741 + unsigned long sysclk = priv->sysclk;
3742 +
3743 + if (!sysclk) {
3744 + netdev_err(dev, "unable to get clock\n");
3745 + return -EINVAL;
3746 + }
3747 +
3748 + sysclk /= FE_US_CYC_CNT_DIVISOR;
3749 + sysclk <<= FE_US_CYC_CNT_SHIFT;
3750 +
3751 + fe_w32((fe_r32(FE_FE_GLO_CFG) &
3752 + ~(FE_US_CYC_CNT_MASK << FE_US_CYC_CNT_SHIFT)) | sysclk,
3753 + FE_FE_GLO_CFG);
3754 +
3755 + fe_w32(fe_r32(FE_GDMA1_FWD_CFG) & ~0xffff, FE_GDMA1_FWD_CFG);
3756 + fe_w32(fe_r32(FE_GDMA1_FWD_CFG) | (FE_GDM1_ICS_EN | FE_GDM1_TCS_EN | FE_GDM1_UCS_EN),
3757 + FE_GDMA1_FWD_CFG);
3758 + fe_w32(fe_r32(FE_CDMA_CSG_CFG) | (FE_ICS_GEN_EN | FE_TCS_GEN_EN | FE_UCS_GEN_EN),
3759 + FE_CDMA_CSG_CFG);
3760 + fe_w32(FE_PSE_FQFC_CFG_INIT, FE_PSE_FQ_CFG);
3761 + }
3762 +
3763 + fe_w32(1, FE_FE_RST_GL);
3764 + fe_w32(0, FE_FE_RST_GL);
3765 +
3766 + return 0;
3767 +}
3768 +
3769 +static int fe_open(struct net_device *dev)
3770 +{
3771 + struct fe_priv *priv = netdev_priv(dev);
3772 + unsigned long flags;
3773 + u32 val;
3774 +
3775 + spin_lock_irqsave(&priv->page_lock, flags);
3776 + napi_enable(&priv->rx_napi);
3777 +
3778 + val = FE_TX_WB_DDONE | FE_RX_DMA_EN | FE_TX_DMA_EN;
3779 + val |= priv->soc->pdma_glo_cfg;
3780 + fe_reg_w32(val, FE_REG_PDMA_GLO_CFG);
3781 +
3782 + spin_unlock_irqrestore(&priv->page_lock, flags);
3783 +
3784 + if (priv->phy)
3785 + priv->phy->start(priv);
3786 +
3787 + if (priv->soc->has_carrier && priv->soc->has_carrier(priv))
3788 + netif_carrier_on(dev);
3789 +
3790 + netif_start_queue(dev);
3791 + fe_int_enable(priv->soc->tx_dly_int | priv->soc->rx_dly_int);
3792 +
3793 + return 0;
3794 +}
3795 +
3796 +static int fe_stop(struct net_device *dev)
3797 +{
3798 + struct fe_priv *priv = netdev_priv(dev);
3799 + unsigned long flags;
3800 +
3801 + fe_int_disable(priv->soc->tx_dly_int | priv->soc->rx_dly_int);
3802 +
3803 + netif_stop_queue(dev);
3804 +
3805 + if (priv->phy)
3806 + priv->phy->stop(priv);
3807 +
3808 + spin_lock_irqsave(&priv->page_lock, flags);
3809 + napi_disable(&priv->rx_napi);
3810 +
3811 + fe_reg_w32(fe_reg_r32(FE_REG_PDMA_GLO_CFG) &
3812 + ~(FE_TX_WB_DDONE | FE_RX_DMA_EN | FE_TX_DMA_EN),
3813 + FE_REG_PDMA_GLO_CFG);
3814 + spin_unlock_irqrestore(&priv->page_lock, flags);
3815 +
3816 + return 0;
3817 +}
3818 +
3819 +static int __init fe_init(struct net_device *dev)
3820 +{
3821 + struct fe_priv *priv = netdev_priv(dev);
3822 + struct device_node *port;
3823 + int err;
3824 +
3825 + BUG_ON(!priv->soc->reset_fe);
3826 + priv->soc->reset_fe();
3827 +
3828 + if (priv->soc->switch_init)
3829 + priv->soc->switch_init(priv);
3830 +
3831 + net_srandom(jiffies);
3832 + memcpy(dev->dev_addr, priv->soc->mac, ETH_ALEN);
3833 + of_get_mac_address_mtd(priv->device->of_node, dev->dev_addr);
3834 +
3835 + err = fe_mdio_init(priv);
3836 + if (err)
3837 + return err;
3838 +
3839 + if (priv->phy) {
3840 + err = priv->phy->connect(priv);
3841 + if (err)
3842 + goto err_mdio_cleanup;
3843 + }
3844 +
3845 + if (priv->soc->port_init)
3846 + for_each_child_of_node(priv->device->of_node, port)
3847 + if (of_device_is_compatible(port, "ralink,eth-port"))
3848 + priv->soc->port_init(priv, port);
3849 +
3850 + err = fe_hw_init(dev);
3851 + if (err)
3852 + goto err_phy_disconnect;
3853 +
3854 + return 0;
3855 +
3856 +err_phy_disconnect:
3857 + if (priv->phy)
3858 + priv->phy->disconnect(priv);
3859 +err_mdio_cleanup:
3860 + fe_mdio_cleanup(priv);
3861 +
3862 + return err;
3863 +}
3864 +
3865 +static void fe_uninit(struct net_device *dev)
3866 +{
3867 + struct fe_priv *priv = netdev_priv(dev);
3868 +
3869 + tasklet_kill(&priv->tx_tasklet);
3870 +
3871 + if (priv->phy)
3872 + priv->phy->disconnect(priv);
3873 + fe_mdio_cleanup(priv);
3874 +
3875 + fe_reg_w32(0, FE_REG_FE_INT_ENABLE);
3876 + free_irq(dev->irq, dev);
3877 +
3878 + fe_free_dma(priv);
3879 +}
3880 +
3881 +static const struct net_device_ops fe_netdev_ops = {
3882 + .ndo_init = fe_init,
3883 + .ndo_uninit = fe_uninit,
3884 + .ndo_open = fe_open,
3885 + .ndo_stop = fe_stop,
3886 + .ndo_start_xmit = fe_start_xmit,
3887 + .ndo_tx_timeout = fe_tx_timeout,
3888 + .ndo_set_mac_address = fe_set_mac_address,
3889 + .ndo_change_mtu = eth_change_mtu,
3890 + .ndo_validate_addr = eth_validate_addr,
3891 +};
3892 +
3893 +static int fe_probe(struct platform_device *pdev)
3894 +{
3895 + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3896 + const struct of_device_id *match;
3897 + struct fe_soc_data *soc = NULL;
3898 + struct net_device *netdev;
3899 + struct fe_priv *priv;
3900 + struct clk *sysclk;
3901 + int err;
3902 +
3903 + match = of_match_device(of_fe_match, &pdev->dev);
3904 + soc = (struct fe_soc_data *) match->data;
3905 + if (soc->reg_table)
3906 + fe_reg_table = soc->reg_table;
3907 +
3908 + fe_base = devm_request_and_ioremap(&pdev->dev, res);
3909 + if (!fe_base)
3910 + return -ENOMEM;
3911 +
3912 + netdev = alloc_etherdev(sizeof(struct fe_priv));
3913 + if (!netdev) {
3914 + dev_err(&pdev->dev, "alloc_etherdev failed\n");
3915 + return -ENOMEM;
3916 + }
3917 +
3918 + strcpy(netdev->name, "eth%d");
3919 + netdev->netdev_ops = &fe_netdev_ops;
3920 + netdev->base_addr = (unsigned long) fe_base;
3921 + netdev->watchdog_timeo = TX_TIMEOUT;
3922 + netdev->features |= NETIF_F_IP_CSUM | NETIF_F_RXCSUM;
3923 +
3924 + netdev->irq = platform_get_irq(pdev, 0);
3925 + if (netdev->irq < 0) {
3926 + dev_err(&pdev->dev, "no IRQ resource found\n");
3927 + kfree(netdev);
3928 + return -ENXIO;
3929 + }
3930 +
3931 + priv = netdev_priv(netdev);
3932 + memset(priv, 0, sizeof(struct fe_priv));
3933 + spin_lock_init(&priv->page_lock);
3934 +
3935 + sysclk = devm_clk_get(&pdev->dev, NULL);
3936 + if (!IS_ERR(sysclk))
3937 + priv->sysclk = clk_get_rate(sysclk);
3938 +
3939 + priv->netdev = netdev;
3940 + priv->device = &pdev->dev;
3941 + priv->soc = soc;
3942 +
3943 + err = register_netdev(netdev);
3944 + if (err) {
3945 + dev_err(&pdev->dev, "error bringing up device\n");
3946 + kfree(netdev);
3947 + return err;
3948 + }
3949 + netif_napi_add(netdev, &priv->rx_napi, fe_poll_rx, 32);
3950 +
3951 + platform_set_drvdata(pdev, netdev);
3952 +
3953 + netdev_info(netdev, "done loading\n");
3954 +
3955 + return 0;
3956 +}
3957 +
3958 +static int fe_remove(struct platform_device *pdev)
3959 +{
3960 + struct net_device *dev = platform_get_drvdata(pdev);
3961 + struct fe_priv *priv = netdev_priv(dev);
3962 +
3963 + netif_stop_queue(dev);
3964 + netif_napi_del(&priv->rx_napi);
3965 +
3966 + unregister_netdev(dev);
3967 + free_netdev(dev);
3968 +
3969 + return 0;
3970 +}
3971 +
3972 +static struct platform_driver fe_driver = {
3973 + .probe = fe_probe,
3974 + .remove = fe_remove,
3975 + .driver = {
3976 + .name = "ralink_soc_eth",
3977 + .owner = THIS_MODULE,
3978 + .of_match_table = of_fe_match,
3979 + },
3980 +};
3981 +
3982 +static int __init init_rtfe(void)
3983 +{
3984 + int ret;
3985 +
3986 + ret = rtesw_init();
3987 + if (ret)
3988 + return ret;
3989 +
3990 + ret = platform_driver_register(&fe_driver);
3991 + if (ret)
3992 + rtesw_exit();
3993 +
3994 + return ret;
3995 +}
3996 +
3997 +static void __exit exit_rtfe(void)
3998 +{
3999 + platform_driver_unregister(&fe_driver);
4000 + rtesw_exit();
4001 +}
4002 +
4003 +module_init(init_rtfe);
4004 +module_exit(exit_rtfe);
4005 +
4006 +MODULE_LICENSE("GPL");
4007 +MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
4008 +MODULE_DESCRIPTION("Ethernet driver for Ralink SoC");
4009 --- /dev/null
4010 +++ b/drivers/net/ethernet/ralink/ralink_soc_eth.h
4011 @@ -0,0 +1,374 @@
4012 +/*
4013 + * This program is free software; you can redistribute it and/or modify
4014 + * it under the terms of the GNU General Public License as published by
4015 + * the Free Software Foundation; version 2 of the License
4016 + *
4017 + * This program is distributed in the hope that it will be useful,
4018 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4019 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4020 + * GNU General Public License for more details.
4021 + *
4022 + * You should have received a copy of the GNU General Public License
4023 + * along with this program; if not, write to the Free Software
4024 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
4025 + *
4026 + * based on Ralink SDK3.3
4027 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
4028 + */
4029 +
4030 +#ifndef FE_ETH_H
4031 +#define FE_ETH_H
4032 +
4033 +#include <linux/mii.h>
4034 +#include <linux/interrupt.h>
4035 +#include <linux/netdevice.h>
4036 +#include <linux/dma-mapping.h>
4037 +#include <linux/phy.h>
4038 +
4039 +
4040 +enum fe_reg {
4041 + FE_REG_PDMA_GLO_CFG = 0,
4042 + FE_REG_PDMA_RST_CFG,
4043 + FE_REG_DLY_INT_CFG,
4044 + FE_REG_TX_BASE_PTR0,
4045 + FE_REG_TX_MAX_CNT0,
4046 + FE_REG_TX_CTX_IDX0,
4047 + FE_REG_RX_BASE_PTR0,
4048 + FE_REG_RX_MAX_CNT0,
4049 + FE_REG_RX_CALC_IDX0,
4050 + FE_REG_FE_INT_ENABLE,
4051 + FE_REG_FE_INT_STATUS,
4052 + FE_REG_FE_DMA_VID_BASE,
4053 + FE_REG_COUNT
4054 +};
4055 +
4056 +#define NUM_DMA_DESC 0x100
4057 +
4058 +#define FE_DELAY_EN_INT 0x80
4059 +#define FE_DELAY_MAX_INT 0x04
4060 +#define FE_DELAY_MAX_TOUT 0x04
4061 +#define FE_DELAY_CHAN (((FE_DELAY_EN_INT | FE_DELAY_MAX_INT) << 8) | FE_DELAY_MAX_TOUT)
4062 +#define FE_DELAY_INIT ((FE_DELAY_CHAN << 16) | FE_DELAY_CHAN)
4063 +#define FE_PSE_FQFC_CFG_INIT 0x80504000
4064 +
4065 +/* interrupt bits */
4066 +#define FE_CNT_PPE_AF BIT(31)
4067 +#define FE_CNT_GDM_AF BIT(29)
4068 +#define FE_PSE_P2_FC BIT(26)
4069 +#define FE_PSE_BUF_DROP BIT(24)
4070 +#define FE_GDM_OTHER_DROP BIT(23)
4071 +#define FE_PSE_P1_FC BIT(22)
4072 +#define FE_PSE_P0_FC BIT(21)
4073 +#define FE_PSE_FQ_EMPTY BIT(20)
4074 +#define FE_GE1_STA_CHG BIT(18)
4075 +#define FE_TX_COHERENT BIT(17)
4076 +#define FE_RX_COHERENT BIT(16)
4077 +#define FE_TX_DONE_INT3 BIT(11)
4078 +#define FE_TX_DONE_INT2 BIT(10)
4079 +#define FE_TX_DONE_INT1 BIT(9)
4080 +#define FE_TX_DONE_INT0 BIT(8)
4081 +#define FE_RX_DONE_INT0 BIT(2)
4082 +#define FE_TX_DLY_INT BIT(1)
4083 +#define FE_RX_DLY_INT BIT(0)
4084 +
4085 +#define RT5350_RX_DLY_INT BIT(30)
4086 +#define RT5350_TX_DLY_INT BIT(28)
4087 +
4088 +/* registers */
4089 +#define FE_FE_OFFSET 0x0000
4090 +#define FE_GDMA_OFFSET 0x0020
4091 +#define FE_PSE_OFFSET 0x0040
4092 +#define FE_GDMA2_OFFSET 0x0060
4093 +#define FE_CDMA_OFFSET 0x0080
4094 +#define FE_DMA_VID0 0x00a8
4095 +#define FE_PDMA_OFFSET 0x0100
4096 +#define FE_PPE_OFFSET 0x0200
4097 +#define FE_CMTABLE_OFFSET 0x0400
4098 +#define FE_POLICYTABLE_OFFSET 0x1000
4099 +
4100 +#define RT5350_PDMA_OFFSET 0x0800
4101 +#define RT5350_SDM_OFFSET 0x0c00
4102 +
4103 +#define FE_MDIO_ACCESS (FE_FE_OFFSET + 0x00)
4104 +#define FE_MDIO_CFG (FE_FE_OFFSET + 0x04)
4105 +#define FE_FE_GLO_CFG (FE_FE_OFFSET + 0x08)
4106 +#define FE_FE_RST_GL (FE_FE_OFFSET + 0x0C)
4107 +#define FE_FE_INT_STATUS (FE_FE_OFFSET + 0x10)
4108 +#define FE_FE_INT_ENABLE (FE_FE_OFFSET + 0x14)
4109 +#define FE_MDIO_CFG2 (FE_FE_OFFSET + 0x18)
4110 +#define FE_FOC_TS_T (FE_FE_OFFSET + 0x1C)
4111 +
4112 +#define FE_GDMA1_FWD_CFG (FE_GDMA_OFFSET + 0x00)
4113 +#define FE_GDMA1_SCH_CFG (FE_GDMA_OFFSET + 0x04)
4114 +#define FE_GDMA1_SHPR_CFG (FE_GDMA_OFFSET + 0x08)
4115 +#define FE_GDMA1_MAC_ADRL (FE_GDMA_OFFSET + 0x0C)
4116 +#define FE_GDMA1_MAC_ADRH (FE_GDMA_OFFSET + 0x10)
4117 +
4118 +#define FE_GDMA2_FWD_CFG (FE_GDMA2_OFFSET + 0x00)
4119 +#define FE_GDMA2_SCH_CFG (FE_GDMA2_OFFSET + 0x04)
4120 +#define FE_GDMA2_SHPR_CFG (FE_GDMA2_OFFSET + 0x08)
4121 +#define FE_GDMA2_MAC_ADRL (FE_GDMA2_OFFSET + 0x0C)
4122 +#define FE_GDMA2_MAC_ADRH (FE_GDMA2_OFFSET + 0x10)
4123 +
4124 +#define FE_PSE_FQ_CFG (FE_PSE_OFFSET + 0x00)
4125 +#define FE_CDMA_FC_CFG (FE_PSE_OFFSET + 0x04)
4126 +#define FE_GDMA1_FC_CFG (FE_PSE_OFFSET + 0x08)
4127 +#define FE_GDMA2_FC_CFG (FE_PSE_OFFSET + 0x0C)
4128 +
4129 +#define FE_CDMA_CSG_CFG (FE_CDMA_OFFSET + 0x00)
4130 +#define FE_CDMA_SCH_CFG (FE_CDMA_OFFSET + 0x04)
4131 +
4132 +#define MT7620A_GDMA_OFFSET 0x0600
4133 +#define MT7620A_GDMA1_FWD_CFG (MT7620A_GDMA_OFFSET + 0x00)
4134 +#define MT7620A_FE_GDMA1_SCH_CFG (MT7620A_GDMA_OFFSET + 0x04)
4135 +#define MT7620A_FE_GDMA1_SHPR_CFG (MT7620A_GDMA_OFFSET + 0x08)
4136 +#define MT7620A_FE_GDMA1_MAC_ADRL (MT7620A_GDMA_OFFSET + 0x0C)
4137 +#define MT7620A_FE_GDMA1_MAC_ADRH (MT7620A_GDMA_OFFSET + 0x10)
4138 +
4139 +#define RT5350_TX_BASE_PTR0 (RT5350_PDMA_OFFSET + 0x00)
4140 +#define RT5350_TX_MAX_CNT0 (RT5350_PDMA_OFFSET + 0x04)
4141 +#define RT5350_TX_CTX_IDX0 (RT5350_PDMA_OFFSET + 0x08)
4142 +#define RT5350_TX_DTX_IDX0 (RT5350_PDMA_OFFSET + 0x0C)
4143 +#define RT5350_TX_BASE_PTR1 (RT5350_PDMA_OFFSET + 0x10)
4144 +#define RT5350_TX_MAX_CNT1 (RT5350_PDMA_OFFSET + 0x14)
4145 +#define RT5350_TX_CTX_IDX1 (RT5350_PDMA_OFFSET + 0x18)
4146 +#define RT5350_TX_DTX_IDX1 (RT5350_PDMA_OFFSET + 0x1C)
4147 +#define RT5350_TX_BASE_PTR2 (RT5350_PDMA_OFFSET + 0x20)
4148 +#define RT5350_TX_MAX_CNT2 (RT5350_PDMA_OFFSET + 0x24)
4149 +#define RT5350_TX_CTX_IDX2 (RT5350_PDMA_OFFSET + 0x28)
4150 +#define RT5350_TX_DTX_IDX2 (RT5350_PDMA_OFFSET + 0x2C)
4151 +#define RT5350_TX_BASE_PTR3 (RT5350_PDMA_OFFSET + 0x30)
4152 +#define RT5350_TX_MAX_CNT3 (RT5350_PDMA_OFFSET + 0x34)
4153 +#define RT5350_TX_CTX_IDX3 (RT5350_PDMA_OFFSET + 0x38)
4154 +#define RT5350_TX_DTX_IDX3 (RT5350_PDMA_OFFSET + 0x3C)
4155 +#define RT5350_RX_BASE_PTR0 (RT5350_PDMA_OFFSET + 0x100)
4156 +#define RT5350_RX_MAX_CNT0 (RT5350_PDMA_OFFSET + 0x104)
4157 +#define RT5350_RX_CALC_IDX0 (RT5350_PDMA_OFFSET + 0x108)
4158 +#define RT5350_RX_DRX_IDX0 (RT5350_PDMA_OFFSET + 0x10C)
4159 +#define RT5350_RX_BASE_PTR1 (RT5350_PDMA_OFFSET + 0x110)
4160 +#define RT5350_RX_MAX_CNT1 (RT5350_PDMA_OFFSET + 0x114)
4161 +#define RT5350_RX_CALC_IDX1 (RT5350_PDMA_OFFSET + 0x118)
4162 +#define RT5350_RX_DRX_IDX1 (RT5350_PDMA_OFFSET + 0x11C)
4163 +#define RT5350_PDMA_GLO_CFG (RT5350_PDMA_OFFSET + 0x204)
4164 +#define RT5350_PDMA_RST_CFG (RT5350_PDMA_OFFSET + 0x208)
4165 +#define RT5350_DLY_INT_CFG (RT5350_PDMA_OFFSET + 0x20c)
4166 +#define RT5350_FE_INT_STATUS (RT5350_PDMA_OFFSET + 0x220)
4167 +#define RT5350_FE_INT_ENABLE (RT5350_PDMA_OFFSET + 0x228)
4168 +#define RT5350_PDMA_SCH_CFG (RT5350_PDMA_OFFSET + 0x280)
4169 +
4170 +#define FE_PDMA_GLO_CFG (FE_PDMA_OFFSET + 0x00)
4171 +#define FE_PDMA_RST_CFG (FE_PDMA_OFFSET + 0x04)
4172 +#define FE_PDMA_SCH_CFG (FE_PDMA_OFFSET + 0x08)
4173 +#define FE_DLY_INT_CFG (FE_PDMA_OFFSET + 0x0C)
4174 +#define FE_TX_BASE_PTR0 (FE_PDMA_OFFSET + 0x10)
4175 +#define FE_TX_MAX_CNT0 (FE_PDMA_OFFSET + 0x14)
4176 +#define FE_TX_CTX_IDX0 (FE_PDMA_OFFSET + 0x18)
4177 +#define FE_TX_DTX_IDX0 (FE_PDMA_OFFSET + 0x1C)
4178 +#define FE_TX_BASE_PTR1 (FE_PDMA_OFFSET + 0x20)
4179 +#define FE_TX_MAX_CNT1 (FE_PDMA_OFFSET + 0x24)
4180 +#define FE_TX_CTX_IDX1 (FE_PDMA_OFFSET + 0x28)
4181 +#define FE_TX_DTX_IDX1 (FE_PDMA_OFFSET + 0x2C)
4182 +#define FE_RX_BASE_PTR0 (FE_PDMA_OFFSET + 0x30)
4183 +#define FE_RX_MAX_CNT0 (FE_PDMA_OFFSET + 0x34)
4184 +#define FE_RX_CALC_IDX0 (FE_PDMA_OFFSET + 0x38)
4185 +#define FE_RX_DRX_IDX0 (FE_PDMA_OFFSET + 0x3C)
4186 +#define FE_TX_BASE_PTR2 (FE_PDMA_OFFSET + 0x40)
4187 +#define FE_TX_MAX_CNT2 (FE_PDMA_OFFSET + 0x44)
4188 +#define FE_TX_CTX_IDX2 (FE_PDMA_OFFSET + 0x48)
4189 +#define FE_TX_DTX_IDX2 (FE_PDMA_OFFSET + 0x4C)
4190 +#define FE_TX_BASE_PTR3 (FE_PDMA_OFFSET + 0x50)
4191 +#define FE_TX_MAX_CNT3 (FE_PDMA_OFFSET + 0x54)
4192 +#define FE_TX_CTX_IDX3 (FE_PDMA_OFFSET + 0x58)
4193 +#define FE_TX_DTX_IDX3 (FE_PDMA_OFFSET + 0x5C)
4194 +#define FE_RX_BASE_PTR1 (FE_PDMA_OFFSET + 0x60)
4195 +#define FE_RX_MAX_CNT1 (FE_PDMA_OFFSET + 0x64)
4196 +#define FE_RX_CALC_IDX1 (FE_PDMA_OFFSET + 0x68)
4197 +#define FE_RX_DRX_IDX1 (FE_PDMA_OFFSET + 0x6C)
4198 +
4199 +#define RT5350_SDM_CFG (RT5350_SDM_OFFSET + 0x00) //Switch DMA configuration
4200 +#define RT5350_SDM_RRING (RT5350_SDM_OFFSET + 0x04) //Switch DMA Rx Ring
4201 +#define RT5350_SDM_TRING (RT5350_SDM_OFFSET + 0x08) //Switch DMA Tx Ring
4202 +#define RT5350_SDM_MAC_ADRL (RT5350_SDM_OFFSET + 0x0C) //Switch MAC address LSB
4203 +#define RT5350_SDM_MAC_ADRH (RT5350_SDM_OFFSET + 0x10) //Switch MAC Address MSB
4204 +#define RT5350_SDM_TPCNT (RT5350_SDM_OFFSET + 0x100) //Switch DMA Tx packet count
4205 +#define RT5350_SDM_TBCNT (RT5350_SDM_OFFSET + 0x104) //Switch DMA Tx byte count
4206 +#define RT5350_SDM_RPCNT (RT5350_SDM_OFFSET + 0x108) //Switch DMA rx packet count
4207 +#define RT5350_SDM_RBCNT (RT5350_SDM_OFFSET + 0x10C) //Switch DMA rx byte count
4208 +#define RT5350_SDM_CS_ERR (RT5350_SDM_OFFSET + 0x110) //Switch DMA rx checksum error count
4209 +
4210 +#define RT5350_SDM_ICS_EN BIT(16)
4211 +#define RT5350_SDM_TCS_EN BIT(17)
4212 +#define RT5350_SDM_UCS_EN BIT(18)
4213 +
4214 +
4215 +/* MDIO_CFG register bits */
4216 +#define FE_MDIO_CFG_AUTO_POLL_EN BIT(29)
4217 +#define FE_MDIO_CFG_GP1_BP_EN BIT(16)
4218 +#define FE_MDIO_CFG_GP1_FRC_EN BIT(15)
4219 +#define FE_MDIO_CFG_GP1_SPEED_10 (0 << 13)
4220 +#define FE_MDIO_CFG_GP1_SPEED_100 (1 << 13)
4221 +#define FE_MDIO_CFG_GP1_SPEED_1000 (2 << 13)
4222 +#define FE_MDIO_CFG_GP1_DUPLEX BIT(12)
4223 +#define FE_MDIO_CFG_GP1_FC_TX BIT(11)
4224 +#define FE_MDIO_CFG_GP1_FC_RX BIT(10)
4225 +#define FE_MDIO_CFG_GP1_LNK_DWN BIT(9)
4226 +#define FE_MDIO_CFG_GP1_AN_FAIL BIT(8)
4227 +#define FE_MDIO_CFG_MDC_CLK_DIV_1 (0 << 6)
4228 +#define FE_MDIO_CFG_MDC_CLK_DIV_2 (1 << 6)
4229 +#define FE_MDIO_CFG_MDC_CLK_DIV_4 (2 << 6)
4230 +#define FE_MDIO_CFG_MDC_CLK_DIV_8 (3 << 6)
4231 +#define FE_MDIO_CFG_TURBO_MII_FREQ BIT(5)
4232 +#define FE_MDIO_CFG_TURBO_MII_MODE BIT(4)
4233 +#define FE_MDIO_CFG_RX_CLK_SKEW_0 (0 << 2)
4234 +#define FE_MDIO_CFG_RX_CLK_SKEW_200 (1 << 2)
4235 +#define FE_MDIO_CFG_RX_CLK_SKEW_400 (2 << 2)
4236 +#define FE_MDIO_CFG_RX_CLK_SKEW_INV (3 << 2)
4237 +#define FE_MDIO_CFG_TX_CLK_SKEW_0 0
4238 +#define FE_MDIO_CFG_TX_CLK_SKEW_200 1
4239 +#define FE_MDIO_CFG_TX_CLK_SKEW_400 2
4240 +#define FE_MDIO_CFG_TX_CLK_SKEW_INV 3
4241 +
4242 +/* uni-cast port */
4243 +#define FE_GDM1_ICS_EN BIT(22)
4244 +#define FE_GDM1_TCS_EN BIT(21)
4245 +#define FE_GDM1_UCS_EN BIT(20)
4246 +#define FE_GDM1_JMB_EN BIT(19)
4247 +#define FE_GDM1_STRPCRC BIT(16)
4248 +#define FE_GDM1_UFRC_P_CPU (0 << 12)
4249 +#define FE_GDM1_UFRC_P_GDMA1 (1 << 12)
4250 +#define FE_GDM1_UFRC_P_PPE (6 << 12)
4251 +
4252 +/* checksums */
4253 +#define FE_ICS_GEN_EN BIT(2)
4254 +#define FE_UCS_GEN_EN BIT(1)
4255 +#define FE_TCS_GEN_EN BIT(0)
4256 +
4257 +/* dma ring */
4258 +#define FE_PST_DRX_IDX0 BIT(16)
4259 +#define FE_PST_DTX_IDX3 BIT(3)
4260 +#define FE_PST_DTX_IDX2 BIT(2)
4261 +#define FE_PST_DTX_IDX1 BIT(1)
4262 +#define FE_PST_DTX_IDX0 BIT(0)
4263 +
4264 +#define FE_TX_WB_DDONE BIT(6)
4265 +#define FE_RX_DMA_BUSY BIT(3)
4266 +#define FE_TX_DMA_BUSY BIT(1)
4267 +#define FE_RX_DMA_EN BIT(2)
4268 +#define FE_TX_DMA_EN BIT(0)
4269 +
4270 +#define FE_PDMA_SIZE_4DWORDS (0 << 4)
4271 +#define FE_PDMA_SIZE_8DWORDS (1 << 4)
4272 +#define FE_PDMA_SIZE_16DWORDS (2 << 4)
4273 +
4274 +#define FE_US_CYC_CNT_MASK 0xff
4275 +#define FE_US_CYC_CNT_SHIFT 0x8
4276 +#define FE_US_CYC_CNT_DIVISOR 1000000
4277 +
4278 +#define RX_DMA_PLEN0(_x) (((_x) >> 16) & 0x3fff)
4279 +#define RX_DMA_LSO BIT(30)
4280 +#define RX_DMA_DONE BIT(31)
4281 +#define RX_DMA_L4VALID BIT(30)
4282 +
4283 +struct fe_rx_dma {
4284 + unsigned int rxd1;
4285 + unsigned int rxd2;
4286 + unsigned int rxd3;
4287 + unsigned int rxd4;
4288 +} __packed __aligned(4);
4289 +
4290 +#define TX_DMA_PLEN0_MASK ((0x3fff) << 16)
4291 +#define TX_DMA_PLEN0(_x) (((_x) & 0x3fff) << 16)
4292 +#define TX_DMA_LSO BIT(30)
4293 +#define TX_DMA_DONE BIT(31)
4294 +#define TX_DMA_QN(_x) ((_x) << 16)
4295 +#define TX_DMA_PN(_x) ((_x) << 24)
4296 +#define TX_DMA_QN_MASK TX_DMA_QN(0x7)
4297 +#define TX_DMA_PN_MASK TX_DMA_PN(0x7)
4298 +#define TX_DMA_CHKSUM (0x7 << 29)
4299 +
4300 +struct fe_tx_dma {
4301 + unsigned int txd1;
4302 + unsigned int txd2;
4303 + unsigned int txd3;
4304 + unsigned int txd4;
4305 +} __packed __aligned(4);
4306 +
4307 +struct fe_priv;
4308 +
4309 +struct fe_phy {
4310 + struct phy_device *phy[8];
4311 + struct device_node *phy_node[8];
4312 + const __be32 *phy_fixed[8];
4313 + int duplex[8];
4314 + int speed[8];
4315 + int tx_fc[8];
4316 + int rx_fc[8];
4317 + spinlock_t lock;
4318 +
4319 + int (*connect)(struct fe_priv *priv);
4320 + void (*disconnect)(struct fe_priv *priv);
4321 + void (*start)(struct fe_priv *priv);
4322 + void (*stop)(struct fe_priv *priv);
4323 +};
4324 +
4325 +struct fe_soc_data
4326 +{
4327 + unsigned char mac[6];
4328 + const u32 *reg_table;
4329 +
4330 + void (*reset_fe)(void);
4331 + void (*set_mac)(struct fe_priv *priv, unsigned char *mac);
4332 + void (*fwd_config)(struct fe_priv *priv);
4333 + void (*tx_dma)(struct fe_priv *priv, int idx, int len);
4334 + void (*rx_dma)(struct fe_priv *priv, int idx, int len);
4335 + int (*switch_init)(struct fe_priv *priv);
4336 + void (*port_init)(struct fe_priv *priv, struct device_node *port);
4337 + int (*has_carrier)(struct fe_priv *priv);
4338 + int (*mdio_init)(struct fe_priv *priv);
4339 + void (*mdio_cleanup)(struct fe_priv *priv);
4340 + int (*mdio_write)(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val);
4341 + int (*mdio_read)(struct mii_bus *bus, int phy_addr, int phy_reg);
4342 + void (*mdio_adjust_link)(struct fe_priv *priv, int port);
4343 +
4344 + void *swpriv;
4345 + u32 pdma_glo_cfg;
4346 + u32 rx_dly_int;
4347 + u32 tx_dly_int;
4348 + u32 checksum_bit;
4349 +
4350 + int min_pkt_len;
4351 +};
4352 +
4353 +struct fe_priv
4354 +{
4355 + spinlock_t page_lock;
4356 +
4357 + struct fe_soc_data *soc;
4358 + struct net_device *netdev;
4359 + struct device *device;
4360 + unsigned long sysclk;
4361 +
4362 + struct fe_rx_dma *rx_dma;
4363 + struct napi_struct rx_napi;
4364 + struct sk_buff *rx_skb[NUM_DMA_DESC];
4365 + dma_addr_t rx_phys;
4366 +
4367 + struct fe_tx_dma *tx_dma;
4368 + struct tasklet_struct tx_tasklet;
4369 + struct sk_buff *tx_skb[NUM_DMA_DESC];
4370 + dma_addr_t tx_phys;
4371 + unsigned int tx_free_idx;
4372 +
4373 + struct fe_phy *phy;
4374 + struct mii_bus *mii_bus;
4375 + int mii_irq[PHY_MAX_ADDR];
4376 +
4377 + int link[8];
4378 +};
4379 +
4380 +extern const struct of_device_id of_fe_match[];
4381 +
4382 +void fe_w32(u32 val, unsigned reg);
4383 +u32 fe_r32(unsigned reg);
4384 +
4385 +#endif /* FE_ETH_H */
4386 --- /dev/null
4387 +++ b/drivers/net/ethernet/ralink/soc_mt7620.c
4388 @@ -0,0 +1,111 @@
4389 +/*
4390 + * This program is free software; you can redistribute it and/or modify
4391 + * it under the terms of the GNU General Public License as published by
4392 + * the Free Software Foundation; version 2 of the License
4393 + *
4394 + * This program is distributed in the hope that it will be useful,
4395 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4396 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4397 + * GNU General Public License for more details.
4398 + *
4399 + * You should have received a copy of the GNU General Public License
4400 + * along with this program; if not, write to the Free Software
4401 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
4402 + *
4403 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
4404 + */
4405 +
4406 +#include <linux/module.h>
4407 +#include <linux/platform_device.h>
4408 +
4409 +#include <asm/mach-ralink/ralink_regs.h>
4410 +
4411 +#include "ralink_soc_eth.h"
4412 +#include "gsw_mt7620a.h"
4413 +
4414 +#define MT7620A_CDMA_CSG_CFG 0x400
4415 +#define MT7620_DMA_VID (MT7620A_CDMA_CSG_CFG | 0x30)
4416 +#define MT7620A_DMA_2B_OFFSET BIT(31)
4417 +#define MT7620A_RESET_FE BIT(21)
4418 +#define MT7620A_RESET_ESW BIT(23)
4419 +#define MT7620_L4_VALID BIT(23)
4420 +
4421 +#define SYSC_REG_RESET_CTRL 0x34
4422 +#define MAX_RX_LENGTH 1536
4423 +
4424 +#define CDMA_ICS_EN BIT(2)
4425 +#define CDMA_UCS_EN BIT(1)
4426 +#define CDMA_TCS_EN BIT(0)
4427 +
4428 +#define GDMA_ICS_EN BIT(22)
4429 +#define GDMA_TCS_EN BIT(21)
4430 +#define GDMA_UCS_EN BIT(20)
4431 +
4432 +static const u32 rt5350_reg_table[FE_REG_COUNT] = {
4433 + [FE_REG_PDMA_GLO_CFG] = RT5350_PDMA_GLO_CFG,
4434 + [FE_REG_PDMA_RST_CFG] = RT5350_PDMA_RST_CFG,
4435 + [FE_REG_DLY_INT_CFG] = RT5350_DLY_INT_CFG,
4436 + [FE_REG_TX_BASE_PTR0] = RT5350_TX_BASE_PTR0,
4437 + [FE_REG_TX_MAX_CNT0] = RT5350_TX_MAX_CNT0,
4438 + [FE_REG_TX_CTX_IDX0] = RT5350_TX_CTX_IDX0,
4439 + [FE_REG_RX_BASE_PTR0] = RT5350_RX_BASE_PTR0,
4440 + [FE_REG_RX_MAX_CNT0] = RT5350_RX_MAX_CNT0,
4441 + [FE_REG_RX_CALC_IDX0] = RT5350_RX_CALC_IDX0,
4442 + [FE_REG_FE_INT_ENABLE] = RT5350_FE_INT_ENABLE,
4443 + [FE_REG_FE_INT_STATUS] = RT5350_FE_INT_STATUS,
4444 + [FE_REG_FE_DMA_VID_BASE] = MT7620_DMA_VID,
4445 +};
4446 +
4447 +static void mt7620_fe_reset(void)
4448 +{
4449 + rt_sysc_w32(MT7620A_RESET_FE | MT7620A_RESET_ESW, SYSC_REG_RESET_CTRL);
4450 + rt_sysc_w32(0, SYSC_REG_RESET_CTRL);
4451 +}
4452 +
4453 +static void mt7620_fwd_config(struct fe_priv *priv)
4454 +{
4455 + fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) & ~7, MT7620A_GDMA1_FWD_CFG);
4456 + fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) | (GDMA_ICS_EN | GDMA_TCS_EN | GDMA_UCS_EN), MT7620A_GDMA1_FWD_CFG);
4457 + fe_w32(fe_r32(MT7620A_CDMA_CSG_CFG) | (CDMA_ICS_EN | CDMA_UCS_EN | CDMA_TCS_EN), MT7620A_CDMA_CSG_CFG);
4458 +}
4459 +
4460 +static void mt7620_tx_dma(struct fe_priv *priv, int idx, int len)
4461 +{
4462 + if (len)
4463 + priv->tx_dma[idx].txd2 = TX_DMA_LSO | TX_DMA_PLEN0(len);
4464 + else
4465 + priv->tx_dma[idx].txd2 = TX_DMA_LSO | TX_DMA_DONE;
4466 +}
4467 +
4468 +static void mt7620_rx_dma(struct fe_priv *priv, int idx, int len)
4469 +{
4470 + priv->rx_dma[idx].rxd2 = RX_DMA_PLEN0(len);
4471 +}
4472 +
4473 +static struct fe_soc_data mt7620_data = {
4474 + .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
4475 + .reset_fe = mt7620_fe_reset,
4476 + .set_mac = mt7620_set_mac,
4477 + .fwd_config = mt7620_fwd_config,
4478 + .tx_dma = mt7620_tx_dma,
4479 + .rx_dma = mt7620_rx_dma,
4480 + .switch_init = mt7620_gsw_probe,
4481 + .port_init = mt7620_port_init,
4482 + .min_pkt_len = 0,
4483 + .reg_table = rt5350_reg_table,
4484 + .pdma_glo_cfg = FE_PDMA_SIZE_16DWORDS | MT7620A_DMA_2B_OFFSET,
4485 + .rx_dly_int = RT5350_RX_DLY_INT,
4486 + .tx_dly_int = RT5350_TX_DLY_INT,
4487 + .checksum_bit = MT7620_L4_VALID,
4488 + .has_carrier = mt7620a_has_carrier,
4489 + .mdio_read = mt7620_mdio_read,
4490 + .mdio_write = mt7620_mdio_write,
4491 + .mdio_adjust_link = mt7620_mdio_link_adjust,
4492 +};
4493 +
4494 +const struct of_device_id of_fe_match[] = {
4495 + { .compatible = "ralink,mt7620a-eth", .data = &mt7620_data },
4496 + {},
4497 +};
4498 +
4499 +MODULE_DEVICE_TABLE(of, of_fe_match);
4500 --- /dev/null
4501 +++ b/drivers/net/ethernet/ralink/soc_rt2880.c
4502 @@ -0,0 +1,51 @@
4503 +/*
4504 + * This program is free software; you can redistribute it and/or modify
4505 + * it under the terms of the GNU General Public License as published by
4506 + * the Free Software Foundation; version 2 of the License
4507 + *
4508 + * This program is distributed in the hope that it will be useful,
4509 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4510 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4511 + * GNU General Public License for more details.
4512 + *
4513 + * You should have received a copy of the GNU General Public License
4514 + * along with this program; if not, write to the Free Software
4515 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
4516 + *
4517 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
4518 + */
4519 +
4520 +#include <linux/module.h>
4521 +
4522 +#include <asm/mach-ralink/ralink_regs.h>
4523 +
4524 +#include "ralink_soc_eth.h"
4525 +#include "mdio_rt2880.h"
4526 +
4527 +#define SYSC_REG_RESET_CTRL 0x034
4528 +#define RT2880_RESET_FE BIT(18)
4529 +
4530 +void rt2880_fe_reset(void)
4531 +{
4532 + rt_sysc_w32(RT2880_RESET_FE, SYSC_REG_RESET_CTRL);
4533 +}
4534 +
4535 +struct fe_soc_data rt2880_data = {
4536 + .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
4537 + .reset_fe = rt2880_fe_reset,
4538 + .min_pkt_len = 64,
4539 + .pdma_glo_cfg = FE_PDMA_SIZE_4DWORDS,
4540 + .checksum_bit = RX_DMA_L4VALID,
4541 + .rx_dly_int = FE_RX_DLY_INT,
4542 + .tx_dly_int = FE_TX_DLY_INT,
4543 + .mdio_read = rt2880_mdio_read,
4544 + .mdio_write = rt2880_mdio_write,
4545 + .mdio_adjust_link = rt2880_mdio_link_adjust,
4546 +};
4547 +
4548 +const struct of_device_id of_fe_match[] = {
4549 + { .compatible = "ralink,rt2880-eth", .data = &rt2880_data },
4550 + {},
4551 +};
4552 +
4553 +MODULE_DEVICE_TABLE(of, of_fe_match);
4554 --- /dev/null
4555 +++ b/drivers/net/ethernet/ralink/soc_rt305x.c
4556 @@ -0,0 +1,113 @@
4557 +/*
4558 + * This program is free software; you can redistribute it and/or modify
4559 + * it under the terms of the GNU General Public License as published by
4560 + * the Free Software Foundation; version 2 of the License
4561 + *
4562 + * This program is distributed in the hope that it will be useful,
4563 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4564 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4565 + * GNU General Public License for more details.
4566 + *
4567 + * You should have received a copy of the GNU General Public License
4568 + * along with this program; if not, write to the Free Software
4569 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
4570 + *
4571 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
4572 + */
4573 +
4574 +#include <linux/module.h>
4575 +
4576 +#include <asm/mach-ralink/ralink_regs.h>
4577 +
4578 +#include "ralink_soc_eth.h"
4579 +
4580 +#define RT305X_RESET_FE BIT(21)
4581 +#define RT305X_RESET_ESW BIT(23)
4582 +#define SYSC_REG_RESET_CTRL 0x034
4583 +
4584 +static const u32 rt5350_reg_table[FE_REG_COUNT] = {
4585 + [FE_REG_PDMA_GLO_CFG] = RT5350_PDMA_GLO_CFG,
4586 + [FE_REG_PDMA_RST_CFG] = RT5350_PDMA_RST_CFG,
4587 + [FE_REG_DLY_INT_CFG] = RT5350_DLY_INT_CFG,
4588 + [FE_REG_TX_BASE_PTR0] = RT5350_TX_BASE_PTR0,
4589 + [FE_REG_TX_MAX_CNT0] = RT5350_TX_MAX_CNT0,
4590 + [FE_REG_TX_CTX_IDX0] = RT5350_TX_CTX_IDX0,
4591 + [FE_REG_RX_BASE_PTR0] = RT5350_RX_BASE_PTR0,
4592 + [FE_REG_RX_MAX_CNT0] = RT5350_RX_MAX_CNT0,
4593 + [FE_REG_RX_CALC_IDX0] = RT5350_RX_CALC_IDX0,
4594 + [FE_REG_FE_INT_ENABLE] = RT5350_FE_INT_ENABLE,
4595 + [FE_REG_FE_INT_STATUS] = RT5350_FE_INT_STATUS,
4596 + [FE_REG_FE_DMA_VID_BASE] = 0,
4597 +};
4598 +
4599 +static void rt305x_fe_reset(void)
4600 +{
4601 + rt_sysc_w32(RT305X_RESET_FE, SYSC_REG_RESET_CTRL);
4602 + rt_sysc_w32(0, SYSC_REG_RESET_CTRL);
4603 +}
4604 +
4605 +static void rt5350_set_mac(struct fe_priv *priv, unsigned char *mac)
4606 +{
4607 + unsigned long flags;
4608 +
4609 + spin_lock_irqsave(&priv->page_lock, flags);
4610 + fe_w32((mac[0] << 8) | mac[1], RT5350_SDM_MAC_ADRH);
4611 + fe_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
4612 + RT5350_SDM_MAC_ADRL);
4613 + spin_unlock_irqrestore(&priv->page_lock, flags);
4614 +}
4615 +
4616 +static void rt5350_fwd_config(struct fe_priv *priv)
4617 +{
4618 + unsigned long sysclk = priv->sysclk;
4619 +
4620 + if (sysclk) {
4621 + sysclk /= FE_US_CYC_CNT_DIVISOR;
4622 + sysclk <<= FE_US_CYC_CNT_SHIFT;
4623 +
4624 + fe_w32((fe_r32(FE_FE_GLO_CFG) &
4625 + ~(FE_US_CYC_CNT_MASK << FE_US_CYC_CNT_SHIFT)) | sysclk,
4626 + FE_FE_GLO_CFG);
4627 + }
4628 +
4629 + fe_w32(fe_r32(RT5350_SDM_CFG) & ~0xffff, RT5350_SDM_CFG);
4630 + fe_w32(fe_r32(RT5350_SDM_CFG) | RT5350_SDM_ICS_EN | RT5350_SDM_TCS_EN | RT5350_SDM_UCS_EN,
4631 + RT5350_SDM_CFG);
4632 +}
4633 +
4634 +static void rt5350_fe_reset(void)
4635 +{
4636 + rt_sysc_w32(RT305X_RESET_FE | RT305X_RESET_ESW, SYSC_REG_RESET_CTRL);
4637 + rt_sysc_w32(0, SYSC_REG_RESET_CTRL);
4638 +}
4639 +
4640 +static struct fe_soc_data rt3050_data = {
4641 + .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
4642 + .reset_fe = rt305x_fe_reset,
4643 + .min_pkt_len = 64,
4644 + .pdma_glo_cfg = FE_PDMA_SIZE_4DWORDS,
4645 + .checksum_bit = RX_DMA_L4VALID,
4646 + .rx_dly_int = FE_RX_DLY_INT,
4647 + .tx_dly_int = FE_TX_DLY_INT,
4648 +};
4649 +
4650 +static struct fe_soc_data rt5350_data = {
4651 + .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
4652 + .reg_table = rt5350_reg_table,
4653 + .reset_fe = rt5350_fe_reset,
4654 + .set_mac = rt5350_set_mac,
4655 + .fwd_config = rt5350_fwd_config,
4656 + .min_pkt_len = 64,
4657 + .pdma_glo_cfg = FE_PDMA_SIZE_4DWORDS,
4658 + .checksum_bit = RX_DMA_L4VALID,
4659 + .rx_dly_int = RT5350_RX_DLY_INT,
4660 + .tx_dly_int = RT5350_TX_DLY_INT,
4661 +};
4662 +
4663 +const struct of_device_id of_fe_match[] = {
4664 + { .compatible = "ralink,rt3050-eth", .data = &rt3050_data },
4665 + { .compatible = "ralink,rt5350-eth", .data = &rt5350_data },
4666 + {},
4667 +};
4668 +
4669 +MODULE_DEVICE_TABLE(of, of_fe_match);
4670 --- /dev/null
4671 +++ b/drivers/net/ethernet/ralink/soc_rt3883.c
4672 @@ -0,0 +1,60 @@
4673 +/*
4674 + * This program is free software; you can redistribute it and/or modify
4675 + * it under the terms of the GNU General Public License as published by
4676 + * the Free Software Foundation; version 2 of the License
4677 + *
4678 + * This program is distributed in the hope that it will be useful,
4679 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4680 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4681 + * GNU General Public License for more details.
4682 + *
4683 + * You should have received a copy of the GNU General Public License
4684 + * along with this program; if not, write to the Free Software
4685 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
4686 + *
4687 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
4688 + */
4689 +
4690 +#include <linux/module.h>
4691 +
4692 +#include <asm/mach-ralink/ralink_regs.h>
4693 +
4694 +#include "ralink_soc_eth.h"
4695 +#include "mdio_rt2880.h"
4696 +
4697 +#define RT3883_SYSC_REG_RSTCTRL 0x34
4698 +#define RT3883_RSTCTRL_FE BIT(21)
4699 +
4700 +static void rt3883_fe_reset(void)
4701 +{
4702 + u32 t;
4703 +
4704 + t = rt_sysc_r32(RT3883_SYSC_REG_RSTCTRL);
4705 + t |= RT3883_RSTCTRL_FE;
4706 + rt_sysc_w32(t , RT3883_SYSC_REG_RSTCTRL);
4707 +
4708 + t &= ~RT3883_RSTCTRL_FE;
4709 + rt_sysc_w32(t, RT3883_SYSC_REG_RSTCTRL);
4710 +}
4711 +
4712 +static struct fe_soc_data rt3883_data = {
4713 + .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
4714 + .reset_fe = rt3883_fe_reset,
4715 + .min_pkt_len = 64,
4716 + .pdma_glo_cfg = FE_PDMA_SIZE_4DWORDS,
4717 + .rx_dly_int = FE_RX_DLY_INT,
4718 + .tx_dly_int = FE_TX_DLY_INT,
4719 + .checksum_bit = RX_DMA_L4VALID,
4720 + .mdio_read = rt2880_mdio_read,
4721 + .mdio_write = rt2880_mdio_write,
4722 + .mdio_adjust_link = rt2880_mdio_link_adjust,
4723 + .port_init = rt2880_port_init,
4724 +};
4725 +
4726 +const struct of_device_id of_fe_match[] = {
4727 + { .compatible = "ralink,rt3883-eth", .data = &rt3883_data },
4728 + {},
4729 +};
4730 +
4731 +MODULE_DEVICE_TABLE(of, of_fe_match);
4732 +
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