target/linux/ramips/patches-3.10/0024-SPI-ralink-add-Ralink-SoC-spi-driver.patch

   1 From d345c53b941a3d791c26f900af6e85aa1bcaf8b6 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Mon, 22 Apr 2013 23:16:18 +0200
   4 Subject: [PATCH 24/33] SPI: ralink: add Ralink SoC spi driver
   5
   6 Add the driver needed to make SPI work on Ralink SoC.
   7
   8 Signed-off-by: John Crispin <blogic@openwrt.org>
   9 ---
  10  drivers/spi/Kconfig      |    6 +
  11  drivers/spi/Makefile     |    1 +
  12  drivers/spi/spi-ralink.c |  475 ++++++++++++++++++++++++++++++++++++++++++++++
  13  3 files changed, 482 insertions(+)
  14  create mode 100644 drivers/spi/spi-ralink.c
  15
  16 --- a/drivers/spi/Kconfig
  17 +++ b/drivers/spi/Kconfig
  18 @@ -354,6 +354,12 @@ config SPI_RSPI
  19         help
  20           SPI driver for Renesas RSPI blocks.
  21
  22 +config SPI_RALINK
  23 +       tristate "Ralink RT288x/RT305x/RT3662 SPI Controller"
  24 +       depends on (SOC_RT288X || SOC_RT305X || SOC_RT3883 || SOC_MT7620)
  25 +       help
  26 +         This selects a driver for the Ralink RT288x/RT305x SPI Controller.
  27 +
  28  config SPI_S3C24XX
  29         tristate "Samsung S3C24XX series SPI"
  30         depends on ARCH_S3C24XX
  31 --- a/drivers/spi/Makefile
  32 +++ b/drivers/spi/Makefile
  33 @@ -56,6 +56,7 @@ spi-pxa2xx-platform-$(CONFIG_SPI_PXA2XX_
  34  obj-$(CONFIG_SPI_PXA2XX)               += spi-pxa2xx-platform.o
  35  obj-$(CONFIG_SPI_PXA2XX_PCI)           += spi-pxa2xx-pci.o
  36  obj-$(CONFIG_SPI_RSPI)                 += spi-rspi.o
  37 +obj-$(CONFIG_SPI_RALINK)               += spi-ralink.o
  38  obj-$(CONFIG_SPI_S3C24XX)              += spi-s3c24xx-hw.o
  39  spi-s3c24xx-hw-y                       := spi-s3c24xx.o
  40  spi-s3c24xx-hw-$(CONFIG_SPI_S3C24XX_FIQ) += spi-s3c24xx-fiq.o
  41 --- /dev/null
  42 +++ b/drivers/spi/spi-ralink.c
  43 @@ -0,0 +1,475 @@
  44 +/*
  45 + * spi-ralink.c -- Ralink RT288x/RT305x SPI controller driver
  46 + *
  47 + * Copyright (C) 2011 Sergiy <piratfm@gmail.com>
  48 + * Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
  49 + *
  50 + * Some parts are based on spi-orion.c:
  51 + *   Author: Shadi Ammouri <shadi@marvell.com>
  52 + *   Copyright (C) 2007-2008 Marvell Ltd.
  53 + *
  54 + * This program is free software; you can redistribute it and/or modify
  55 + * it under the terms of the GNU General Public License version 2 as
  56 + * published by the Free Software Foundation.
  57 + */
  58 +
  59 +#include <linux/init.h>
  60 +#include <linux/module.h>
  61 +#include <linux/clk.h>
  62 +#include <linux/err.h>
  63 +#include <linux/delay.h>
  64 +#include <linux/io.h>
  65 +#include <linux/reset.h>
  66 +#include <linux/spi/spi.h>
  67 +#include <linux/platform_device.h>
  68 +
  69 +#define DRIVER_NAME                    "spi-ralink"
  70 +#define RALINK_NUM_CHIPSELECTS         1 /* only one slave is supported*/
  71 +#define RALINK_SPI_WAIT_RDY_MAX_LOOP   2000 /* in usec */
  72 +
  73 +#define RAMIPS_SPI_STAT                        0x00
  74 +#define RAMIPS_SPI_CFG                 0x10
  75 +#define RAMIPS_SPI_CTL                 0x14
  76 +#define RAMIPS_SPI_DATA                        0x20
  77 +
  78 +/* SPISTAT register bit field */
  79 +#define SPISTAT_BUSY                   BIT(0)
  80 +
  81 +/* SPICFG register bit field */
  82 +#define SPICFG_LSBFIRST                        0
  83 +#define SPICFG_MSBFIRST                        BIT(8)
  84 +#define SPICFG_SPICLKPOL               BIT(6)
  85 +#define SPICFG_RXCLKEDGE_FALLING       BIT(5)
  86 +#define SPICFG_TXCLKEDGE_FALLING       BIT(4)
  87 +#define SPICFG_SPICLK_PRESCALE_MASK    0x7
  88 +#define SPICFG_SPICLK_DIV2             0
  89 +#define SPICFG_SPICLK_DIV4             1
  90 +#define SPICFG_SPICLK_DIV8             2
  91 +#define SPICFG_SPICLK_DIV16            3
  92 +#define SPICFG_SPICLK_DIV32            4
  93 +#define SPICFG_SPICLK_DIV64            5
  94 +#define SPICFG_SPICLK_DIV128           6
  95 +#define SPICFG_SPICLK_DISABLE          7
  96 +
  97 +/* SPICTL register bit field */
  98 +#define SPICTL_HIZSDO                  BIT(3)
  99 +#define SPICTL_STARTWR                 BIT(2)
 100 +#define SPICTL_STARTRD                 BIT(1)
 101 +#define SPICTL_SPIENA                  BIT(0)
 102 +
 103 +#ifdef DEBUG
 104 +#define spi_debug(args...) printk(args)
 105 +#else
 106 +#define spi_debug(args...)
 107 +#endif
 108 +
 109 +struct ralink_spi {
 110 +       struct spi_master       *master;
 111 +       void __iomem            *base;
 112 +       unsigned int            sys_freq;
 113 +       unsigned int            speed;
 114 +       struct clk              *clk;
 115 +};
 116 +
 117 +static inline struct ralink_spi *spidev_to_ralink_spi(struct spi_device *spi)
 118 +{
 119 +       return spi_master_get_devdata(spi->master);
 120 +}
 121 +
 122 +static inline u32 ralink_spi_read(struct ralink_spi *rs, u32 reg)
 123 +{
 124 +       return ioread32(rs->base + reg);
 125 +}
 126 +
 127 +static inline void ralink_spi_write(struct ralink_spi *rs, u32 reg, u32 val)
 128 +{
 129 +       iowrite32(val, rs->base + reg);
 130 +}
 131 +
 132 +static inline void ralink_spi_setbits(struct ralink_spi *rs, u32 reg, u32 mask)
 133 +{
 134 +       void __iomem *addr = rs->base + reg;
 135 +       u32 val;
 136 +
 137 +       val = ioread32(addr);
 138 +       val |= mask;
 139 +       iowrite32(val, addr);
 140 +}
 141 +
 142 +static inline void ralink_spi_clrbits(struct ralink_spi *rs, u32 reg, u32 mask)
 143 +{
 144 +       void __iomem *addr = rs->base + reg;
 145 +       u32 val;
 146 +
 147 +       val = ioread32(addr);
 148 +       val &= ~mask;
 149 +       iowrite32(val, addr);
 150 +}
 151 +
 152 +static int ralink_spi_baudrate_set(struct spi_device *spi, unsigned int speed)
 153 +{
 154 +       struct ralink_spi *rs = spidev_to_ralink_spi(spi);
 155 +       u32 rate;
 156 +       u32 prescale;
 157 +       u32 reg;
 158 +
 159 +       spi_debug("%s: speed:%u\n", __func__, speed);
 160 +
 161 +       /*
 162 +        * the supported rates are: 2, 4, 8, ... 128
 163 +        * round up as we look for equal or less speed
 164 +        */
 165 +       rate = DIV_ROUND_UP(rs->sys_freq, speed);
 166 +       spi_debug("%s: rate-1:%u\n", __func__, rate);
 167 +       rate = roundup_pow_of_two(rate);
 168 +       spi_debug("%s: rate-2:%u\n", __func__, rate);
 169 +
 170 +       /* check if requested speed is too small */
 171 +       if (rate > 128)
 172 +               return -EINVAL;
 173 +
 174 +       if (rate < 2)
 175 +               rate = 2;
 176 +
 177 +       /* Convert the rate to SPI clock divisor value. */
 178 +       prescale = ilog2(rate/2);
 179 +       spi_debug("%s: prescale:%u\n", __func__, prescale);
 180 +
 181 +       reg = ralink_spi_read(rs, RAMIPS_SPI_CFG);
 182 +       reg = ((reg & ~SPICFG_SPICLK_PRESCALE_MASK) | prescale);
 183 +       ralink_spi_write(rs, RAMIPS_SPI_CFG, reg);
 184 +       rs->speed = speed;
 185 +       return 0;
 186 +}
 187 +
 188 +/*
 189 + * called only when no transfer is active on the bus
 190 + */
 191 +static int
 192 +ralink_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
 193 +{
 194 +       struct ralink_spi *rs = spidev_to_ralink_spi(spi);
 195 +       unsigned int speed = spi->max_speed_hz;
 196 +       int rc;
 197 +       unsigned int bits_per_word = 8;
 198 +
 199 +       if ((t != NULL) && t->speed_hz)
 200 +               speed = t->speed_hz;
 201 +
 202 +       if ((t != NULL) && t->bits_per_word)
 203 +               bits_per_word = t->bits_per_word;
 204 +
 205 +       if (rs->speed != speed) {
 206 +               spi_debug("%s: speed_hz:%u\n", __func__, speed);
 207 +               rc = ralink_spi_baudrate_set(spi, speed);
 208 +               if (rc)
 209 +                       return rc;
 210 +       }
 211 +
 212 +       if (bits_per_word != 8) {
 213 +               spi_debug("%s: bad bits_per_word: %u\n", __func__,
 214 +                         bits_per_word);
 215 +               return -EINVAL;
 216 +       }
 217 +
 218 +       return 0;
 219 +}
 220 +
 221 +static void ralink_spi_set_cs(struct ralink_spi *rs, int enable)
 222 +{
 223 +       if (enable)
 224 +               ralink_spi_clrbits(rs, RAMIPS_SPI_CTL, SPICTL_SPIENA);
 225 +       else
 226 +               ralink_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_SPIENA);
 227 +}
 228 +
 229 +static inline int ralink_spi_wait_till_ready(struct ralink_spi *rs)
 230 +{
 231 +       int i;
 232 +
 233 +       for (i = 0; i < RALINK_SPI_WAIT_RDY_MAX_LOOP; i++) {
 234 +               u32 status;
 235 +
 236 +               status = ralink_spi_read(rs, RAMIPS_SPI_STAT);
 237 +               if ((status & SPISTAT_BUSY) == 0)
 238 +                       return 0;
 239 +
 240 +               udelay(1);
 241 +       }
 242 +
 243 +       return -ETIMEDOUT;
 244 +}
 245 +
 246 +static unsigned int
 247 +ralink_spi_write_read(struct spi_device *spi, struct spi_transfer *xfer)
 248 +{
 249 +       struct ralink_spi *rs = spidev_to_ralink_spi(spi);
 250 +       unsigned count = 0;
 251 +       u8 *rx = xfer->rx_buf;
 252 +       const u8 *tx = xfer->tx_buf;
 253 +       int err;
 254 +
 255 +       spi_debug("%s(%d): %s %s\n", __func__, xfer->len,
 256 +                 (tx != NULL) ? "tx" : "  ",
 257 +                 (rx != NULL) ? "rx" : "  ");
 258 +
 259 +       if (tx) {
 260 +               for (count = 0; count < xfer->len; count++) {
 261 +                       ralink_spi_write(rs, RAMIPS_SPI_DATA, tx[count]);
 262 +                       ralink_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_STARTWR);
 263 +                       err = ralink_spi_wait_till_ready(rs);
 264 +                       if (err) {
 265 +                               dev_err(&spi->dev, "TX failed, err=%d\n", err);
 266 +                               goto out;
 267 +                       }
 268 +               }
 269 +       }
 270 +
 271 +       if (rx) {
 272 +               for (count = 0; count < xfer->len; count++) {
 273 +                       ralink_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_STARTRD);
 274 +                       err = ralink_spi_wait_till_ready(rs);
 275 +                       if (err) {
 276 +                               dev_err(&spi->dev, "RX failed, err=%d\n", err);
 277 +                               goto out;
 278 +                       }
 279 +                       rx[count] = (u8) ralink_spi_read(rs, RAMIPS_SPI_DATA);
 280 +               }
 281 +       }
 282 +
 283 +out:
 284 +       return count;
 285 +}
 286 +
 287 +static int ralink_spi_transfer_one_message(struct spi_master *master,
 288 +                                          struct spi_message *m)
 289 +{
 290 +       struct ralink_spi *rs = spi_master_get_devdata(master);
 291 +       struct spi_device *spi = m->spi;
 292 +       struct spi_transfer *t = NULL;
 293 +       int par_override = 0;
 294 +       int status = 0;
 295 +       int cs_active = 0;
 296 +
 297 +       /* Load defaults */
 298 +       status = ralink_spi_setup_transfer(spi, NULL);
 299 +       if (status < 0)
 300 +               goto msg_done;
 301 +
 302 +       list_for_each_entry(t, &m->transfers, transfer_list) {
 303 +               unsigned int bits_per_word = spi->bits_per_word;
 304 +
 305 +               if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
 306 +                       dev_err(&spi->dev,
 307 +                               "message rejected: invalid transfer data buffers\n");
 308 +                       status = -EIO;
 309 +                       goto msg_done;
 310 +               }
 311 +
 312 +               if (t->bits_per_word)
 313 +                       bits_per_word = t->bits_per_word;
 314 +
 315 +               if (bits_per_word != 8) {
 316 +                       dev_err(&spi->dev,
 317 +                               "message rejected: invalid transfer bits_per_word (%d bits)\n",
 318 +                               bits_per_word);
 319 +                       status = -EIO;
 320 +                       goto msg_done;
 321 +               }
 322 +
 323 +               if (t->speed_hz && t->speed_hz < (rs->sys_freq / 128)) {
 324 +                       dev_err(&spi->dev,
 325 +                               "message rejected: device min speed (%d Hz) exceeds required transfer speed (%d Hz)\n",
 326 +                               (rs->sys_freq / 128), t->speed_hz);
 327 +                       status = -EIO;
 328 +                       goto msg_done;
 329 +               }
 330 +
 331 +               if (par_override || t->speed_hz || t->bits_per_word) {
 332 +                       par_override = 1;
 333 +                       status = ralink_spi_setup_transfer(spi, t);
 334 +                       if (status < 0)
 335 +                               goto msg_done;
 336 +                       if (!t->speed_hz && !t->bits_per_word)
 337 +                               par_override = 0;
 338 +               }
 339 +
 340 +               if (!cs_active) {
 341 +                       ralink_spi_set_cs(rs, 1);
 342 +                       cs_active = 1;
 343 +               }
 344 +
 345 +               if (t->len)
 346 +                       m->actual_length += ralink_spi_write_read(spi, t);
 347 +
 348 +               if (t->delay_usecs)
 349 +                       udelay(t->delay_usecs);
 350 +
 351 +               if (t->cs_change) {
 352 +                       ralink_spi_set_cs(rs, 0);
 353 +                       cs_active = 0;
 354 +               }
 355 +       }
 356 +
 357 +msg_done:
 358 +       if (cs_active)
 359 +               ralink_spi_set_cs(rs, 0);
 360 +
 361 +       m->status = status;
 362 +       spi_finalize_current_message(master);
 363 +
 364 +       return 0;
 365 +}
 366 +
 367 +static int ralink_spi_setup(struct spi_device *spi)
 368 +{
 369 +       struct ralink_spi *rs = spidev_to_ralink_spi(spi);
 370 +
 371 +       if ((spi->max_speed_hz == 0) ||
 372 +           (spi->max_speed_hz > (rs->sys_freq / 2)))
 373 +               spi->max_speed_hz = (rs->sys_freq / 2);
 374 +
 375 +       if (spi->max_speed_hz < (rs->sys_freq / 128)) {
 376 +               dev_err(&spi->dev, "setup: requested speed is too low %d Hz\n",
 377 +                       spi->max_speed_hz);
 378 +               return -EINVAL;
 379 +       }
 380 +
 381 +       if (spi->bits_per_word != 0 && spi->bits_per_word != 8) {
 382 +               dev_err(&spi->dev,
 383 +                       "setup: requested bits per words - os wrong %d bpw\n",
 384 +                       spi->bits_per_word);
 385 +               return -EINVAL;
 386 +       }
 387 +
 388 +       if (spi->bits_per_word == 0)
 389 +               spi->bits_per_word = 8;
 390 +
 391 +       /*
 392 +        * baudrate & width will be set ralink_spi_setup_transfer
 393 +        */
 394 +       return 0;
 395 +}
 396 +
 397 +static void ralink_spi_reset(struct ralink_spi *rs)
 398 +{
 399 +       ralink_spi_write(rs, RAMIPS_SPI_CFG,
 400 +                        SPICFG_MSBFIRST | SPICFG_TXCLKEDGE_FALLING |
 401 +                        SPICFG_SPICLK_DIV16 | SPICFG_SPICLKPOL);
 402 +       ralink_spi_write(rs, RAMIPS_SPI_CTL, SPICTL_HIZSDO | SPICTL_SPIENA);
 403 +}
 404 +
 405 +static int ralink_spi_probe(struct platform_device *pdev)
 406 +{
 407 +       struct spi_master *master;
 408 +       struct ralink_spi *rs;
 409 +       struct resource *r;
 410 +       int status = 0;
 411 +
 412 +       master = spi_alloc_master(&pdev->dev, sizeof(*rs));
 413 +       if (master == NULL) {
 414 +               dev_dbg(&pdev->dev, "master allocation failed\n");
 415 +               return -ENOMEM;
 416 +       }
 417 +
 418 +       //if (pdev->id != -1)
 419 +               master->bus_num = 0;
 420 +
 421 +       /* we support only mode 0, and no options */
 422 +       master->mode_bits = 0;
 423 +
 424 +       master->setup = ralink_spi_setup;
 425 +       master->transfer_one_message = ralink_spi_transfer_one_message;
 426 +       master->num_chipselect = RALINK_NUM_CHIPSELECTS;
 427 +       master->dev.of_node = pdev->dev.of_node;
 428 +
 429 +       dev_set_drvdata(&pdev->dev, master);
 430 +
 431 +       rs = spi_master_get_devdata(master);
 432 +       rs->master = master;
 433 +
 434 +       rs->clk = clk_get(&pdev->dev, NULL);
 435 +       if (IS_ERR(rs->clk)) {
 436 +               status = PTR_ERR(rs->clk);
 437 +               dev_err(&pdev->dev, "unable to get SYS clock, err=%d\n",
 438 +                       status);
 439 +               goto out_put_master;
 440 +       }
 441 +
 442 +       status = clk_enable(rs->clk);
 443 +       if (status)
 444 +               goto out_put_clk;
 445 +
 446 +       rs->sys_freq = clk_get_rate(rs->clk);
 447 +       spi_debug("%s: sys_freq: %u\n", __func__, rs->sys_freq);
 448 +
 449 +       r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 450 +       if (r == NULL) {
 451 +               status = -ENODEV;
 452 +               goto out_disable_clk;
 453 +       }
 454 +
 455 +       rs->base = devm_request_and_ioremap(&pdev->dev, r);
 456 +       if (!rs->base) {
 457 +               status = -EADDRNOTAVAIL;
 458 +               goto out_disable_clk;
 459 +       }
 460 +
 461 +       device_reset(&pdev->dev);
 462 +
 463 +       ralink_spi_reset(rs);
 464 +
 465 +       status = spi_register_master(master);
 466 +       if (status)
 467 +               goto out_disable_clk;
 468 +
 469 +       return 0;
 470 +
 471 +out_disable_clk:
 472 +       clk_disable(rs->clk);
 473 +out_put_clk:
 474 +       clk_put(rs->clk);
 475 +out_put_master:
 476 +       spi_master_put(master);
 477 +       return status;
 478 +}
 479 +
 480 +static int ralink_spi_remove(struct platform_device *pdev)
 481 +{
 482 +       struct spi_master *master;
 483 +       struct ralink_spi *rs;
 484 +
 485 +       master = dev_get_drvdata(&pdev->dev);
 486 +       rs = spi_master_get_devdata(master);
 487 +
 488 +       clk_disable(rs->clk);
 489 +       clk_put(rs->clk);
 490 +       spi_unregister_master(master);
 491 +
 492 +       return 0;
 493 +}
 494 +
 495 +MODULE_ALIAS("platform:" DRIVER_NAME);
 496 +
 497 +static const struct of_device_id ralink_spi_match[] = {
 498 +       { .compatible = "ralink,rt2880-spi" },
 499 +       {},
 500 +};
 501 +MODULE_DEVICE_TABLE(of, ralink_spi_match);
 502 +
 503 +static struct platform_driver ralink_spi_driver = {
 504 +       .driver = {
 505 +               .name = DRIVER_NAME,
 506 +               .owner = THIS_MODULE,
 507 +               .of_match_table = ralink_spi_match,
 508 +       },
 509 +       .probe = ralink_spi_probe,
 510 +       .remove = ralink_spi_remove,
 511 +};
 512 +
 513 +module_platform_driver(ralink_spi_driver);
 514 +
 515 +MODULE_DESCRIPTION("Ralink SPI driver");
 516 +MODULE_AUTHOR("Sergiy <piratfm@gmail.com>");
 517 +MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
 518 +MODULE_LICENSE("GPL");