target/linux/ramips/patches-3.8/0115-SPI-ralink-add-Ralink-SoC-spi-driver.patch

   1 e8c5ebbd743dac63178807c0f68fe1b75680474a3 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Wed, 30 Jan 2013 17:58:15 +0100
   4 Subject: [PATCH 115/121] SPI: ralink: add Ralink SoC spi driver
   5
   6 Add the driver needed to make SPI work on Ralink SoC.
   7
   8 Signed-off-by: John Crispin <blogic@openwrt.org>
   9 ---
  10  drivers/spi/Kconfig      |    6 +
  11  drivers/spi/Makefile     |    1 +
  12  drivers/spi/spi-ralink.c |  472 ++++++++++++++++++++++++++++++++++++++++++++++
  13  3 files changed, 479 insertions(+)
  14  create mode 100644 drivers/spi/spi-ralink.c
  15
  16 diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
  17 index f80eee7..301dbad 100644
  18 --- a/drivers/spi/Kconfig
  19 +++ b/drivers/spi/Kconfig
  20 @@ -326,6 +326,12 @@ config SPI_RSPI
  21         help
  22           SPI driver for Renesas RSPI blocks.
  23
  24 +config SPI_RALINK
  25 +       tristate "Ralink RT288x/RT305x/RT3662 SPI Controller"
  26 +       depends on (SOC_RT288X || SOC_RT305X || SOC_RT3883)
  27 +       help
  28 +         This selects a driver for the Ralink RT288x/RT305x SPI Controller.
  29 +
  30  config SPI_S3C24XX
  31         tristate "Samsung S3C24XX series SPI"
  32         depends on ARCH_S3C24XX
  33 diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
  34 index e53c309..a4b3c5b 100644
  35 --- a/drivers/spi/Makefile
  36 +++ b/drivers/spi/Makefile
  37 @@ -53,6 +53,7 @@ spi-pxa2xx-platform-$(CONFIG_SPI_PXA2XX_DMA)  += spi-pxa2xx-dma.o
  38  obj-$(CONFIG_SPI_PXA2XX)               += spi-pxa2xx-platform.o
  39  obj-$(CONFIG_SPI_PXA2XX_PCI)           += spi-pxa2xx-pci.o
  40  obj-$(CONFIG_SPI_RSPI)                 += spi-rspi.o
  41 +obj-$(CONFIG_SPI_RALINK)               += spi-ralink.o
  42  obj-$(CONFIG_SPI_S3C24XX)              += spi-s3c24xx-hw.o
  43  spi-s3c24xx-hw-y                       := spi-s3c24xx.o
  44  spi-s3c24xx-hw-$(CONFIG_SPI_S3C24XX_FIQ) += spi-s3c24xx-fiq.o
  45 diff --git a/drivers/spi/spi-ralink.c b/drivers/spi/spi-ralink.c
  46 new file mode 100644
  47 index 0000000..8d89cab
  48 --- /dev/null
  49 +++ b/drivers/spi/spi-ralink.c
  50 @@ -0,0 +1,472 @@
  51 +/*
  52 + * spi-ralink.c -- Ralink RT288x/RT305x SPI controller driver
  53 + *
  54 + * Copyright (C) 2011 Sergiy <piratfm@gmail.com>
  55 + * Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
  56 + *
  57 + * Some parts are based on spi-orion.c:
  58 + *   Author: Shadi Ammouri <shadi@marvell.com>
  59 + *   Copyright (C) 2007-2008 Marvell Ltd.
  60 + *
  61 + * This program is free software; you can redistribute it and/or modify
  62 + * it under the terms of the GNU General Public License version 2 as
  63 + * published by the Free Software Foundation.
  64 + */
  65 +
  66 +#include <linux/init.h>
  67 +#include <linux/module.h>
  68 +#include <linux/clk.h>
  69 +#include <linux/err.h>
  70 +#include <linux/delay.h>
  71 +#include <linux/platform_device.h>
  72 +#include <linux/io.h>
  73 +#include <linux/spi/spi.h>
  74 +
  75 +#define DRIVER_NAME                    "spi-ralink"
  76 +#define RALINK_NUM_CHIPSELECTS         1 /* only one slave is supported*/
  77 +#define RALINK_SPI_WAIT_RDY_MAX_LOOP   2000 /* in usec */
  78 +
  79 +#define RAMIPS_SPI_STAT                        0x00
  80 +#define RAMIPS_SPI_CFG                 0x10
  81 +#define RAMIPS_SPI_CTL                 0x14
  82 +#define RAMIPS_SPI_DATA                        0x20
  83 +
  84 +/* SPISTAT register bit field */
  85 +#define SPISTAT_BUSY                   BIT(0)
  86 +
  87 +/* SPICFG register bit field */
  88 +#define SPICFG_LSBFIRST                        0
  89 +#define SPICFG_MSBFIRST                        BIT(8)
  90 +#define SPICFG_SPICLKPOL               BIT(6)
  91 +#define SPICFG_RXCLKEDGE_FALLING       BIT(5)
  92 +#define SPICFG_TXCLKEDGE_FALLING       BIT(4)
  93 +#define SPICFG_SPICLK_PRESCALE_MASK    0x7
  94 +#define SPICFG_SPICLK_DIV2             0
  95 +#define SPICFG_SPICLK_DIV4             1
  96 +#define SPICFG_SPICLK_DIV8             2
  97 +#define SPICFG_SPICLK_DIV16            3
  98 +#define SPICFG_SPICLK_DIV32            4
  99 +#define SPICFG_SPICLK_DIV64            5
 100 +#define SPICFG_SPICLK_DIV128           6
 101 +#define SPICFG_SPICLK_DISABLE          7
 102 +
 103 +/* SPICTL register bit field */
 104 +#define SPICTL_HIZSDO                  BIT(3)
 105 +#define SPICTL_STARTWR                 BIT(2)
 106 +#define SPICTL_STARTRD                 BIT(1)
 107 +#define SPICTL_SPIENA                  BIT(0)
 108 +
 109 +#ifdef DEBUG
 110 +#define spi_debug(args...) printk(args)
 111 +#else
 112 +#define spi_debug(args...)
 113 +#endif
 114 +
 115 +struct ralink_spi {
 116 +       struct spi_master       *master;
 117 +       void __iomem            *base;
 118 +       unsigned int            sys_freq;
 119 +       unsigned int            speed;
 120 +       struct clk              *clk;
 121 +};
 122 +
 123 +static inline struct ralink_spi *spidev_to_ralink_spi(struct spi_device *spi)
 124 +{
 125 +       return spi_master_get_devdata(spi->master);
 126 +}
 127 +
 128 +static inline u32 ralink_spi_read(struct ralink_spi *rs, u32 reg)
 129 +{
 130 +       return ioread32(rs->base + reg);
 131 +}
 132 +
 133 +static inline void ralink_spi_write(struct ralink_spi *rs, u32 reg, u32 val)
 134 +{
 135 +       iowrite32(val, rs->base + reg);
 136 +}
 137 +
 138 +static inline void ralink_spi_setbits(struct ralink_spi *rs, u32 reg, u32 mask)
 139 +{
 140 +       void __iomem *addr = rs->base + reg;
 141 +       u32 val;
 142 +
 143 +       val = ioread32(addr);
 144 +       val |= mask;
 145 +       iowrite32(val, addr);
 146 +}
 147 +
 148 +static inline void ralink_spi_clrbits(struct ralink_spi *rs, u32 reg, u32 mask)
 149 +{
 150 +       void __iomem *addr = rs->base + reg;
 151 +       u32 val;
 152 +
 153 +       val = ioread32(addr);
 154 +       val &= ~mask;
 155 +       iowrite32(val, addr);
 156 +}
 157 +
 158 +static int ralink_spi_baudrate_set(struct spi_device *spi, unsigned int speed)
 159 +{
 160 +       struct ralink_spi *rs = spidev_to_ralink_spi(spi);
 161 +       u32 rate;
 162 +       u32 prescale;
 163 +       u32 reg;
 164 +
 165 +       spi_debug("%s: speed:%u\n", __func__, speed);
 166 +
 167 +       /*
 168 +        * the supported rates are: 2, 4, 8, ... 128
 169 +        * round up as we look for equal or less speed
 170 +        */
 171 +       rate = DIV_ROUND_UP(rs->sys_freq, speed);
 172 +       spi_debug("%s: rate-1:%u\n", __func__, rate);
 173 +       rate = roundup_pow_of_two(rate);
 174 +       spi_debug("%s: rate-2:%u\n", __func__, rate);
 175 +
 176 +       /* check if requested speed is too small */
 177 +       if (rate > 128)
 178 +               return -EINVAL;
 179 +
 180 +       if (rate < 2)
 181 +               rate = 2;
 182 +
 183 +       /* Convert the rate to SPI clock divisor value. */
 184 +       prescale = ilog2(rate/2);
 185 +       spi_debug("%s: prescale:%u\n", __func__, prescale);
 186 +
 187 +       reg = ralink_spi_read(rs, RAMIPS_SPI_CFG);
 188 +       reg = ((reg & ~SPICFG_SPICLK_PRESCALE_MASK) | prescale);
 189 +       ralink_spi_write(rs, RAMIPS_SPI_CFG, reg);
 190 +       rs->speed = speed;
 191 +       return 0;
 192 +}
 193 +
 194 +/*
 195 + * called only when no transfer is active on the bus
 196 + */
 197 +static int
 198 +ralink_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
 199 +{
 200 +       struct ralink_spi *rs = spidev_to_ralink_spi(spi);
 201 +       unsigned int speed = spi->max_speed_hz;
 202 +       int rc;
 203 +       unsigned int bits_per_word = 8;
 204 +
 205 +       if ((t != NULL) && t->speed_hz)
 206 +               speed = t->speed_hz;
 207 +
 208 +       if ((t != NULL) && t->bits_per_word)
 209 +               bits_per_word = t->bits_per_word;
 210 +
 211 +       if (rs->speed != speed) {
 212 +               spi_debug("%s: speed_hz:%u\n", __func__, speed);
 213 +               rc = ralink_spi_baudrate_set(spi, speed);
 214 +               if (rc)
 215 +                       return rc;
 216 +       }
 217 +
 218 +       if (bits_per_word != 8) {
 219 +               spi_debug("%s: bad bits_per_word: %u\n", __func__,
 220 +                         bits_per_word);
 221 +               return -EINVAL;
 222 +       }
 223 +
 224 +       return 0;
 225 +}
 226 +
 227 +static void ralink_spi_set_cs(struct ralink_spi *rs, int enable)
 228 +{
 229 +       if (enable)
 230 +               ralink_spi_clrbits(rs, RAMIPS_SPI_CTL, SPICTL_SPIENA);
 231 +       else
 232 +               ralink_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_SPIENA);
 233 +}
 234 +
 235 +static inline int ralink_spi_wait_till_ready(struct ralink_spi *rs)
 236 +{
 237 +       int i;
 238 +
 239 +       for (i = 0; i < RALINK_SPI_WAIT_RDY_MAX_LOOP; i++) {
 240 +               u32 status;
 241 +
 242 +               status = ralink_spi_read(rs, RAMIPS_SPI_STAT);
 243 +               if ((status & SPISTAT_BUSY) == 0)
 244 +                       return 0;
 245 +
 246 +               udelay(1);
 247 +       }
 248 +
 249 +       return -ETIMEDOUT;
 250 +}
 251 +
 252 +static unsigned int
 253 +ralink_spi_write_read(struct spi_device *spi, struct spi_transfer *xfer)
 254 +{
 255 +       struct ralink_spi *rs = spidev_to_ralink_spi(spi);
 256 +       unsigned count = 0;
 257 +       u8 *rx = xfer->rx_buf;
 258 +       const u8 *tx = xfer->tx_buf;
 259 +       int err;
 260 +
 261 +       spi_debug("%s(%d): %s %s\n", __func__, xfer->len,
 262 +                 (tx != NULL) ? "tx" : "  ",
 263 +                 (rx != NULL) ? "rx" : "  ");
 264 +
 265 +       if (tx) {
 266 +               for (count = 0; count < xfer->len; count++) {
 267 +                       ralink_spi_write(rs, RAMIPS_SPI_DATA, tx[count]);
 268 +                       ralink_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_STARTWR);
 269 +                       err = ralink_spi_wait_till_ready(rs);
 270 +                       if (err) {
 271 +                               dev_err(&spi->dev, "TX failed, err=%d\n", err);
 272 +                               goto out;
 273 +                       }
 274 +               }
 275 +       }
 276 +
 277 +       if (rx) {
 278 +               for (count = 0; count < xfer->len; count++) {
 279 +                       ralink_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_STARTRD);
 280 +                       err = ralink_spi_wait_till_ready(rs);
 281 +                       if (err) {
 282 +                               dev_err(&spi->dev, "RX failed, err=%d\n", err);
 283 +                               goto out;
 284 +                       }
 285 +                       rx[count] = (u8) ralink_spi_read(rs, RAMIPS_SPI_DATA);
 286 +               }
 287 +       }
 288 +
 289 +out:
 290 +       return count;
 291 +}
 292 +
 293 +static int ralink_spi_transfer_one_message(struct spi_master *master,
 294 +                                          struct spi_message *m)
 295 +{
 296 +       struct ralink_spi *rs = spi_master_get_devdata(master);
 297 +       struct spi_device *spi = m->spi;
 298 +       struct spi_transfer *t = NULL;
 299 +       int par_override = 0;
 300 +       int status = 0;
 301 +       int cs_active = 0;
 302 +
 303 +       /* Load defaults */
 304 +       status = ralink_spi_setup_transfer(spi, NULL);
 305 +       if (status < 0)
 306 +               goto msg_done;
 307 +
 308 +       list_for_each_entry(t, &m->transfers, transfer_list) {
 309 +               unsigned int bits_per_word = spi->bits_per_word;
 310 +
 311 +               if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
 312 +                       dev_err(&spi->dev,
 313 +                               "message rejected: invalid transfer data buffers\n");
 314 +                       status = -EIO;
 315 +                       goto msg_done;
 316 +               }
 317 +
 318 +               if (t->bits_per_word)
 319 +                       bits_per_word = t->bits_per_word;
 320 +
 321 +               if (bits_per_word != 8) {
 322 +                       dev_err(&spi->dev,
 323 +                               "message rejected: invalid transfer bits_per_word (%d bits)\n",
 324 +                               bits_per_word);
 325 +                       status = -EIO;
 326 +                       goto msg_done;
 327 +               }
 328 +
 329 +               if (t->speed_hz && t->speed_hz < (rs->sys_freq / 128)) {
 330 +                       dev_err(&spi->dev,
 331 +                               "message rejected: device min speed (%d Hz) exceeds required transfer speed (%d Hz)\n",
 332 +                               (rs->sys_freq / 128), t->speed_hz);
 333 +                       status = -EIO;
 334 +                       goto msg_done;
 335 +               }
 336 +
 337 +               if (par_override || t->speed_hz || t->bits_per_word) {
 338 +                       par_override = 1;
 339 +                       status = ralink_spi_setup_transfer(spi, t);
 340 +                       if (status < 0)
 341 +                               goto msg_done;
 342 +                       if (!t->speed_hz && !t->bits_per_word)
 343 +                               par_override = 0;
 344 +               }
 345 +
 346 +               if (!cs_active) {
 347 +                       ralink_spi_set_cs(rs, 1);
 348 +                       cs_active = 1;
 349 +               }
 350 +
 351 +               if (t->len)
 352 +                       m->actual_length += ralink_spi_write_read(spi, t);
 353 +
 354 +               if (t->delay_usecs)
 355 +                       udelay(t->delay_usecs);
 356 +
 357 +               if (t->cs_change) {
 358 +                       ralink_spi_set_cs(rs, 0);
 359 +                       cs_active = 0;
 360 +               }
 361 +       }
 362 +
 363 +msg_done:
 364 +       if (cs_active)
 365 +               ralink_spi_set_cs(rs, 0);
 366 +
 367 +       m->status = status;
 368 +       spi_finalize_current_message(master);
 369 +
 370 +       return 0;
 371 +}
 372 +
 373 +static int ralink_spi_setup(struct spi_device *spi)
 374 +{
 375 +       struct ralink_spi *rs = spidev_to_ralink_spi(spi);
 376 +
 377 +       if ((spi->max_speed_hz == 0) ||
 378 +           (spi->max_speed_hz > (rs->sys_freq / 2)))
 379 +               spi->max_speed_hz = (rs->sys_freq / 2);
 380 +
 381 +       if (spi->max_speed_hz < (rs->sys_freq / 128)) {
 382 +               dev_err(&spi->dev, "setup: requested speed is too low %d Hz\n",
 383 +                       spi->max_speed_hz);
 384 +               return -EINVAL;
 385 +       }
 386 +
 387 +       if (spi->bits_per_word != 0 && spi->bits_per_word != 8) {
 388 +               dev_err(&spi->dev,
 389 +                       "setup: requested bits per words - os wrong %d bpw\n",
 390 +                       spi->bits_per_word);
 391 +               return -EINVAL;
 392 +       }
 393 +
 394 +       if (spi->bits_per_word == 0)
 395 +               spi->bits_per_word = 8;
 396 +
 397 +       /*
 398 +        * baudrate & width will be set ralink_spi_setup_transfer
 399 +        */
 400 +       return 0;
 401 +}
 402 +
 403 +static void ralink_spi_reset(struct ralink_spi *rs)
 404 +{
 405 +       ralink_spi_write(rs, RAMIPS_SPI_CFG,
 406 +                        SPICFG_MSBFIRST | SPICFG_TXCLKEDGE_FALLING |
 407 +                        SPICFG_SPICLK_DIV16 | SPICFG_SPICLKPOL);
 408 +       ralink_spi_write(rs, RAMIPS_SPI_CTL, SPICTL_HIZSDO | SPICTL_SPIENA);
 409 +}
 410 +
 411 +static int ralink_spi_probe(struct platform_device *pdev)
 412 +{
 413 +       struct spi_master *master;
 414 +       struct ralink_spi *rs;
 415 +       struct resource *r;
 416 +       int status = 0;
 417 +
 418 +       master = spi_alloc_master(&pdev->dev, sizeof(*rs));
 419 +       if (master == NULL) {
 420 +               dev_dbg(&pdev->dev, "master allocation failed\n");
 421 +               return -ENOMEM;
 422 +       }
 423 +
 424 +       //if (pdev->id != -1)
 425 +               master->bus_num = 0;
 426 +
 427 +       /* we support only mode 0, and no options */
 428 +       master->mode_bits = 0;
 429 +
 430 +       master->setup = ralink_spi_setup;
 431 +       master->transfer_one_message = ralink_spi_transfer_one_message;
 432 +       master->num_chipselect = RALINK_NUM_CHIPSELECTS;
 433 +       master->dev.of_node = pdev->dev.of_node;
 434 +
 435 +       dev_set_drvdata(&pdev->dev, master);
 436 +
 437 +       rs = spi_master_get_devdata(master);
 438 +       rs->master = master;
 439 +
 440 +       rs->clk = clk_get(&pdev->dev, NULL);
 441 +       if (IS_ERR(rs->clk)) {
 442 +               status = PTR_ERR(rs->clk);
 443 +               dev_err(&pdev->dev, "unable to get SYS clock, err=%d\n",
 444 +                       status);
 445 +               goto out_put_master;
 446 +       }
 447 +
 448 +       status = clk_enable(rs->clk);
 449 +       if (status)
 450 +               goto out_put_clk;
 451 +
 452 +       rs->sys_freq = clk_get_rate(rs->clk);
 453 +       spi_debug("%s: sys_freq: %u\n", __func__, rs->sys_freq);
 454 +
 455 +       r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 456 +       if (r == NULL) {
 457 +               status = -ENODEV;
 458 +               goto out_disable_clk;
 459 +       }
 460 +
 461 +       rs->base = devm_request_and_ioremap(&pdev->dev, r);
 462 +       if (!rs->base) {
 463 +               status = -EADDRNOTAVAIL;
 464 +               goto out_disable_clk;
 465 +       }
 466 +
 467 +       ralink_spi_reset(rs);
 468 +
 469 +       status = spi_register_master(master);
 470 +       if (status)
 471 +               goto out_disable_clk;
 472 +
 473 +       return 0;
 474 +
 475 +out_disable_clk:
 476 +       clk_disable(rs->clk);
 477 +out_put_clk:
 478 +       clk_put(rs->clk);
 479 +out_put_master:
 480 +       spi_master_put(master);
 481 +       return status;
 482 +}
 483 +
 484 +static int ralink_spi_remove(struct platform_device *pdev)
 485 +{
 486 +       struct spi_master *master;
 487 +       struct ralink_spi *rs;
 488 +
 489 +       master = dev_get_drvdata(&pdev->dev);
 490 +       rs = spi_master_get_devdata(master);
 491 +
 492 +       clk_disable(rs->clk);
 493 +       clk_put(rs->clk);
 494 +       spi_unregister_master(master);
 495 +
 496 +       return 0;
 497 +}
 498 +
 499 +MODULE_ALIAS("platform:" DRIVER_NAME);
 500 +
 501 +static const struct of_device_id ralink_spi_match[] = {
 502 +       { .compatible = "ralink,rt2880-spi" },
 503 +       {},
 504 +};
 505 +MODULE_DEVICE_TABLE(of, ralink_spi_match);
 506 +
 507 +static struct platform_driver ralink_spi_driver = {
 508 +       .driver = {
 509 +               .name = DRIVER_NAME,
 510 +               .owner = THIS_MODULE,
 511 +               .of_match_table = ralink_spi_match,
 512 +       },
 513 +       .probe = ralink_spi_probe,
 514 +       .remove = ralink_spi_remove,
 515 +};
 516 +
 517 +module_platform_driver(ralink_spi_driver);
 518 +
 519 +MODULE_DESCRIPTION("Ralink SPI driver");
 520 +MODULE_AUTHOR("Sergiy <piratfm@gmail.com>");
 521 +MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
 522 +MODULE_LICENSE("GPL");
 523 --
 524 1.7.10.4
 525