target/linux/ramips/patches-4.3/0009-PCI-MIPS-adds-mt7620a-pcie-driver.patch

   1 From 41aa7fc236fdb1f4c9b8b10df9b71f0d248cb36b Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Mon, 7 Dec 2015 17:11:12 +0100
   4 Subject: [PATCH 09/53] PCI: MIPS: adds mt7620a pcie driver
   5
   6 Signed-off-by: John Crispin <blogic@openwrt.org>
   7 ---
   8  arch/mips/include/asm/mach-ralink/mt7620.h |    1 +
   9  arch/mips/pci/Makefile                     |    1 +
  10  arch/mips/pci/pci-mt7620.c                 |  396 ++++++++++++++++++++++++++++
  11  arch/mips/ralink/Kconfig                   |    1 +
  12  4 files changed, 399 insertions(+)
  13  create mode 100644 arch/mips/pci/pci-mt7620.c
  14
  15 diff --git a/arch/mips/include/asm/mach-ralink/mt7620.h b/arch/mips/include/asm/mach-ralink/mt7620.h
  16 index 1976fb8..72e64fa 100644
  17 --- a/arch/mips/include/asm/mach-ralink/mt7620.h
  18 +++ b/arch/mips/include/asm/mach-ralink/mt7620.h
  19 @@ -19,6 +19,7 @@ enum mt762x_soc_type {
  20         MT762X_SOC_MT7620N,
  21         MT762X_SOC_MT7628AN,
  22  };
  23 +extern enum mt762x_soc_type mt762x_soc;
  24
  25  #define MT7620_SYSC_BASE               0x10000000
  26
  27 diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
  28 index 04e61c3..ccbdc90 100644
  29 --- a/arch/mips/pci/Makefile
  30 +++ b/arch/mips/pci/Makefile
  31 @@ -43,6 +43,7 @@ obj-$(CONFIG_SIBYTE_BCM1x80)  += pci-bcm1480.o pci-bcm1480ht.o
  32  obj-$(CONFIG_SNI_RM)           += fixup-sni.o ops-sni.o
  33  obj-$(CONFIG_LANTIQ)           += fixup-lantiq.o
  34  obj-$(CONFIG_PCI_LANTIQ)       += pci-lantiq.o ops-lantiq.o
  35 +obj-$(CONFIG_SOC_MT7620)       += pci-mt7620.o
  36  obj-$(CONFIG_SOC_MT7621)       += pci-mt7621.o
  37  obj-$(CONFIG_SOC_RT288X)       += pci-rt2880.o
  38  obj-$(CONFIG_SOC_RT3883)       += pci-rt3883.o
  39 diff --git a/arch/mips/pci/pci-mt7620.c b/arch/mips/pci/pci-mt7620.c
  40 new file mode 100644
  41 index 0000000..780e4e9
  42 --- /dev/null
  43 +++ b/arch/mips/pci/pci-mt7620.c
  44 @@ -0,0 +1,396 @@
  45 +/*
  46 + *  Ralink MT7620A SoC PCI support
  47 + *
  48 + *  Copyright (C) 2007-2013 Bruce Chang
  49 + *  Copyright (C) 2013 John Crispin <blogic@openwrt.org>
  50 + *
  51 + *  This program is free software; you can redistribute it and/or modify it
  52 + *  under the terms of the GNU General Public License version 2 as published
  53 + *  by the Free Software Foundation.
  54 + */
  55 +
  56 +#include <linux/types.h>
  57 +#include <linux/pci.h>
  58 +#include <linux/io.h>
  59 +#include <linux/init.h>
  60 +#include <linux/delay.h>
  61 +#include <linux/interrupt.h>
  62 +#include <linux/module.h>
  63 +#include <linux/of.h>
  64 +#include <linux/of_irq.h>
  65 +#include <linux/of_pci.h>
  66 +#include <linux/reset.h>
  67 +#include <linux/platform_device.h>
  68 +
  69 +#include <asm/mach-ralink/ralink_regs.h>
  70 +#include <asm/mach-ralink/mt7620.h>
  71 +
  72 +#define RALINK_PCI_MM_MAP_BASE         0x20000000
  73 +#define RALINK_PCI_IO_MAP_BASE         0x10160000
  74 +
  75 +#define RALINK_INT_PCIE0               4
  76 +#define RALINK_SYSCFG1                 0x14
  77 +#define RALINK_CLKCFG1                 0x30
  78 +#define RALINK_GPIOMODE                        0x60
  79 +#define RALINK_PCIE_CLK_GEN            0x7c
  80 +#define RALINK_PCIE_CLK_GEN1           0x80
  81 +#define PCIEPHY0_CFG                   0x90
  82 +#define PPLL_CFG1                      0x9c
  83 +#define PPLL_DRV                       0xa0
  84 +#define PDRV_SW_SET                    (1<<31)
  85 +#define LC_CKDRVPD_                    (1<<19)
  86 +
  87 +#define RALINK_PCI_CONFIG_ADDR         0x20
  88 +#define RALINK_PCI_CONFIG_DATA_VIRT_REG        0x24
  89 +#define MEMORY_BASE                    0x0
  90 +#define RALINK_PCIE0_RST               (1<<26)
  91 +#define RALINK_PCI_BASE                        0xB0140000
  92 +#define RALINK_PCI_MEMBASE             0x28
  93 +#define RALINK_PCI_IOBASE              0x2C
  94 +
  95 +#define RT6855_PCIE0_OFFSET            0x2000
  96 +
  97 +#define RALINK_PCI_PCICFG_ADDR         0x00
  98 +#define RALINK_PCI0_BAR0SETUP_ADDR     0x10
  99 +#define RALINK_PCI0_IMBASEBAR0_ADDR    0x18
 100 +#define RALINK_PCI0_ID                 0x30
 101 +#define RALINK_PCI0_CLASS              0x34
 102 +#define RALINK_PCI0_SUBID              0x38
 103 +#define RALINK_PCI0_STATUS             0x50
 104 +#define RALINK_PCI_PCIMSK_ADDR         0x0C
 105 +
 106 +#define RALINK_PCIEPHY_P0_CTL_OFFSET   0x7498
 107 +#define RALINK_PCIE0_CLK_EN            (1 << 26)
 108 +
 109 +#define BUSY                           0x80000000
 110 +#define WAITRETRY_MAX                  10
 111 +#define WRITE_MODE                     (1UL << 23)
 112 +#define DATA_SHIFT                     0
 113 +#define ADDR_SHIFT                     8
 114 +
 115 +static void __iomem *bridge_base;
 116 +static void __iomem *pcie_base;
 117 +
 118 +static struct reset_control *rstpcie0;
 119 +
 120 +static inline void bridge_w32(u32 val, unsigned reg)
 121 +{
 122 +       iowrite32(val, bridge_base + reg);
 123 +}
 124 +
 125 +static inline u32 bridge_r32(unsigned reg)
 126 +{
 127 +       return ioread32(bridge_base + reg);
 128 +}
 129 +
 130 +static inline void pcie_w32(u32 val, unsigned reg)
 131 +{
 132 +       iowrite32(val, pcie_base + reg);
 133 +}
 134 +
 135 +static inline u32 pcie_r32(unsigned reg)
 136 +{
 137 +       return ioread32(pcie_base + reg);
 138 +}
 139 +
 140 +static inline void pcie_m32(u32 clr, u32 set, unsigned reg)
 141 +{
 142 +       u32 val = pcie_r32(reg);
 143 +
 144 +       val &= ~clr;
 145 +       val |= set;
 146 +       pcie_w32(val, reg);
 147 +}
 148 +
 149 +static int wait_pciephy_busy(void)
 150 +{
 151 +       unsigned long reg_value = 0x0, retry = 0;
 152 +
 153 +       while (1) {
 154 +               reg_value = pcie_r32(PCIEPHY0_CFG);
 155 +
 156 +               if (reg_value & BUSY)
 157 +                       mdelay(100);
 158 +               else
 159 +                       break;
 160 +               if (retry++ > WAITRETRY_MAX){
 161 +                       printk("PCIE-PHY retry failed.\n");
 162 +                       return -1;
 163 +               }
 164 +       }
 165 +       return 0;
 166 +}
 167 +
 168 +static void pcie_phy(unsigned long addr, unsigned long val)
 169 +{
 170 +       wait_pciephy_busy();
 171 +       pcie_w32(WRITE_MODE | (val << DATA_SHIFT) | (addr << ADDR_SHIFT), PCIEPHY0_CFG);
 172 +       mdelay(1);
 173 +       wait_pciephy_busy();
 174 +}
 175 +
 176 +static int pci_config_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 * val)
 177 +{
 178 +       unsigned int slot = PCI_SLOT(devfn);
 179 +       u8 func = PCI_FUNC(devfn);
 180 +       u32 address;
 181 +       u32 data;
 182 +       u32 num = 0;
 183 +
 184 +       if (bus)
 185 +               num = bus->number;
 186 +
 187 +       address = (((where & 0xF00) >> 8) << 24) | (num << 16) | (slot << 11) | (func << 8) | (where & 0xfc) | 0x80000000;
 188 +       bridge_w32(address, RALINK_PCI_CONFIG_ADDR);
 189 +       data = bridge_r32(RALINK_PCI_CONFIG_DATA_VIRT_REG);
 190 +
 191 +       switch (size) {
 192 +       case 1:
 193 +               *val = (data >> ((where & 3) << 3)) & 0xff;
 194 +               break;
 195 +       case 2:
 196 +               *val = (data >> ((where & 3) << 3)) & 0xffff;
 197 +               break;
 198 +       case 4:
 199 +               *val = data;
 200 +               break;
 201 +       }
 202 +
 203 +       return PCIBIOS_SUCCESSFUL;
 204 +}
 205 +
 206 +static int pci_config_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val)
 207 +{
 208 +       unsigned int slot = PCI_SLOT(devfn);
 209 +       u8 func = PCI_FUNC(devfn);
 210 +       u32 address;
 211 +       u32 data;
 212 +       u32 num = 0;
 213 +
 214 +       if (bus)
 215 +               num = bus->number;
 216 +
 217 +       address = (((where & 0xF00) >> 8) << 24) | (num << 16) | (slot << 11) | (func << 8) | (where & 0xfc) | 0x80000000;
 218 +       bridge_w32(address, RALINK_PCI_CONFIG_ADDR);
 219 +       data = bridge_r32(RALINK_PCI_CONFIG_DATA_VIRT_REG);
 220 +
 221 +       switch (size) {
 222 +       case 1:
 223 +               data = (data & ~(0xff << ((where & 3) << 3))) |
 224 +                       (val << ((where & 3) << 3));
 225 +               break;
 226 +       case 2:
 227 +               data = (data & ~(0xffff << ((where & 3) << 3))) |
 228 +                       (val << ((where & 3) << 3));
 229 +               break;
 230 +       case 4:
 231 +               data = val;
 232 +               break;
 233 +       }
 234 +
 235 +       bridge_w32(data, RALINK_PCI_CONFIG_DATA_VIRT_REG);
 236 +
 237 +       return PCIBIOS_SUCCESSFUL;
 238 +}
 239 +
 240 +struct pci_ops mt7620_pci_ops= {
 241 +       .read   = pci_config_read,
 242 +       .write  = pci_config_write,
 243 +};
 244 +
 245 +static struct resource mt7620_res_pci_mem1;
 246 +static struct resource mt7620_res_pci_io1;
 247 +struct pci_controller mt7620_controller = {
 248 +       .pci_ops        = &mt7620_pci_ops,
 249 +       .mem_resource   = &mt7620_res_pci_mem1,
 250 +       .mem_offset     = 0x00000000UL,
 251 +       .io_resource    = &mt7620_res_pci_io1,
 252 +       .io_offset      = 0x00000000UL,
 253 +       .io_map_base    = 0xa0000000,
 254 +};
 255 +
 256 +static int mt7620_pci_hw_init(struct platform_device *pdev) {
 257 +       /* PCIE: bypass PCIe DLL */
 258 +       pcie_phy(0x0, 0x80);
 259 +       pcie_phy(0x1, 0x04);
 260 +
 261 +       /* PCIE: Elastic buffer control */
 262 +       pcie_phy(0x68, 0xB4);
 263 +
 264 +       pcie_m32(0, BIT(1), RALINK_PCI_PCICFG_ADDR);
 265 +
 266 +       reset_control_assert(rstpcie0);
 267 +
 268 +       rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
 269 +       rt_sysc_m32(BIT(19), BIT(31), PPLL_DRV);
 270 +
 271 +       reset_control_deassert(rstpcie0);
 272 +       rt_sysc_m32(0, RALINK_PCIE0_CLK_EN, RALINK_CLKCFG1);
 273 +
 274 +       mdelay(100);
 275 +
 276 +       if (!(rt_sysc_r32(PPLL_CFG1) & BIT(23))) {
 277 +               dev_err(&pdev->dev, "MT7620 PPLL unlock\n");
 278 +               reset_control_assert(rstpcie0);
 279 +               rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
 280 +               return -1;
 281 +       }
 282 +       rt_sysc_m32(BIT(18) | BIT(17), BIT(19) | BIT(31), PPLL_DRV);
 283 +
 284 +       return 0;
 285 +}
 286 +
 287 +static int mt7628_pci_hw_init(struct platform_device *pdev) {
 288 +       u32 val = 0;
 289 +
 290 +       rt_sysc_m32(BIT(16), 0, RALINK_GPIOMODE);
 291 +       reset_control_deassert(rstpcie0);
 292 +       rt_sysc_m32(0, RALINK_PCIE0_CLK_EN, RALINK_CLKCFG1);
 293 +       mdelay(100);
 294 +
 295 +       pcie_m32(~0xff, 0x5, RALINK_PCIEPHY_P0_CTL_OFFSET);
 296 +
 297 +       pci_config_read(NULL, 0, 0x70c, 4, &val);
 298 +       val &= ~(0xff) << 8;
 299 +       val |= 0x50 << 8;
 300 +       pci_config_write(NULL, 0, 0x70c, 4, val);
 301 +
 302 +       pci_config_read(NULL, 0, 0x70c, 4, &val);
 303 +       dev_err(&pdev->dev, "Port 0 N_FTS = %x\n", (unsigned int) val);
 304 +
 305 +       return 0;
 306 +}
 307 +
 308 +static int mt7620_pci_probe(struct platform_device *pdev)
 309 +{
 310 +       struct resource *bridge_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 311 +       struct resource *pcie_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 312 +       u32 val = 0;
 313 +
 314 +       rstpcie0 = devm_reset_control_get(&pdev->dev, "pcie0");
 315 +       if (IS_ERR(rstpcie0))
 316 +               return PTR_ERR(rstpcie0);
 317 +
 318 +       bridge_base = devm_ioremap_resource(&pdev->dev, bridge_res);
 319 +        if (!bridge_base)
 320 +               return -ENOMEM;
 321 +
 322 +       pcie_base = devm_ioremap_resource(&pdev->dev, pcie_res);
 323 +        if (!pcie_base)
 324 +               return -ENOMEM;
 325 +
 326 +       iomem_resource.start = 0;
 327 +       iomem_resource.end = ~0;
 328 +       ioport_resource.start = 0;
 329 +       ioport_resource.end = ~0;
 330 +
 331 +       /* bring up the pci core */
 332 +       switch (ralink_soc) {
 333 +       case MT762X_SOC_MT7620A:
 334 +               if (mt7620_pci_hw_init(pdev))
 335 +                       return -1;
 336 +               break;
 337 +
 338 +       case MT762X_SOC_MT7628AN:
 339 +               if (mt7628_pci_hw_init(pdev))
 340 +                       return -1;
 341 +               break;
 342 +
 343 +       default:
 344 +               dev_err(&pdev->dev, "pcie is not supported on this hardware\n");
 345 +               return -1;
 346 +       }
 347 +       mdelay(50);
 348 +
 349 +       /* enable write access */
 350 +       pcie_m32(BIT(1), 0, RALINK_PCI_PCICFG_ADDR);
 351 +       mdelay(100);
 352 +
 353 +       /* check if there is a card present */
 354 +       if ((pcie_r32(RALINK_PCI0_STATUS) & 0x1) == 0) {
 355 +               reset_control_assert(rstpcie0);
 356 +               rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
 357 +               if (ralink_soc == MT762X_SOC_MT7620A)
 358 +                       rt_sysc_m32(LC_CKDRVPD_, PDRV_SW_SET, PPLL_DRV);
 359 +               dev_err(&pdev->dev, "PCIE0 no card, disable it(RST&CLK)\n");
 360 +               return -1;
 361 +       }
 362 +
 363 +       /* setup ranges */
 364 +       bridge_w32(0xffffffff, RALINK_PCI_MEMBASE);
 365 +       bridge_w32(RALINK_PCI_IO_MAP_BASE, RALINK_PCI_IOBASE);
 366 +
 367 +       pcie_w32(0x7FFF0001, RALINK_PCI0_BAR0SETUP_ADDR);
 368 +       pcie_w32(MEMORY_BASE, RALINK_PCI0_IMBASEBAR0_ADDR);
 369 +       pcie_w32(0x06040001, RALINK_PCI0_CLASS);
 370 +
 371 +       /* enable interrupts */
 372 +       pcie_m32(0, BIT(20), RALINK_PCI_PCIMSK_ADDR);
 373 +
 374 +       /* voodoo from the SDK driver */
 375 +       pci_config_read(NULL, 0, 4, 4, &val);
 376 +       pci_config_write(NULL, 0, 4, 4, val | 0x7);
 377 +
 378 +       pci_load_of_ranges(&mt7620_controller, pdev->dev.of_node);
 379 +       register_pci_controller(&mt7620_controller);
 380 +
 381 +       return 0;
 382 +}
 383 +
 384 +int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 385 +{
 386 +       u16 cmd;
 387 +       u32 val;
 388 +       int irq = 0;
 389 +
 390 +       if ((dev->bus->number == 0) && (slot == 0)) {
 391 +               pcie_w32(0x7FFF0001, RALINK_PCI0_BAR0SETUP_ADDR); //open 7FFF:2G; ENABLE
 392 +               pci_config_write(dev->bus, 0, PCI_BASE_ADDRESS_0, 4, MEMORY_BASE);
 393 +               pci_config_read(dev->bus, 0, PCI_BASE_ADDRESS_0, 4, &val);
 394 +       } else if ((dev->bus->number == 1) && (slot == 0x0)) {
 395 +               irq = RALINK_INT_PCIE0;
 396 +       } else {
 397 +               dev_err(&dev->dev, "no irq found - bus=0x%x, slot = 0x%x\n", dev->bus->number, slot);
 398 +               return 0;
 399 +       }
 400 +       dev_err(&dev->dev, "card - bus=0x%x, slot = 0x%x irq=%d\n", dev->bus->number, slot, irq);
 401 +
 402 +       pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 0x14);  //configure cache line size 0x14
 403 +       pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xFF);  //configure latency timer 0x10
 404 +       pci_read_config_word(dev, PCI_COMMAND, &cmd);
 405 +
 406 +       // FIXME
 407 +       cmd = cmd | PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
 408 +       pci_write_config_word(dev, PCI_COMMAND, cmd);
 409 +       pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
 410 +       //pci_write_config_byte(dev, PCI_INTERRUPT_PIN, dev->irq);
 411 +
 412 +       return irq;
 413 +}
 414 +
 415 +int pcibios_plat_dev_init(struct pci_dev *dev)
 416 +{
 417 +       return 0;
 418 +}
 419 +
 420 +static const struct of_device_id mt7620_pci_ids[] = {
 421 +       { .compatible = "mediatek,mt7620-pci" },
 422 +       {},
 423 +};
 424 +MODULE_DEVICE_TABLE(of, mt7620_pci_ids);
 425 +
 426 +static struct platform_driver mt7620_pci_driver = {
 427 +       .probe = mt7620_pci_probe,
 428 +       .driver = {
 429 +               .name = "mt7620-pci",
 430 +               .owner = THIS_MODULE,
 431 +               .of_match_table = of_match_ptr(mt7620_pci_ids),
 432 +       },
 433 +};
 434 +
 435 +static int __init mt7620_pci_init(void)
 436 +{
 437 +       return platform_driver_register(&mt7620_pci_driver);
 438 +}
 439 +
 440 +arch_initcall(mt7620_pci_init);
 441 diff --git a/arch/mips/ralink/Kconfig b/arch/mips/ralink/Kconfig
 442 index c2778f2..2aa5e42 100644
 443 --- a/arch/mips/ralink/Kconfig
 444 +++ b/arch/mips/ralink/Kconfig
 445 @@ -43,6 +43,7 @@ choice
 446
 447         config SOC_MT7620
 448                 bool "MT7620/8"
 449 +               select HW_HAS_PCI
 450
 451         config SOC_MT7621
 452                 bool "MT7621"
 453 --
 454 1.7.10.4
 455