target/linux/realtek/dts-5.10/rtl8382_inaba_aml2-17gp.dts

   1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
   2
   3 #include "rtl838x.dtsi"
   4
   5 #include <dt-bindings/input/input.h>
   6 #include <dt-bindings/gpio/gpio.h>
   7
   8 / {
   9         compatible = "inaba,aml2-17gp", "realtek,rtl838x-soc";
  10         model = "INABA Abaniact AML2-17GP";
  11
  12         chosen {
  13                 bootargs = "console=ttyS0,115200";
  14         };
  15
  16         memory@0 {
  17                 device_type = "memory";
  18                 reg = <0x0 0x8000000>;
  19         };
  20
  21         keys {
  22                 compatible = "gpio-keys-polled";
  23                 poll-interval = <20>;
  24
  25                 reset {
  26                         label = "reset";
  27                         gpios = <&gpio0 24 GPIO_ACTIVE_LOW>;
  28                         linux,code = <KEY_RESTART>;
  29                 };
  30         };
  31 };
  32
  33 &gpio0 {
  34         indirect-access-bus-id = <0>;
  35 };
  36
  37 &spi0 {
  38         status = "okay";
  39
  40         flash@0 {
  41                 compatible = "jedec,spi-nor";
  42                 reg = <0>;
  43                 spi-max-frequency = <10000000>;
  44
  45                 partitions {
  46                         compatible = "fixed-partitions";
  47                         #address-cells = <1>;
  48                         #size-cells = <1>;
  49
  50                         partition@0 {
  51                                 label = "u-boot";
  52                                 reg = <0x0 0x80000>;
  53                                 read-only;
  54                         };
  55
  56                         partition@80000 {
  57                                 label = "u-boot-env";
  58                                 reg = <0x80000 0x10000>;
  59                                 read-only;
  60                         };
  61
  62                         partition@90000 {
  63                                 label = "u-boot-env2";
  64                                 reg = <0x90000 0x10000>;
  65                         };
  66
  67                         partition@a0000 {
  68                                 label = "jffs2_cfg";
  69                                 reg = <0xa0000 0x400000>;
  70                                 read-only;
  71                         };
  72
  73                         partition@4a0000 {
  74                                 label = "jffs2_log";
  75                                 reg = <0x4a0000 0x100000>;
  76                                 read-only;
  77                         };
  78
  79                         partition@5a0000 {
  80                                 compatible = "openwrt,uimage", "denx,uimage";
  81                                 label = "firmware";
  82                                 reg = <0x5a0000 0xd30000>;
  83                                 openwrt,ih-magic = <0x83800000>;
  84                         };
  85
  86                         partition@12d0000 {
  87                                 label = "runtime2";
  88                                 reg = <0x12d0000 0xd30000>;
  89                         };
  90                 };
  91         };
  92 };
  93
  94 &ethernet0 {
  95         mdio-bus {
  96                 compatible = "realtek,rtl838x-mdio";
  97                 regmap = <&ethernet0>;
  98                 #address-cells = <1>;
  99                 #size-cells = <0>;
 100
 101                 INTERNAL_PHY(8)
 102                 INTERNAL_PHY(9)
 103                 INTERNAL_PHY(10)
 104                 INTERNAL_PHY(11)
 105                 INTERNAL_PHY(12)
 106                 INTERNAL_PHY(13)
 107                 INTERNAL_PHY(14)
 108                 INTERNAL_PHY(15)
 109
 110                 EXTERNAL_PHY(16)
 111                 EXTERNAL_PHY(17)
 112                 EXTERNAL_PHY(18)
 113                 EXTERNAL_PHY(19)
 114                 EXTERNAL_PHY(20)
 115                 EXTERNAL_PHY(21)
 116                 EXTERNAL_PHY(22)
 117                 EXTERNAL_PHY(23)
 118
 119                 EXTERNAL_PHY(24)
 120         };
 121 };
 122
 123 &switch0 {
 124         ports {
 125                 #address-cells = <1>;
 126                 #size-cells = <0>;
 127
 128                 SWITCH_PORT(8, 1, internal)
 129                 SWITCH_PORT(9, 2, internal)
 130                 SWITCH_PORT(10, 3, internal)
 131                 SWITCH_PORT(11, 4, internal)
 132                 SWITCH_PORT(12, 5, internal)
 133                 SWITCH_PORT(13, 6, internal)
 134                 SWITCH_PORT(14, 7, internal)
 135                 SWITCH_PORT(15, 8, internal)
 136
 137                 SWITCH_PORT(16, 9, qsgmii)
 138                 SWITCH_PORT(17, 10, qsgmii)
 139                 SWITCH_PORT(18, 11, qsgmii)
 140                 SWITCH_PORT(19, 12, qsgmii)
 141                 SWITCH_PORT(20, 13, qsgmii)
 142                 SWITCH_PORT(21, 14, qsgmii)
 143                 SWITCH_PORT(22, 15, qsgmii)
 144                 SWITCH_PORT(23, 16, qsgmii)
 145
 146                 port@24 {
 147                         reg = <24>;
 148                         label = "wan";
 149                         phy-handle = <&phy24>;
 150                         phy-mode = "qsgmii";
 151                 };
 152
 153                 port@28 {
 154                         ethernet = <&ethernet0>;
 155                         reg = <28>;
 156                         phy-mode = "internal";
 157
 158                         fixed-link {
 159                                 speed = <1000>;
 160                                 full-duplex;
 161                         };
 162                 };
 163         };
 164 };