target/linux/realtek/dts-5.10/rtl839x.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
   2
   3 #include <dt-bindings/clock/rtl83xx-clk.h>
   4
   5 /dts-v1/;
   6
   7 #define STRINGIZE(s) #s
   8 #define LAN_LABEL(p, s) STRINGIZE(p ## s)
   9 #define SWITCH_PORT_LABEL(n) LAN_LABEL(lan, n)
  10
  11 #define INTERNAL_PHY(n) \
  12         phy##n: ethernet-phy@##n { \
  13                 reg = <##n>; \
  14                 compatible = "ethernet-phy-ieee802.3-c22"; \
  15                 phy-is-integrated; \
  16         };
  17
  18 #define EXTERNAL_PHY(n) \
  19         phy##n: ethernet-phy@##n { \
  20                 reg = <##n>; \
  21                 compatible = "ethernet-phy-ieee802.3-c22"; \
  22         };
  23
  24 #define EXTERNAL_SFP_PHY(n) \
  25         phy##n: ethernet-phy@##n { \
  26                 compatible = "ethernet-phy-ieee802.3-c22"; \
  27                 sfp; \
  28                 media = "fibre"; \
  29                 reg = <##n>; \
  30         };
  31
  32 #define SWITCH_PORT(n, s, m) \
  33         port@##n { \
  34                 reg = <##n>; \
  35                 label = SWITCH_PORT_LABEL(s) ; \
  36                 phy-handle = <&phy##n>; \
  37                 phy-mode = #m ; \
  38         };
  39
  40 #define SWITCH_SFP_PORT(n, s, m) \
  41         port@##n { \
  42                 reg = <##n>; \
  43                 label = SWITCH_PORT_LABEL(s) ; \
  44                 phy-handle = <&phy##n>; \
  45                 phy-mode = #m ; \
  46                 fixed-link { \
  47                         speed = <1000>; \
  48                         full-duplex; \
  49                 }; \
  50         };
  51
  52 / {
  53         #address-cells = <1>;
  54         #size-cells = <1>;
  55
  56         compatible = "realtek,rtl839x-soc";
  57
  58         osc: oscillator {
  59                 compatible = "fixed-clock";
  60                 #clock-cells = <0>;
  61                 clock-frequency = <25000000>;
  62         };
  63
  64         ccu: clock-controller {
  65                 compatible = "realtek,rtl8390-clock";
  66                 #clock-cells = <1>;
  67                 clocks = <&osc>;
  68                 clock-names = "ref_clk";
  69         };
  70
  71         cpus {
  72                 #address-cells = <1>;
  73                 #size-cells = <0>;
  74
  75                 cpu@0 {
  76                         compatible = "mips,mips34Kc";
  77                         reg = <0>;
  78                         clocks = <&ccu CLK_CPU>;
  79                         operating-points-v2 = <&cpu_opp_table>;
  80                 };
  81
  82                 cpu@1 {
  83                         compatible = "mips,mips34Kc";
  84                         reg = <1>;
  85                         clocks = <&ccu CLK_CPU>;
  86                         operating-points-v2 = <&cpu_opp_table>;
  87                 };
  88         };
  89
  90         cpu_opp_table: opp-table-0 {
  91                 compatible = "operating-points-v2";
  92                 opp-shared;
  93
  94                 opp00 {
  95                         opp-hz = /bits/ 64 <425000000>;
  96                 };
  97                 opp01 {
  98                         opp-hz = /bits/ 64 <450000000>;
  99                 };
 100                 opp02 {
 101                         opp-hz = /bits/ 64 <475000000>;
 102                 };
 103                 opp03 {
 104                         opp-hz = /bits/ 64 <500000000>;
 105                 };
 106                 opp04 {
 107                         opp-hz = /bits/ 64 <525000000>;
 108                 };
 109                 opp05 {
 110                         opp-hz = /bits/ 64 <550000000>;
 111                 };
 112                 opp06 {
 113                         opp-hz = /bits/ 64 <575000000>;
 114                 };
 115                 opp07 {
 116                         opp-hz = /bits/ 64 <600000000>;
 117                 };
 118                 opp08 {
 119                         opp-hz = /bits/ 64 <625000000>;
 120                 };
 121                 opp09 {
 122                         opp-hz = /bits/ 64 <650000000>;
 123                 };
 124                 opp10 {
 125                         opp-hz = /bits/ 64 <675000000>;
 126                 };
 127                 opp11 {
 128                         opp-hz = /bits/ 64 <700000000>;
 129                 };
 130                 opp12 {
 131                         opp-hz = /bits/ 64 <725000000>;
 132                 };
 133                 opp13 {
 134                         opp-hz = /bits/ 64 <750000000>;
 135                 };
 136         };
 137
 138         chosen {
 139                 bootargs = "console=ttyS0,115200";
 140         };
 141
 142         cpuintc: cpuintc {
 143                 compatible = "mti,cpu-interrupt-controller";
 144                 #address-cells = <0>;
 145                 #interrupt-cells = <1>;
 146                 interrupt-controller;
 147         };
 148
 149         soc: soc {
 150                 compatible = "simple-bus";
 151                 #address-cells = <1>;
 152                 #size-cells = <1>;
 153                 ranges = <0x0 0x18000000 0x10000>;
 154
 155                 intc: interrupt-controller@3000 {
 156                         compatible = "realtek,rtl8390-intc", "realtek,rtl-intc";
 157                         reg = <0x3000 0x18>, <0x3018 0x18>;
 158                         interrupt-controller;
 159                         #interrupt-cells = <2>;
 160
 161                         interrupt-parent = <&cpuintc>;
 162                         interrupts = <2>, <3>, <4>, <5>, <6>;
 163                 };
 164
 165                 spi0: spi@1200 {
 166                         compatible = "realtek,rtl8380-spi";
 167                         reg = <0x1200 0x100>;
 168
 169                         #address-cells = <1>;
 170                         #size-cells = <0>;
 171                 };
 172
 173                 uart0: uart@2000 {
 174                         compatible = "ns16550a";
 175                         reg = <0x2000 0x100>;
 176
 177                         clocks = <&ccu CLK_LXB>;
 178
 179                         interrupt-parent = <&intc>;
 180                         interrupts = <31 1>;
 181
 182                         reg-io-width = <1>;
 183                         reg-shift = <2>;
 184                         fifo-size = <1>;
 185                         no-loopback-test;
 186                 };
 187
 188                 uart1: uart@2100 {
 189                         pinctrl-names = "default";
 190                         pinctrl-0 = <&enable_uart1>;
 191
 192                         compatible = "ns16550a";
 193                         reg = <0x2100 0x100>;
 194
 195                         clocks = <&ccu CLK_LXB>;
 196
 197                         interrupt-parent = <&intc>;
 198                         interrupts = <30 2>;
 199
 200                         reg-io-width = <1>;
 201                         reg-shift = <2>;
 202                         fifo-size = <1>;
 203                         no-loopback-test;
 204
 205                         status = "disabled";
 206                 };
 207
 208                 gpio0: gpio-controller@3500 {
 209                         compatible = "realtek,rtl8390-gpio", "realtek,otto-gpio";
 210                         reg = <0x3500 0x20>;
 211
 212                         gpio-controller;
 213                         #gpio-cells = <2>;
 214                         ngpios = <24>;
 215
 216                         interrupt-controller;
 217                         #interrupt-cells = <2>;
 218                         interrupt-parent = <&intc>;
 219                         interrupts = <23 2>;
 220                 };
 221
 222                 watchdog0: watchdog@3150 {
 223                         compatible = "realtek,rtl8390-wdt";
 224                         reg = <0x3150 0xc>;
 225
 226                         realtek,reset-mode = "soc";
 227
 228                         clocks = <&ccu CLK_LXB>;
 229                         timeout-sec = <30>;
 230
 231                         interrupt-parent = <&intc>;
 232                         interrupt-names = "phase1", "phase2";
 233                         interrupts = <19 4>, <18 4>;
 234                 };
 235
 236         };
 237
 238         pinmux@1b000004 {
 239                 compatible = "pinctrl-single";
 240                 reg = <0x1b000004 0x4>;
 241
 242                 pinctrl-single,bit-per-mux;
 243                 pinctrl-single,register-width = <32>;
 244                 pinctrl-single,function-mask = <0x1>;
 245                 #pinctrl-cells = <2>;
 246
 247                 enable_uart1: pinmux_enable_uart1 {
 248                         pinctrl-single,bits = <0x0 0x1 0x3>;
 249                 };
 250         };
 251
 252         /* LED_GLB_CTRL */
 253         pinmux@1b0000e4 {
 254                 compatible = "pinctrl-single";
 255                 reg = <0x1b0000e4 0x4>;
 256
 257                 pinctrl-single,bit-per-mux;
 258                 pinctrl-single,register-width = <32>;
 259                 pinctrl-single,function-mask = <0x1>;
 260                 #pinctrl-cells = <2>;
 261
 262                 /* enable GPIO 0 */
 263                 pinmux_disable_sys_led: disable_sys_led {
 264                         pinctrl-single,bits = <0x0 0x0 0x4000>;
 265                 };
 266         };
 267
 268         ethernet0: ethernet@1b00a300 {
 269                 compatible = "realtek,rtl838x-eth";
 270                 reg = <0x1b00a300 0x100>;
 271
 272                 interrupt-parent = <&intc>;
 273                 interrupts = <24 3>;
 274
 275                 phy-mode = "internal";
 276
 277                 fixed-link {
 278                         speed = <1000>;
 279                         full-duplex;
 280                 };
 281         };
 282
 283         sram0: sram@9f000000 {
 284                 compatible = "mmio-sram";
 285                 reg = <0x9f000000 0x18000>;
 286                 #address-cells = <1>;
 287                 #size-cells = <1>;
 288                 ranges = <0 0x9f000000 0x18000>;
 289         };
 290
 291         switch0: switch@1b000000 {
 292                 status = "okay";
 293                 compatible = "realtek,rtl83xx-switch";
 294
 295                 interrupt-parent = <&intc>;
 296                 interrupts = <20 2>;
 297         };
 298 };