target/linux/realtek/files-5.10/arch/mips/include/asm/mach-rtl838x/irq.h

   1 // SPDX-License-Identifier: GPL-2.0-only
   2
   3 #ifndef _RTL83XX_IRQ_H_
   4 #define _RTL83XX_IRQ_H_
   5
   6 #define NR_IRQS 32
   7 #include_next <irq.h>
   8
   9 /* Global Interrupt Mask Register */
  10 #define RTL83XX_ICTL_GIMR       0x00
  11 /* Global Interrupt Status Register */
  12 #define RTL83XX_ICTL_GISR       0x04
  13
  14 #define RTL83XX_IRQ_CPU_BASE    0
  15 #define RTL83XX_IRQ_CPU_NUM     8
  16 #define RTL83XX_IRQ_ICTL_BASE   (RTL83XX_IRQ_CPU_BASE + RTL83XX_IRQ_CPU_NUM)
  17 #define RTL83XX_IRQ_ICTL_NUM    32
  18
  19 /* Cascaded interrupts */
  20 #define RTL83XX_ICTL1_IRQ       (RTL83XX_IRQ_CPU_BASE + 2)
  21 #define RTL83XX_ICTL2_IRQ       (RTL83XX_IRQ_CPU_BASE + 3)
  22 #define RTL83XX_ICTL3_IRQ       (RTL83XX_IRQ_CPU_BASE + 4)
  23 #define RTL83XX_ICTL4_IRQ       (RTL83XX_IRQ_CPU_BASE + 5)
  24 #define RTL83XX_ICTL5_IRQ       (RTL83XX_IRQ_CPU_BASE + 6)
  25
  26 /* Interrupt routing register */
  27 #define RTL83XX_IRR0            0x08
  28 #define RTL83XX_IRR1            0x0c
  29 #define RTL83XX_IRR2            0x10
  30 #define RTL83XX_IRR3            0x14
  31
  32 /* Cascade map */
  33 #define UART0_CASCADE           2
  34 #define UART1_CASCADE           1
  35 #define TC0_CASCADE             5
  36 #define TC1_CASCADE             1
  37 #define TC2_CASCADE             1
  38 #define TC3_CASCADE             1
  39 #define TC4_CASCADE             1
  40 #define OCPTO_CASCADE           1
  41 #define HLXTO_CASCADE           1
  42 #define SLXTO_CASCADE           1
  43 #define NIC_CASCADE             4
  44 #define GPIO_ABCD_CASCADE       4
  45 #define GPIO_EFGH_CASCADE       4
  46 #define RTC_CASCADE             4
  47 #define SWCORE_CASCADE          3
  48 #define WDT_IP1_CASCADE         4
  49 #define WDT_IP2_CASCADE         5
  50 #define USB_H2_CASCADE          1
  51
  52 /* Pack cascade map into interrupt routing registers */
  53 #define RTL83XX_IRR0_SETTING (\
  54         (UART0_CASCADE          << 28) | \
  55         (UART1_CASCADE          << 24) | \
  56         (TC0_CASCADE            << 20) | \
  57         (TC1_CASCADE            << 16) | \
  58         (OCPTO_CASCADE          << 12) | \
  59         (HLXTO_CASCADE          << 8)  | \
  60         (SLXTO_CASCADE          << 4)  | \
  61         (NIC_CASCADE            << 0))
  62 #define RTL83XX_IRR1_SETTING (\
  63         (GPIO_ABCD_CASCADE      << 28) | \
  64         (GPIO_EFGH_CASCADE      << 24) | \
  65         (RTC_CASCADE            << 20) | \
  66         (SWCORE_CASCADE         << 16))
  67 #define RTL83XX_IRR2_SETTING    0
  68 #define RTL83XX_IRR3_SETTING    0
  69
  70 /* On the RTL8390 there is no GPIO_EFGH and RTC IRQ */
  71 #define RTL8390_IRR1_SETTING (\
  72         (GPIO_ABCD_CASCADE      << 28) | \
  73         (SWCORE_CASCADE         << 16))
  74
  75 /* The RTL9300 has a different external IRQ numbering scheme */
  76 #define RTL9300_IRR0_SETTING (\
  77         (UART1_CASCADE          << 28) | \
  78         (UART0_CASCADE          << 24) | \
  79         (USB_H2_CASCADE         << 16) | \
  80         (NIC_CASCADE            << 0))
  81 #define RTL9300_IRR1_SETTING (\
  82         (SWCORE_CASCADE         << 28))
  83 #define RTL9300_IRR2_SETTING (\
  84         (GPIO_ABCD_CASCADE      << 20) | \
  85         (TC4_CASCADE            << 12) | \
  86         (TC3_CASCADE            << 8) | \
  87         (TC2_CASCADE            << 4) | \
  88         (TC1_CASCADE            << 0))
  89 #define RTL9300_IRR3_SETTING (\
  90         (TC0_CASCADE            << 28) | \
  91         (WDT_IP1_CASCADE        << 20))
  92
  93 #endif /* _RTL83XX_IRQ_H_ */