target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/rtl838x.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #ifndef _RTL838X_H
   4 #define _RTL838X_H
   5
   6 #include <net/dsa.h>
   7
   8 /*
   9  * Register definition
  10  */
  11 #define RTL838X_MAC_PORT_CTRL(port)             (0xd560 + (((port) << 7)))
  12 #define RTL839X_MAC_PORT_CTRL(port)             (0x8004 + (((port) << 7)))
  13 #define RTL930X_MAC_PORT_CTRL(port)             (0x3260 + (((port) << 6)))
  14 #define RTL930X_MAC_L2_PORT_CTRL(port)          (0x3268 + (((port) << 6)))
  15 #define RTL931X_MAC_PORT_CTRL(port)             (0x6004 + (((port) << 7)))
  16
  17 #define RTL838X_RST_GLB_CTRL_0                  (0x003c)
  18
  19 #define RTL838X_MAC_FORCE_MODE_CTRL             (0xa104)
  20 #define RTL839X_MAC_FORCE_MODE_CTRL             (0x02bc)
  21 #define RTL930X_MAC_FORCE_MODE_CTRL             (0xCA1C)
  22 #define RTL931X_MAC_FORCE_MODE_CTRL             (0x0DCC)
  23
  24 #define RTL838X_DMY_REG31                       (0x3b28)
  25 #define RTL838X_SDS_MODE_SEL                    (0x0028)
  26 #define RTL838X_SDS_CFG_REG                     (0x0034)
  27 #define RTL838X_INT_MODE_CTRL                   (0x005c)
  28 #define RTL838X_CHIP_INFO                       (0x00d8)
  29 #define RTL839X_CHIP_INFO                       (0x0ff4)
  30 #define RTL838X_PORT_ISO_CTRL(port)             (0x4100 + ((port) << 2))
  31 #define RTL839X_PORT_ISO_CTRL(port)             (0x1400 + ((port) << 3))
  32
  33 /* Packet statistics */
  34 #define RTL838X_STAT_PORT_STD_MIB               (0x1200)
  35 #define RTL839X_STAT_PORT_STD_MIB               (0xC000)
  36 #define RTL930X_STAT_PORT_MIB_CNTR              (0x0664)
  37 #define RTL838X_STAT_RST                        (0x3100)
  38 #define RTL839X_STAT_RST                        (0xF504)
  39 #define RTL930X_STAT_RST                        (0x3240)
  40 #define RTL931X_STAT_RST                        (0x7ef4)
  41 #define RTL838X_STAT_PORT_RST                   (0x3104)
  42 #define RTL839X_STAT_PORT_RST                   (0xF508)
  43 #define RTL930X_STAT_PORT_RST                   (0x3244)
  44 #define RTL931X_STAT_PORT_RST                   (0x7ef8)
  45 #define RTL838X_STAT_CTRL                       (0x3108)
  46 #define RTL839X_STAT_CTRL                       (0x04cc)
  47 #define RTL930X_STAT_CTRL                       (0x3248)
  48 #define RTL931X_STAT_CTRL                       (0x5720)
  49
  50 /* Registers of the internal Serdes of the 8390 */
  51 #define RTL8390_SDS0_1_XSG0                     (0xA000)
  52 #define RTL8390_SDS0_1_XSG1                     (0xA100)
  53 #define RTL839X_SDS12_13_XSG0                   (0xB800)
  54 #define RTL839X_SDS12_13_XSG1                   (0xB900)
  55 #define RTL839X_SDS12_13_PWR0                   (0xb880)
  56 #define RTL839X_SDS12_13_PWR1                   (0xb980)
  57
  58 /* Registers of the internal Serdes of the 8380 */
  59 #define RTL838X_SDS4_FIB_REG0                   (0xF800)
  60 #define RTL838X_SDS4_REG28                      (0xef80)
  61 #define RTL838X_SDS4_DUMMY0                     (0xef8c)
  62 #define RTL838X_SDS5_EXT_REG6                   (0xf18c)
  63
  64 /* VLAN registers */
  65 #define RTL838X_VLAN_CTRL                       (0x3A74)
  66 #define RTL838X_VLAN_PROFILE(idx)               (0x3A88 + ((idx) << 2))
  67 #define RTL838X_VLAN_PORT_EGR_FLTR              (0x3A84)
  68 #define RTL838X_VLAN_PORT_PB_VLAN               (0x3C00)
  69 #define RTL838X_VLAN_PORT_IGR_FLTR(port)        (0x3A7C + (((port >> 4) << 2)))
  70 #define RTL838X_VLAN_PORT_IGR_FLTR_0            (0x3A7C)
  71 #define RTL838X_VLAN_PORT_IGR_FLTR_1            (0x3A7C + 4)
  72 #define RTL838X_VLAN_PORT_TAG_STS_CTRL          (0xA530)
  73
  74 #define RTL839X_VLAN_PROFILE(idx)               (0x25C0 + (((idx) << 3)))
  75 #define RTL839X_VLAN_CTRL                       (0x26D4)
  76 #define RTL839X_VLAN_PORT_PB_VLAN               (0x26D8)
  77 #define RTL839X_VLAN_PORT_IGR_FLTR(port)        (0x27B4 + (((port >> 4) << 2)))
  78 #define RTL839X_VLAN_PORT_EGR_FLTR(port)        (0x27C4 + (((port >> 5) << 2)))
  79 #define RTL839X_VLAN_PORT_TAG_STS_CTRL          (0x6828)
  80
  81 #define RTL930X_VLAN_PROFILE_SET(idx)           (0x9c60 + (((idx) * 20)))
  82 #define RTL930X_VLAN_CTRL                       (0x82D4)
  83 #define RTL930X_VLAN_PORT_PB_VLAN               (0x82D8)
  84 #define RTL930X_VLAN_PORT_IGR_FLTR(port)        (0x83C0 + (((port >> 4) << 2)))
  85 #define RTL930X_VLAN_PORT_EGR_FLTR              (0x83C8)
  86 #define RTL930X_VLAN_PORT_TAG_STS_CTRL          (0xCE24)
  87
  88 #define RTL931X_VLAN_PROFILE_SET(idx)           (0x9800 + (((idx) * 28)))
  89 #define RTL931X_VLAN_CTRL                       (0x94E4)
  90 #define RTL931X_VLAN_PORT_IGR_FLTR(port)        (0x96B4 + (((port >> 4) << 2)))
  91 #define RTL931X_VLAN_PORT_EGR_FLTR(port)        (0x96C4 + (((port >> 5) << 2)))
  92 #define RTL931X_VLAN_PORT_TAG_CTRL              (0x4860)
  93
  94 /* Table access registers */
  95 #define RTL838X_TBL_ACCESS_CTRL_0               (0x6914)
  96 #define RTL838X_TBL_ACCESS_DATA_0(idx)          (0x6918 + ((idx) << 2))
  97 #define RTL838X_TBL_ACCESS_CTRL_1               (0xA4C8)
  98 #define RTL838X_TBL_ACCESS_DATA_1(idx)          (0xA4CC + ((idx) << 2))
  99
 100 #define RTL839X_TBL_ACCESS_CTRL_0               (0x1190)
 101 #define RTL839X_TBL_ACCESS_DATA_0(idx)          (0x1194 + ((idx) << 2))
 102 #define RTL839X_TBL_ACCESS_CTRL_1               (0x6b80)
 103 #define RTL839X_TBL_ACCESS_DATA_1(idx)          (0x6b84 + ((idx) << 2))
 104 #define RTL839X_TBL_ACCESS_CTRL_2               (0x611C)
 105 #define RTL839X_TBL_ACCESS_DATA_2(i)            (0x6120 + (((i) << 2)))
 106
 107 #define RTL930X_TBL_ACCESS_CTRL_0               (0xB340)
 108 #define RTL930X_TBL_ACCESS_DATA_0(idx)          (0xB344 + ((idx) << 2))
 109 #define RTL930X_TBL_ACCESS_CTRL_1               (0xB3A0)
 110 #define RTL930X_TBL_ACCESS_DATA_1(idx)          (0xB3A4 + ((idx) << 2))
 111 #define RTL930X_TBL_ACCESS_CTRL_2               (0xCE04)
 112 #define RTL930X_TBL_ACCESS_DATA_2(i)            (0xCE08 + (((i) << 2)))
 113
 114 #define RTL931X_TBL_ACCESS_CTRL_0               (0x8500)
 115 #define RTL931X_TBL_ACCESS_DATA_0(idx)          (0x8508 + ((idx) << 2))
 116 #define RTL931X_TBL_ACCESS_CTRL_1               (0x40C0)
 117 #define RTL931X_TBL_ACCESS_DATA_1(idx)          (0x40C4 + ((idx) << 2))
 118 #define RTL931X_TBL_ACCESS_CTRL_2               (0x8528)
 119 #define RTL931X_TBL_ACCESS_DATA_2(i)            (0x852C + (((i) << 2)))
 120 #define RTL931X_TBL_ACCESS_CTRL_3               (0x0200)
 121 #define RTL931X_TBL_ACCESS_DATA_3(i)            (0x0204 + (((i) << 2)))
 122 #define RTL931X_TBL_ACCESS_CTRL_4               (0x20DC)
 123 #define RTL931X_TBL_ACCESS_DATA_4(i)            (0x20E0 + (((i) << 2)))
 124 #define RTL931X_TBL_ACCESS_CTRL_5               (0x7E1C)
 125 #define RTL931X_TBL_ACCESS_DATA_5(i)            (0x7E20 + (((i) << 2)))
 126
 127 /* MAC handling */
 128 #define RTL838X_MAC_LINK_STS                    (0xa188)
 129 #define RTL839X_MAC_LINK_STS                    (0x0390)
 130 #define RTL930X_MAC_LINK_STS                    (0xCB10)
 131 #define RTL931X_MAC_LINK_STS                    (0x0EC0)
 132 #define RTL838X_MAC_LINK_SPD_STS(p)             (0xa190 + (((p >> 4) << 2)))
 133 #define RTL839X_MAC_LINK_SPD_STS(p)             (0x03a0 + (((p >> 4) << 2)))
 134 #define RTL930X_MAC_LINK_SPD_STS(p)             (0xCB18 + (((p >> 3) << 2)))
 135 #define RTL931X_MAC_LINK_SPD_STS(p)             (0x0ED0 + (((p >> 3) << 2)))
 136 #define RTL838X_MAC_LINK_DUP_STS                (0xa19c)
 137 #define RTL839X_MAC_LINK_DUP_STS                (0x03b0)
 138 #define RTL930X_MAC_LINK_DUP_STS                (0xCB28)
 139 #define RTL931X_MAC_LINK_DUP_STS                (0x0EF0)
 140 #define RTL838X_MAC_TX_PAUSE_STS                (0xa1a0)
 141 #define RTL839X_MAC_TX_PAUSE_STS                (0x03b8)
 142 #define RTL930X_MAC_TX_PAUSE_STS                (0xCB2C)
 143 #define RTL931X_MAC_TX_PAUSE_STS                (0x0EF8)
 144 #define RTL838X_MAC_RX_PAUSE_STS                (0xa1a4)
 145 #define RTL839X_MAC_RX_PAUSE_STS                (0x03c0)
 146 #define RTL930X_MAC_RX_PAUSE_STS                (0xCB30)
 147 #define RTL931X_MAC_RX_PAUSE_STS                (0x0F00)
 148
 149 /* MAC link state bits */
 150 #define FORCE_EN                                (1 << 0)
 151 #define FORCE_LINK_EN                           (1 << 1)
 152 #define NWAY_EN                                 (1 << 2)
 153 #define DUPLX_MODE                              (1 << 3)
 154 #define TX_PAUSE_EN                             (1 << 6)
 155 #define RX_PAUSE_EN                             (1 << 7)
 156
 157 /* EEE */
 158 #define RTL838X_MAC_EEE_ABLTY                   (0xa1a8)
 159 #define RTL838X_EEE_PORT_TX_EN                  (0x014c)
 160 #define RTL838X_EEE_PORT_RX_EN                  (0x0150)
 161 #define RTL838X_EEE_CLK_STOP_CTRL               (0x0148)
 162 #define RTL838X_EEE_TX_TIMER_GIGA_CTRL          (0xaa04)
 163 #define RTL838X_EEE_TX_TIMER_GELITE_CTRL        (0xaa08)
 164
 165 #define RTL839X_EEE_TX_TIMER_GELITE_CTRL        (0x042C)
 166 #define RTL839X_EEE_TX_TIMER_GIGA_CTRL          (0x0430)
 167 #define RTL839X_EEE_TX_TIMER_10G_CTRL           (0x0434)
 168 #define RTL839X_EEE_CTRL(p)                     (0x8008 + ((p) << 7))
 169 #define RTL839X_MAC_EEE_ABLTY                   (0x03C8)
 170
 171 #define RTL930X_MAC_EEE_ABLTY                   (0xCB34)
 172 #define RTL930X_EEE_CTRL(p)                     (0x3274 + ((p) << 6))
 173 #define RTL930X_EEEP_PORT_CTRL(p)               (0x3278 + ((p) << 6))
 174
 175 /* L2 functionality */
 176 #define RTL838X_L2_CTRL_0                       (0x3200)
 177 #define RTL839X_L2_CTRL_0                       (0x3800)
 178 #define RTL930X_L2_CTRL                         (0x8FD8)
 179 #define RTL931X_L2_CTRL                         (0xC800)
 180 #define RTL838X_L2_CTRL_1                       (0x3204)
 181 #define RTL839X_L2_CTRL_1                       (0x3804)
 182 #define RTL930X_L2_AGE_CTRL                     (0x8FDC)
 183 #define RTL931X_L2_AGE_CTRL                     (0xC804)
 184 #define RTL838X_L2_PORT_AGING_OUT               (0x3358)
 185 #define RTL839X_L2_PORT_AGING_OUT               (0x3b74)
 186 #define RTL930X_L2_PORT_AGE_CTRL                (0x8FE0)
 187 #define RTL931X_L2_PORT_AGE_CTRL                (0xc808)
 188 #define RTL838X_TBL_ACCESS_L2_CTRL              (0x6900)
 189 #define RTL839X_TBL_ACCESS_L2_CTRL              (0x1180)
 190 #define RTL930X_TBL_ACCESS_L2_CTRL              (0xB320)
 191 #define RTL930X_TBL_ACCESS_L2_METHOD_CTRL       (0xB324)
 192 #define RTL838X_TBL_ACCESS_L2_DATA(idx)         (0x6908 + ((idx) << 2))
 193 #define RTL839X_TBL_ACCESS_L2_DATA(idx)         (0x1184 + ((idx) << 2))
 194 #define RTL930X_TBL_ACCESS_L2_DATA(idx)         (0xab08 + ((idx) << 2))
 195 #define RTL838X_L2_TBL_FLUSH_CTRL               (0x3370)
 196 #define RTL839X_L2_TBL_FLUSH_CTRL               (0x3ba0)
 197 #define RTL930X_L2_TBL_FLUSH_CTRL               (0x9404)
 198 #define RTL931X_L2_TBL_FLUSH_CTRL               (0xCD9C)
 199
 200 #define RTL838X_L2_PORT_NEW_SALRN(p)            (0x328c + (((p >> 4) << 2)))
 201 #define RTL839X_L2_PORT_NEW_SALRN(p)            (0x38F0 + (((p >> 4) << 2)))
 202 #define RTL930X_L2_PORT_SALRN(p)                (0x8FEC + (((p >> 4) << 2)))
 203 #define RTL931X_L2_PORT_NEW_SALRN(p)            (0xC820 + (((p >> 4) << 2)))
 204 #define RTL838X_L2_PORT_NEW_SA_FWD(p)           (0x3294 + (((p >> 4) << 2)))
 205 #define RTL839X_L2_PORT_NEW_SA_FWD(p)           (0x3900 + (((p >> 4) << 2)))
 206 #define RTL930X_L2_PORT_NEW_SA_FWD(p)           (0x8FF4 + (((p / 10) << 2)))
 207 #define RTL931X_L2_PORT_NEW_SA_FWD(p)           (0xC830 + (((p / 10) << 2)))
 208
 209 #define RTL930X_ST_CTRL                         (0x8798)
 210
 211 #define RTL930X_L2_PORT_SABLK_CTRL              (0x905c)
 212 #define RTL930X_L2_PORT_DABLK_CTRL              (0x9060)
 213
 214 #define RTL838X_RMA_BPDU_FLD_PMSK               (0x4348)
 215 #define RTL930X_RMA_BPDU_FLD_PMSK               (0x9F18)
 216 #define RTL931X_RMA_BPDU_FLD_PMSK               (0x8950)
 217 #define RTL839X_RMA_BPDU_FLD_PMSK               (0x125C)
 218
 219 #define RTL838X_L2_PORT_LM_ACT(p)               (0x3208 + ((p) << 2))
 220 #define RTL838X_VLAN_PORT_FWD                   (0x3A78)
 221 #define RTL839X_VLAN_PORT_FWD                   (0x27AC)
 222 #define RTL930X_VLAN_PORT_FWD                   (0x834C)
 223 #define RTL838X_VLAN_FID_CTRL                   (0x3aa8)
 224
 225 /* Port Mirroring */
 226 #define RTL838X_MIR_CTRL                        (0x5D00)
 227 #define RTL838X_MIR_DPM_CTRL                    (0x5D20)
 228 #define RTL838X_MIR_SPM_CTRL                    (0x5D10)
 229
 230 #define RTL839X_MIR_CTRL                        (0x2500)
 231 #define RTL839X_MIR_DPM_CTRL                    (0x2530)
 232 #define RTL839X_MIR_SPM_CTRL                    (0x2510)
 233
 234 #define RTL930X_MIR_CTRL                        (0xA2A0)
 235 #define RTL930X_MIR_DPM_CTRL                    (0xA2C0)
 236 #define RTL930X_MIR_SPM_CTRL                    (0xA2B0)
 237
 238 #define RTL931X_MIR_CTRL                        (0xAF00)
 239 #define RTL931X_MIR_DPM_CTRL                    (0xAF30)
 240 #define RTL931X_MIR_SPM_CTRL                    (0xAF10)
 241
 242 /* Storm/rate control and scheduling */
 243 #define RTL838X_STORM_CTRL                      (0x4700)
 244 #define RTL839X_STORM_CTRL                      (0x1800)
 245 #define RTL838X_STORM_CTRL_LB_CTRL(p)           (0x4884 + (((p) << 2)))
 246 #define RTL838X_STORM_CTRL_BURST_PPS_0          (0x4874)
 247 #define RTL838X_STORM_CTRL_BURST_PPS_1          (0x4878)
 248 #define RTL838X_STORM_CTRL_BURST_0              (0x487c)
 249 #define RTL838X_STORM_CTRL_BURST_1              (0x4880)
 250 #define RTL839X_STORM_CTRL_LB_TICK_TKN_CTRL_0   (0x1804)
 251 #define RTL839X_STORM_CTRL_LB_TICK_TKN_CTRL_1   (0x1808)
 252 #define RTL838X_SCHED_CTRL                      (0xB980)
 253 #define RTL839X_SCHED_CTRL                      (0x60F4)
 254 #define RTL838X_SCHED_LB_TICK_TKN_CTRL_0        (0xAD58)
 255 #define RTL838X_SCHED_LB_TICK_TKN_CTRL_1        (0xAD5C)
 256 #define RTL839X_SCHED_LB_TICK_TKN_CTRL_0        (0x1804)
 257 #define RTL839X_SCHED_LB_TICK_TKN_CTRL_1        (0x1808)
 258 #define RTL839X_STORM_CTRL_SPCL_LB_TICK_TKN_CTRL (0x2000)
 259 #define RTL839X_IGR_BWCTRL_LB_TICK_TKN_CTRL_0   (0x1604)
 260 #define RTL839X_IGR_BWCTRL_LB_TICK_TKN_CTRL_1   (0x1608)
 261 #define RTL839X_SCHED_LB_TICK_TKN_CTRL          (0x60F8)
 262 #define RTL839X_SCHED_LB_TICK_TKN_PPS_CTRL      (0x6200)
 263 #define RTL838X_SCHED_LB_THR                    (0xB984)
 264 #define RTL839X_SCHED_LB_THR                    (0x60FC)
 265 #define RTL838X_SCHED_P_EGR_RATE_CTRL(p)        (0xC008 + (((p) << 7)))
 266 #define RTL838X_SCHED_Q_EGR_RATE_CTRL(p, q)     (0xC00C + (p << 7) + (((q) << 2)))
 267 #define RTL838X_STORM_CTRL_PORT_BC_EXCEED       (0x470C)
 268 #define RTL838X_STORM_CTRL_PORT_MC_EXCEED       (0x4710)
 269 #define RTL838X_STORM_CTRL_PORT_UC_EXCEED       (0x4714)
 270 #define RTL839X_STORM_CTRL_PORT_BC_EXCEED(p)    (0x180c + (((p >> 5) << 2)))
 271 #define RTL839X_STORM_CTRL_PORT_MC_EXCEED(p)    (0x1814 + (((p >> 5) << 2)))
 272 #define RTL839X_STORM_CTRL_PORT_UC_EXCEED(p)    (0x181c + (((p >> 5) << 2)))
 273 #define RTL838X_STORM_CTRL_PORT_UC(p)           (0x4718 + (((p) << 2)))
 274 #define RTL838X_STORM_CTRL_PORT_MC(p)           (0x478c + (((p) << 2)))
 275 #define RTL838X_STORM_CTRL_PORT_BC(p)           (0x4800 + (((p) << 2)))
 276 #define RTL839X_STORM_CTRL_PORT_UC_0(p)         (0x185C + (((p) << 3)))
 277 #define RTL839X_STORM_CTRL_PORT_UC_1(p)         (0x1860 + (((p) << 3)))
 278 #define RTL839X_STORM_CTRL_PORT_MC_0(p)         (0x19FC + (((p) << 3)))
 279 #define RTL839X_STORM_CTRL_PORT_MC_1(p)         (0x1a00 + (((p) << 3)))
 280 #define RTL839X_STORM_CTRL_PORT_BC_0(p)         (0x1B9C + (((p) << 3)))
 281 #define RTL839X_STORM_CTRL_PORT_BC_1(p)         (0x1BA0 + (((p) << 3)))
 282 #define RTL839X_TBL_ACCESS_CTRL_2               (0x611C)
 283 #define RTL839X_TBL_ACCESS_DATA_2(i)            (0x6120 + (((i) << 2)))
 284 #define RTL839X_IGR_BWCTRL_PORT_CTRL_10G_0(p)   (0x1618 + (((p) << 3)))
 285 #define RTL839X_IGR_BWCTRL_PORT_CTRL_10G_1(p)   (0x161C + (((p) << 3)))
 286 #define RTL839X_IGR_BWCTRL_PORT_CTRL_0(p)       (0x1640 + (((p) << 3)))
 287 #define RTL839X_IGR_BWCTRL_PORT_CTRL_1(p)       (0x1644 + (((p) << 3)))
 288 #define RTL839X_IGR_BWCTRL_CTRL_LB_THR          (0x1614)
 289
 290 /* Link aggregation (Trunking) */
 291 #define RTL839X_TRK_MBR_CTR                     (0x2200)
 292 #define RTL838X_TRK_MBR_CTR                     (0x3E00)
 293 #define RTL930X_TRK_MBR_CTRL                    (0xA41C)
 294 #define RTL931X_TRK_MBR_CTRL                    (0xB8D0)
 295
 296 /* Attack prevention */
 297 #define RTL838X_ATK_PRVNT_PORT_EN               (0x5B00)
 298 #define RTL838X_ATK_PRVNT_CTRL                  (0x5B04)
 299 #define RTL838X_ATK_PRVNT_ACT                   (0x5B08)
 300 #define RTL838X_ATK_PRVNT_STS                   (0x5B1C)
 301
 302 /* 802.1X */
 303 #define RTL838X_SPCL_TRAP_EAPOL_CTRL            (0x6988)
 304 #define RTL839X_SPCL_TRAP_EAPOL_CTRL            (0x105C)
 305
 306 /* QoS */
 307 #define RTL838X_QM_INTPRI2QID_CTRL              (0x5F00)
 308 #define RTL839X_QM_INTPRI2QID_CTRL(q)           (0x1110 + (q << 2))
 309 #define RTL839X_QM_PORT_QNUM(p)                 (0x1130 + (((p / 10) << 2)))
 310 #define RTL838X_PRI_SEL_PORT_PRI(p)             (0x5FB8 + (((p / 10) << 2)))
 311 #define RTL839X_PRI_SEL_PORT_PRI(p)             (0x10A8 + (((p / 10) << 2)))
 312 #define RTL838X_QM_PKT2CPU_INTPRI_MAP           (0x5F10)
 313 #define RTL839X_QM_PKT2CPU_INTPRI_MAP           (0x1154)
 314 #define RTL838X_PRI_SEL_CTRL                    (0x10E0)
 315 #define RTL839X_PRI_SEL_CTRL                    (0x10E0)
 316 #define RTL838X_PRI_SEL_TBL_CTRL(i)             (0x5FD8 + (((i) << 2)))
 317 #define RTL839X_PRI_SEL_TBL_CTRL(i)             (0x10D0 + (((i) << 2)))
 318 #define RTL838X_QM_PKT2CPU_INTPRI_0             (0x5F04)
 319 #define RTL838X_QM_PKT2CPU_INTPRI_1             (0x5F08)
 320 #define RTL838X_QM_PKT2CPU_INTPRI_2             (0x5F0C)
 321 #define RTL839X_OAM_CTRL                        (0x2100)
 322 #define RTL839X_OAM_PORT_ACT_CTRL(p)            (0x2104 + (((p) << 2)))
 323 #define RTL839X_RMK_PORT_DEI_TAG_CTRL(p)        (0x6A9C + (((p >> 5) << 2)))
 324 #define RTL839X_PRI_SEL_IPRI_REMAP              (0x1080)
 325 #define RTL838X_PRI_SEL_IPRI_REMAP              (0x5F8C)
 326 #define RTL839X_PRI_SEL_DEI2DP_REMAP            (0x10EC)
 327 #define RTL839X_PRI_SEL_DSCP2DP_REMAP_ADDR(i)   (0x10F0 + (((i >> 4) << 2)))
 328 #define RTL839X_RMK_DEI_CTRL                    (0x6AA4)
 329 #define RTL839X_WRED_PORT_THR_CTRL(i)           (0x6084 + ((i) << 2))
 330 #define RTL839X_WRED_QUEUE_THR_CTRL(q, i)       (0x6090 + ((q) * 12) + ((i) << 2))
 331 #define RTL838X_PRI_DSCP_INVLD_CTRL0            (0x5FE8)
 332 #define RTL838X_RMK_IPRI_CTRL                   (0xA460)
 333 #define RTL838X_RMK_OPRI_CTRL                   (0xA464)
 334 #define RTL838X_SCHED_P_TYPE_CTRL(p)            (0xC04C + (((p) << 7)))
 335 #define RTL838X_SCHED_LB_CTRL(p)                (0xC004 + (((p) << 7)))
 336 #define RTL838X_FC_P_EGR_DROP_CTRL(p)           (0x6B1C + (((p) << 2)))
 337
 338 /* Debug features */
 339 #define RTL930X_STAT_PRVTE_DROP_COUNTER0        (0xB5B8)
 340
 341 #define MAX_VLANS 4096
 342 #define MAX_LAGS 16
 343 #define MAX_PRIOS 8
 344 #define RTL930X_PORT_IGNORE 0x3f
 345 #define MAX_MC_GROUPS 512
 346 #define UNKNOWN_MC_PMASK (MAX_MC_GROUPS - 1)
 347
 348 enum phy_type {
 349         PHY_NONE = 0,
 350         PHY_RTL838X_SDS = 1,
 351         PHY_RTL8218B_INT = 2,
 352         PHY_RTL8218B_EXT = 3,
 353         PHY_RTL8214FC = 4,
 354         PHY_RTL839X_SDS = 5,
 355 };
 356
 357 struct rtl838x_port {
 358         bool enable;
 359         u64 pm;
 360         u16 pvid;
 361         bool eee_enabled;
 362         enum phy_type phy;
 363         bool is10G;
 364         bool is2G5;
 365         u8 sds_num;
 366         const struct dsa_port *dp;
 367 };
 368
 369 struct rtl838x_vlan_info {
 370         u64 untagged_ports;
 371         u64 tagged_ports;
 372         u8 profile_id;
 373         bool hash_mc_fid;
 374         bool hash_uc_fid;
 375         u8 fid;
 376 };
 377
 378 enum l2_entry_type {
 379         L2_INVALID = 0,
 380         L2_UNICAST = 1,
 381         L2_MULTICAST = 2,
 382         IP4_MULTICAST = 3,
 383         IP6_MULTICAST = 4,
 384 };
 385
 386 struct rtl838x_l2_entry {
 387         u8 mac[6];
 388         u16 vid;
 389         u16 rvid;
 390         u8 port;
 391         bool valid;
 392         enum l2_entry_type type;
 393         bool is_static;
 394         bool is_ip_mc;
 395         bool is_ipv6_mc;
 396         bool block_da;
 397         bool block_sa;
 398         bool suspended;
 399         bool next_hop;
 400         int age;
 401         u8 trunk;
 402         bool is_trunk;
 403         u8 stack_dev;
 404         u16 mc_portmask_index;
 405         u32 mc_gip;
 406         u32 mc_sip;
 407         u16 mc_mac_index;
 408         u16 nh_route_id;
 409         bool nh_vlan_target;  // Only RTL83xx: VLAN used for next hop
 410 };
 411
 412 struct rtl838x_nexthop {
 413         u16 id;         // ID in HW Nexthop table
 414         u32 ip;         // IP Addres of nexthop
 415         u32 dev_id;
 416         u16 port;
 417         u16 vid;
 418         u16 fid;
 419         u64 mac;
 420         u16 mac_id;
 421         u16 l2_id;      // Index of this next hop forwarding entry in L2 FIB table
 422         u16 if_id;
 423 };
 424
 425 struct rtl838x_switch_priv;
 426
 427 struct rtl838x_reg {
 428         void (*mask_port_reg_be)(u64 clear, u64 set, int reg);
 429         void (*set_port_reg_be)(u64 set, int reg);
 430         u64 (*get_port_reg_be)(int reg);
 431         void (*mask_port_reg_le)(u64 clear, u64 set, int reg);
 432         void (*set_port_reg_le)(u64 set, int reg);
 433         u64 (*get_port_reg_le)(int reg);
 434         int stat_port_rst;
 435         int stat_rst;
 436         int stat_port_std_mib;
 437         int (*port_iso_ctrl)(int p);
 438         void (*traffic_enable)(int source, int dest);
 439         void (*traffic_disable)(int source, int dest);
 440         void (*traffic_set)(int source, u64 dest_matrix);
 441         u64 (*traffic_get)(int source);
 442         int l2_ctrl_0;
 443         int l2_ctrl_1;
 444         int l2_port_aging_out;
 445         int smi_poll_ctrl;
 446         int l2_tbl_flush_ctrl;
 447         void (*exec_tbl0_cmd)(u32 cmd);
 448         void (*exec_tbl1_cmd)(u32 cmd);
 449         int (*tbl_access_data_0)(int i);
 450         int isr_glb_src;
 451         int isr_port_link_sts_chg;
 452         int imr_port_link_sts_chg;
 453         int imr_glb;
 454         void (*vlan_tables_read)(u32 vlan, struct rtl838x_vlan_info *info);
 455         void (*vlan_set_tagged)(u32 vlan, struct rtl838x_vlan_info *info);
 456         void (*vlan_set_untagged)(u32 vlan, u64 portmask);
 457         void (*vlan_profile_dump)(int index);
 458         void (*vlan_profile_setup)(int profile);
 459         void (*stp_get)(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[]);
 460         void (*stp_set)(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[]);
 461         int  (*mac_force_mode_ctrl)(int port);
 462         int  (*mac_port_ctrl)(int port);
 463         int  (*l2_port_new_salrn)(int port);
 464         int  (*l2_port_new_sa_fwd)(int port);
 465         int mir_ctrl;
 466         int mir_dpm;
 467         int mir_spm;
 468         int mac_link_sts;
 469         int mac_link_dup_sts;
 470         int  (*mac_link_spd_sts)(int port);
 471         int mac_rx_pause_sts;
 472         int mac_tx_pause_sts;
 473         u64 (*read_l2_entry_using_hash)(u32 hash, u32 position, struct rtl838x_l2_entry *e);
 474         void (*write_l2_entry_using_hash)(u32 hash, u32 pos, struct rtl838x_l2_entry *e);
 475         u64 (*read_cam)(int idx, struct rtl838x_l2_entry *e);
 476         void (*write_cam)(int idx, struct rtl838x_l2_entry *e);
 477         int vlan_port_egr_filter;
 478         int vlan_port_igr_filter;
 479         int vlan_port_pb;
 480         int vlan_port_tag_sts_ctrl;
 481         int (*rtl838x_vlan_port_tag_sts_ctrl)(int port);
 482         int (*trk_mbr_ctr)(int group);
 483         int rma_bpdu_fld_pmask;
 484         int spcl_trap_eapol_ctrl;
 485         void (*init_eee)(struct rtl838x_switch_priv *priv, bool enable);
 486         void (*port_eee_set)(struct rtl838x_switch_priv *priv, int port, bool enable);
 487         int (*eee_port_ability)(struct rtl838x_switch_priv *priv,
 488                                 struct ethtool_eee *e, int port);
 489         u64 (*l2_hash_seed)(u64 mac, u32 vid);
 490         u32 (*l2_hash_key)(struct rtl838x_switch_priv *priv, u64 seed);
 491         u64 (*read_mcast_pmask)(int idx);
 492         void (*write_mcast_pmask)(int idx, u64 portmask);
 493         void (*vlan_fwd_on_inner)(int port, bool is_set);
 494 };
 495
 496 struct rtl838x_switch_priv {
 497         /* Switch operation */
 498         struct dsa_switch *ds;
 499         struct device *dev;
 500         u16 id;
 501         u16 family_id;
 502         char version;
 503         struct rtl838x_port ports[57];
 504         struct mutex reg_mutex;
 505         int link_state_irq;
 506         int mirror_group_ports[4];
 507         struct mii_bus *mii_bus;
 508         const struct rtl838x_reg *r;
 509         u8 cpu_port;
 510         u8 port_mask;
 511         u8 port_width;
 512         u64 irq_mask;
 513         u32 fib_entries;
 514         int l2_bucket_size;
 515         struct dentry *dbgfs_dir;
 516         int n_lags;
 517         u64 lags_port_members[MAX_LAGS];
 518         struct net_device *lag_devs[MAX_LAGS];
 519         struct notifier_block nb;
 520         bool eee_enabled;
 521         unsigned long int mc_group_bm[MAX_MC_GROUPS >> 5];
 522 };
 523
 524 void rtl838x_dbgfs_init(struct rtl838x_switch_priv *priv);
 525
 526 #endif /* _RTL838X_H */