target/linux/sunxi/patches-3.14/182-clk-sunxi-add-support-for-usb-clockreg-reset.patch

   1 From 0643a93746775da2189ab0afd8f748afcaa791c5 Mon Sep 17 00:00:00 2001
   2 From: Hans de Goede <hdegoede@redhat.com>
   3 Date: Fri, 7 Feb 2014 16:21:49 +0100
   4 Subject: [PATCH] clk: sunxi: Add support for USB clock-register reset bits
   5 MIME-Version: 1.0
   6 Content-Type: text/plain; charset=UTF-8
   7 Content-Transfer-Encoding: 8bit
   8
   9 The usb-clk register is special in that it not only contains clk gate bits,
  10 but also has a few reset bits. This commit adds support for this by allowing
  11 gates type sunxi clks to also register a reset controller.
  12
  13 Signed-off-by: Hans de Goede <hdegoede@redhat.com>
  14 Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
  15 Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
  16 Signed-off-by: Emilio López <emilio@elopez.com.ar>
  17 ---
  18  drivers/clk/sunxi/clk-sunxi.c | 71 +++++++++++++++++++++++++++++++++++++++++++
  19  1 file changed, 71 insertions(+)
  20
  21 diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
  22 index 736fb60..23beb6e 100644
  23 --- a/drivers/clk/sunxi/clk-sunxi.c
  24 +++ b/drivers/clk/sunxi/clk-sunxi.c
  25 @@ -18,6 +18,7 @@
  26  #include <linux/clkdev.h>
  27  #include <linux/of.h>
  28  #include <linux/of_address.h>
  29 +#include <linux/reset-controller.h>
  30
  31  #include "clk-factors.h"
  32
  33 @@ -688,6 +689,59 @@ static void __init sunxi_divider_clk_setup(struct device_node *node,
  34
  35
  36  /**
  37 + * sunxi_gates_reset... - reset bits in leaf gate clk registers handling
  38 + */
  39 +
  40 +struct gates_reset_data {
  41 +       void __iomem                    *reg;
  42 +       spinlock_t                      *lock;
  43 +       struct reset_controller_dev     rcdev;
  44 +};
  45 +
  46 +static int sunxi_gates_reset_assert(struct reset_controller_dev *rcdev,
  47 +                             unsigned long id)
  48 +{
  49 +       struct gates_reset_data *data = container_of(rcdev,
  50 +                                                    struct gates_reset_data,
  51 +                                                    rcdev);
  52 +       unsigned long flags;
  53 +       u32 reg;
  54 +
  55 +       spin_lock_irqsave(data->lock, flags);
  56 +
  57 +       reg = readl(data->reg);
  58 +       writel(reg & ~BIT(id), data->reg);
  59 +
  60 +       spin_unlock_irqrestore(data->lock, flags);
  61 +
  62 +       return 0;
  63 +}
  64 +
  65 +static int sunxi_gates_reset_deassert(struct reset_controller_dev *rcdev,
  66 +                               unsigned long id)
  67 +{
  68 +       struct gates_reset_data *data = container_of(rcdev,
  69 +                                                    struct gates_reset_data,
  70 +                                                    rcdev);
  71 +       unsigned long flags;
  72 +       u32 reg;
  73 +
  74 +       spin_lock_irqsave(data->lock, flags);
  75 +
  76 +       reg = readl(data->reg);
  77 +       writel(reg | BIT(id), data->reg);
  78 +
  79 +       spin_unlock_irqrestore(data->lock, flags);
  80 +
  81 +       return 0;
  82 +}
  83 +
  84 +static struct reset_control_ops sunxi_gates_reset_ops = {
  85 +       .assert         = sunxi_gates_reset_assert,
  86 +       .deassert       = sunxi_gates_reset_deassert,
  87 +};
  88 +
  89 +/**
  90   * sunxi_gates_clk_setup() - Setup function for leaf gates on clocks
  91   */
  92
  93 @@ -695,6 +749,7 @@ static void __init sunxi_divider_clk_setup(struct device_node *node,
  94
  95  struct gates_data {
  96         DECLARE_BITMAP(mask, SUNXI_GATES_MAX_SIZE);
  97 +       u32 reset_mask;
  98  };
  99
 100  static const struct gates_data sun4i_axi_gates_data __initconst = {
 101 @@ -765,6 +820,7 @@ static void __init sunxi_gates_clk_setup(struct device_node *node,
 102                                          struct gates_data *data)
 103  {
 104         struct clk_onecell_data *clk_data;
 105 +       struct gates_reset_data *reset_data;
 106         const char *clk_parent;
 107         const char *clk_name;
 108         void *reg;
 109 @@ -808,6 +864,21 @@ static void __init sunxi_gates_clk_setup(struct device_node *node,
 110         clk_data->clk_num = i;
 111
 112         of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
 113 +
 114 +       /* Register a reset controler for gates with reset bits */
 115 +       if (data->reset_mask == 0)
 116 +               return;
 117 +
 118 +       reset_data = kzalloc(sizeof(*reset_data), GFP_KERNEL);
 119 +       if (!reset_data)
 120 +               return;
 121 +
 122 +       reset_data->reg = reg;
 123 +       reset_data->lock = &clk_lock;
 124 +       reset_data->rcdev.nr_resets = __fls(data->reset_mask) + 1;
 125 +       reset_data->rcdev.ops = &sunxi_gates_reset_ops;
 126 +       reset_data->rcdev.of_node = node;
 127 +       reset_controller_register(&reset_data->rcdev);
 128  }
 129
 130
 131 --
 132 2.0.3
 133